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Article

A Full Ka-Band CMOS Amplifier Using Inductive Neutralization with a Flat Gain of 13 ± 0.2 dB

School of Electrical Engineering, Korea University, Seoul 02841, Korea
*
Author to whom correspondence should be addressed.
Submission received: 24 March 2022 / Revised: 3 May 2022 / Accepted: 5 May 2022 / Published: 9 May 2022
(This article belongs to the Special Issue Recent Research in Microwave and Millimeter-Wave Components)

Abstract

:
This paper presents a CMOS wideband amplifier operating in the full Ka-band, with a low gain variation. An inductive neutralization is applied to the amplifier to compensate for the gain roll-off in the high-frequency region. Neutralization inductance is carefully determined considering the tradeoff between stability and gain. To achieve a low gain variation over the full Ka-band, the amplifier employs the frequency staggering technique in which impedance matching for three gain stages is performed at different frequencies of 26, 34, and 42 GHz. The experimental results show that a peak gain of 13.2 dB is achieved at 39.2 GHz. The 3 dB bandwidth is from 23.5 to 41.7 GHz, which fully covers the Ka-band. Especially, the gain ripple of the amplifier is only 13 ± 0.2 dB over a wide bandwidth from 26.2 to 40.2 GHz. The input and output return loss values are better than −10 dB from 26.3 to 40.1 GHz and from 25.3 to 50 GHz, respectively. The DC power consumption is 18.6 mW.

1. Introduction

Owing to the demand for high-speed data transfer, 5G communication based on the millimeter wave has been actively developed. The global spectrum allocated for the 5G millimeter wave is mainly distributed in the Ka-band (26.5–40 GHz) [1,2]. Therefore, a wideband flat-gain amplifier operating in the full Ka-band is needed for implementing multistandard or ultrawideband radio systems supporting the global spectrum.
Conventionally, wideband amplifiers operating at several gigahertz have been implemented using a resistive feedback technique [3,4,5]. The resistive feedback makes the input impedance more resistive, thereby allowing wideband input matching and enhancing the linearity [6]. However, a disadvantage of the resistive feedback is that the gain decreases in the upper end of the bandwidth [7]. Therefore, multiple amplifying stages must be cascaded to compensate for the gain roll-off, which increases the overall DC power consumption. Recently, a feedback technique based on a transformer balun was proposed to achieve a wideband gain response with a compact size [8,9]. However, the complicated structure of the transformer balun makes it challenging to optimize the transformer parameters such as the primary and secondary inductances and the coupling coefficient to achieve both the wideband input matching and flat-gain response at the same time.
This paper presents a full Ka-band amplifier with a low gain variation. In the first gain stage, the inductive neutralization is adopted to compensate for the gain roll-off in the upper end of the Ka-band, while the frequency staggering is employed in the subsequent gain stages for wideband and flat-gain responses. In Section 2, the analysis and design of the amplifier are presented. The experimental results are presented in Section 3. Finally, the conclusions are drawn in Section 4.

2. Circuit Analysis and Design

Figure 1 shows a schematic of the full Ka-band flat-gain CMOS amplifier using the inductive neutralization and frequency staggering techniques. Three common-source (CS) gain stages (M1, M2, and M3) were cascaded to secure a sufficient gain. To accomplish a wideband flat-gain response over the full Ka-band, the inductive neutralization was applied to the first stage, while the frequency staggering was employed in the following interstage and output matching networks.

2.1. Inductive Neutralization Technique

To achieve a high flat gain, the optimum transistor topology was determined first. Figure 2 shows the maximum stable gain (MSG) (or the maximum available gain (MAG)) [10] of various transistor topologies in the given 65 nm CMOS technology.
For a fair comparison, the simulation conditions were set identical: the gate width and drain bias current of each transistor are 30 μm and 3.1 mA, respectively. Among the CS, common-gate (CG), and cascade topologies, the CS topology provides the highest gain beyond 38 GHz. However, the gain of the CS still gradually decreases as the frequency increases further than 38 GHz. To achieve a flat gain over the full Ka-band, a gain-boosting technique should be used to compensate for the gain roll-off at the upper end of the Ka-band.
In this research, we adopted the inductive neutralization technique in the CS to boost the gain. It is well known that the gate-drain capacitance Cgd degrades the forward gain of the transistor [11]. Therefore, by connecting a neutralization inductor (Lneut) between the gate and drain, Cgd is resonated with the inductor, and thus the MSG (or MAG) can be boosted [12,13]. In Figure 2, the MSG (or MAG) of the CS topology with the inductive neutralization (Lneut = 1.3 nH) is shown, which is higher than that of other topologies beyond 31 GHz. Moreover, the inductive neutralization changes the behavior of the MSG (or MAG) over the frequency. It is observed in Figure 2 that the peak of the MSG (or MAG) is pushed to a higher frequency region and, thus, can be located almost at the upper end of the Ka-band. This offsets the high loss of passive matching components and the resulting gain roll-off at the high frequencies.
While boosting the gain by resonating out the feedback capacitance Cgd, the inductive neutralization may disrupt the stability of the transistor. This is because positive feedback can be reinforced when the Cgd–Lneut network operates far from the resonance. Therefore, the value of Lneut should be carefully determined considering a tradeoff between the gain and the stability. Figure 3 shows the simulated MSG (or MAG) and stability factor K at 39 GHz versus Lneut. The MSG (or MAG) has two peaks at Lneut = 1.23 and 1.44 nH, respectively. On the other hand, the K has a single peak at Lneut = 1.3 nH and decreases rapidly as Lneut deviates from 1.3 nH. The K becomes even below unity when Lneut < 1.23 nH or Lneut > 1.44 nH. Hence, we chose Lneut of 1.3 nH, which results in MAG of 15.1 dB and K of 11.2 at 39 GHz. Notably, both MAG and K are boosted by inductive neutralization. The inductive neutralization with Lneut of 1.3 nH was applied to the first gain stage (M1), which presents a high gain at the upper end of the Ka-band. It should be noted that the second and third gain stages (M2 and M3) have no inductive neutralization because they should present a high gain at lower frequencies, as described in Section 2.2.
The input matching of the amplifier should operate in a wide bandwidth to suppress mismatch loss that occurs in the interconnection with other circuit blocks. The inductive neutralization of the first gain stage alters the input impedance of M1; therefore, it should be considered in the input matching design shown in Figure 4. Specifically, the Cgd–Lneut network brings the load impedance of M1 (ZL1) to the input of M1 (Zin1) when the operation is off the resonance frequency. ZL1 includes the drain bias network of M1 (L3 and Cbypass), the input impedance looking into M2, and the interstage matching between M1 and M2. In Figure 5, the impedances of the input matching network are shown as the frequency is swept from 26 to 40 GHz. The Zin1 with no ZL1 and Lneut included is dominantly determined by the gate capacitance and resistance, as expected, shown in line (a). However, Zin1 with ZL1 included, shown in line (b), and with both ZL1 and Lneut included, shown in line (c), are substantially different from line (a). Fortunately, Lnuet induces a resonance behavior in Zin1, thereby providing a wideband characteristic to the input reflection coefficient. Finally, the input impedance at the port (Zin) is matched to 50 Ω with L1, C1, and L2, shown in line (d).

2.2. Frequency Staggering Technique

To achieve a flat gain over a wide frequency range, the center frequencies of three gain stages (M1, M2, and M3) are intentionally staggered. Through the interstage and output impedance matching described below, the peak-gain frequencies of the first, second, and third stages are tuned to 42, 25.5, and 30.5 GHz, respectively, as shown in Figure 6.
The ac equivalent circuit of the amplifier is drawn in Figure 7a. For the first interstage matching between M1 and M2, the impedances seen looking into the output of M1 (Zout1) and the input of M2 (Zin2) are simulated as Zout1 = 48.3 − j89.2 Ω and Zin2 = 14.2 − j71.9 Ω at 42 GHz. For conjugate matching, Zin2 is transformed to Zout1* by an L-section network consisting of L3, L4, and TL1. As shown in Figure 7b, the series inductive components (L4 and TL1) bring Zin2 to Zin2,1, which is located on a constant conductance circle of Re{1/Zout1*}. Then, a shunt inductor (L3) transforms Zin2,1 to Zin2,2, which completes the conjugate matching to Zout1*. It should be noted that the value of L3 determines the frequency at which the conjugate matching is satisfied. In Figure 7b, the locus of Zin2,2 at 42 GHz is depicted as L3 decreases from infinity to 0.1 nH. According to the plot, L3 is chosen as 0.8 nH to achieve conjugate matching at 42 GHz. The final matching point of Zin2,2 slightly deviates from Zout1* after fine optimization of the whole amplifier. The conjugate interstage matching between M1 and M2 at 42 GHz results in the gain peak of the first gain stage at the same frequency as that shown in Figure 6.
The second interstage matching between M2 and M3 is performed in a similar way to the first interstage matching. However, the matching frequency is intentionally changed to 26 GHz. As shown in Figure 7c, the input impedance of M3 (Zin3) is transformed to the conjugate of the output impedance of M2 (Zout2*). The center frequency of the matching is tuned to 26 GHz by choosing the value of a shunt inductor (L5) as 0.3 nH. It is noted that the second interstage matching is supposed to have the matching performance sensitive to the adjacent stages more than the first interstage matching. This is because the adjacent impedances are seen through Cgd of M2 and M3, while Cgd of M1 is diminished by the neutralization inductor Lneut. Therefore, an extra shunt inductor (L6) is added as an additional degree of design freedom in the second interstage matching while minimizing the influence on the adjacent matching. The second interstage matching results in the gain peak of the second stage at 25.5 GHz, as observed in Figure 6.
The output matching is fulfilled by L8 and L9 at 34 GHz, which leads to the peak gain of the final stage at 30.5 GHz shown in Figure 6. It is noted that there is a slight difference between the matching frequency and the peak gain frequency of each individual stage. This is because the gain and bandwidth of the whole amplifier were re-optimized after combining the individual stages.
Through the frequency staggering, the overall gain of the whole amplifier exhibits a flat response of 12.8 ± 0.5 dB from 25.6 to 42.4 GHz, covering the full Ka-band, as shown in Figure 6. After full electromagnetic simulation with Keysight ADS Momentum, the values of the matching components are slightly reoptimized considering the undesired magnetic and electric coupling between matching components and interconnection lines. The design parameter values of the full Ka-band amplifier are listed in Table 1.

3. Experimental Results

The full Ka-band amplifier was fabricated using a 65 nm CMOS technology. The chip micrograph is shown in Figure 8. The whole chip area including the probing pads and the core chip area were 1 × 0.7 and 0.5 × 0.75 mm 2 , respectively.
The measured S-parameters are shown in Figure 9. A peak gain of 13.2 dB was measured at 39.2 GHz. The 3 dB bandwidth was 18.2 GHz from 23.5 to 41.7 GHz, which covered the entire Ka-band frequencies. Specifically, from 26.2 to 40.2 GHz, the gain exhibited a flat response with a small variation, i.e., 13 ± 0.2 dB. The measured |S11| and |S22| were smaller than −10 dB from 26.3 to 40.1 GHz. The stability K-factor was calculated from the measured S-parameters, as shown in Figure 10. It was observed that the Ka-band amplifier was stable over the frequencies from DC to 50 GHz, which include both the operation and the out-of-band frequencies. The measured group delay is shown in Figure 11. The group delay was fairly flat in the frequency range between 22 and 46 GHz. The power measurement of the amplifier at 34 GHz is shown in Figure 12. The input 1 dB compression point (IP1dB) was −13.2 dBm. Figure 13 shows the measured IP1dB over the frequency. The IP1dB ranged from −13.2 to −16.6 dBm between 26 and 40 GHz.
In Table 2, the measured performances are summarized and compared with those of the previously reported CMOS Ka-band amplifiers. The amplifier in this study exhibited a superior gain flatness in the full Ka-band frequencies to the other state-of-the-art amplifiers.

4. Conclusions

In this research, a full Ka-band amplifier with a flat-gain response was fabricated using a 65 nm CMOS technology. To compensate for the gain roll-off in the upper end of the bandwidth, an inductive neutralization technique was used in the first stage. Neutralization inductance was carefully determined by considering gain and stability. To achieve a wideband flat gain, three CS stages designed at different center frequencies of 26, 34, and 42 GHz were cascaded. Using the frequency staggering technique, we found that the whole amplifier exhibited a flat-gain response of 13 ± 0.2 dB over the full Ka-band frequencies.

Author Contributions

Conceptualization, B.K. and S.J.; methodology, B.K. and S.J.; investigation, B.K. and S.J.; data curation, B.K. and S.J.; formal analysis, B.K. and S.J.; writing—original draft preparation, B.K.; writing—review and editing, S.J.; supervision, S.J.; project administration, S.J.; funding acquisition, S.J. All authors have read and agreed to the published version of the manuscript.

Funding

This study was supported by the Institute of Information and Communications Technology Planning and Evaluation (IITP) grant funded by the Korean government (MSIT) (No. 2021-0-00260, Research on LEO Inter-Satellite Links).

Institutional Review Board Statement

Not applicable.

Informed Consent Statement

Not applicable.

Data Availability Statement

Not applicable.

Acknowledgments

The authors would like to thank the IC Design Education Center (IDEC), Korea, for the chip fabrication and EDA tool support.

Conflicts of Interest

The authors declare no conflict of interest.

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Figure 1. Schematic of the full Ka-band amplifier with flat gain.
Figure 1. Schematic of the full Ka-band amplifier with flat gain.
Applsci 12 04782 g001
Figure 2. Comparison of MSG (or MAG) of different transistor topologies in a 65 nm CMOS technology.
Figure 2. Comparison of MSG (or MAG) of different transistor topologies in a 65 nm CMOS technology.
Applsci 12 04782 g002
Figure 3. Simulated MSG (or MAG) and stability factor K at 39 GHz versus Lneut.
Figure 3. Simulated MSG (or MAG) and stability factor K at 39 GHz versus Lneut.
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Figure 4. Input matching network of the first gain stage.
Figure 4. Input matching network of the first gain stage.
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Figure 5. Loci of the input impedances from 26 to 40 GHz.
Figure 5. Loci of the input impedances from 26 to 40 GHz.
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Figure 6. Gain of the three individual stages and the whole amplifier.
Figure 6. Gain of the three individual stages and the whole amplifier.
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Figure 7. Interstage matching: (a) AC equivalent circuit of the amplifier; (b) first interstage matching at 42 GHz; (c) second interstage matching at 26 GHz.
Figure 7. Interstage matching: (a) AC equivalent circuit of the amplifier; (b) first interstage matching at 42 GHz; (c) second interstage matching at 26 GHz.
Applsci 12 04782 g007aApplsci 12 04782 g007b
Figure 8. Chip micrograph of the full Ka-band amplifier.
Figure 8. Chip micrograph of the full Ka-band amplifier.
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Figure 9. Measured S-parameters of the full Ka-band amplifier.
Figure 9. Measured S-parameters of the full Ka-band amplifier.
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Figure 10. Stability factor based on the measured S-parameters.
Figure 10. Stability factor based on the measured S-parameters.
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Figure 11. Measured group delay.
Figure 11. Measured group delay.
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Figure 12. Measured output power and gain versus input power at 34 GHz.
Figure 12. Measured output power and gain versus input power at 34 GHz.
Applsci 12 04782 g012
Figure 13. Measured IP1dB versus frequency.
Figure 13. Measured IP1dB versus frequency.
Applsci 12 04782 g013
Table 1. Design parameter values of the full Ka-band amplifier.
Table 1. Design parameter values of the full Ka-band amplifier.
ParametersValuesParametersValues
L10.6 nHC10.41 pF
L20.68 nHR1200 Ω
L30.8 nHR21000 Ω
L40.45 nHTL1265 μm
L50.3 nHTL2120 μm
L60.7 nHM1–M31 × 30 μm
L70.2 nHVg11.1 V
L80.65 nHVg21.1 V
L90.27 nHVg30.9 V
Lneut1.3 nHVd11.1 V
Cbypass1.36 pFVd21.1 V
Cdc1.36 pFVd31.1 V
Table 2. Performance comparison with previous CMOS-based Ka-band amplifiers.
Table 2. Performance comparison with previous CMOS-based Ka-band amplifiers.
Ref.TechnologyPeak Gain
(dB)
|S21|3-dB BW
(GHz)
|S11|−10 dB BW
(GHz)
Gain Flatness
over Frequency
IP1dB
(dBm)
DC Power
Consumption (mW)
Core
Chip Area **
( m m 2 )
This work65-nm
CMOS
13.218.2
(23.5–41.7)
13.8
(26.3–40.1)
13 ± 0.2 dB over
26.2–40.2 GHz
−13.218.60.37
[8]65-nm
CMOS
13.523.4
(19.2–42.6)
22.1
(16.8–38.9)
12.65 ± 0.85 dB over
21–41 GHz *
−9.86.360.13
[14]65-nm
CMOS
22.18.5
(24–32.5)
10
(30–40 *)
20.6 ± 1.5 dB over
24–32.5 GHz
−1919.30.12
[15]22 nm SOI CMOS12.617
(23–40)
6
(25–31 *)
20.6 ± 1.5 dB over
24–32.5 GHz
−6130.12
[16]22 nm SOI CMOS18.219
(24–43)
24
(20–44 *)
18 ± 1.1 dB over
24–29 GHz
−20.412.10.21
[17]28-nm
CMOS
18.64.3
(28.2–32.5 *)
7
(30–37)
17.1 ± 1.5 dB over
28.2–32.5 GHz
−259.70.23
[18]40-nm
CMOS
18.49.3
(25–34.3 *)
14
(26–40)
16.9 ± 1.5 dB over
25–34.3 GHz *
−13.421.50.26
[19]45 nm SOI
CMOS
2020
(27–47.5 *)
19
(27–48)
19 ± 1.5 dB over
27–47.5 GHz
−19580.2
[20]90 nm SOI
CMOS
13.815
(29–44)
21
(29–50 *)
12.3 ± 1.5 dB over
29–44 GHz
−10180.48 ***
* Estimated from a plot of the article; ** excluding probing pads; *** including probing pads.
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Kim, B.; Jeon, S. A Full Ka-Band CMOS Amplifier Using Inductive Neutralization with a Flat Gain of 13 ± 0.2 dB. Appl. Sci. 2022, 12, 4782. https://0-doi-org.brum.beds.ac.uk/10.3390/app12094782

AMA Style

Kim B, Jeon S. A Full Ka-Band CMOS Amplifier Using Inductive Neutralization with a Flat Gain of 13 ± 0.2 dB. Applied Sciences. 2022; 12(9):4782. https://0-doi-org.brum.beds.ac.uk/10.3390/app12094782

Chicago/Turabian Style

Kim, Byungwook, and Sanggeun Jeon. 2022. "A Full Ka-Band CMOS Amplifier Using Inductive Neutralization with a Flat Gain of 13 ± 0.2 dB" Applied Sciences 12, no. 9: 4782. https://0-doi-org.brum.beds.ac.uk/10.3390/app12094782

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