A Virtual Impedance Control Strategy for Improving the Stability and Dynamic Performance of VSC–HVDC Operation in Bidirectional Power Flow Mode

Abstract

It is a common practice that one converter controls DC voltage and the other controls power in two-terminal voltage source converter (VSC)–based high voltage DC (HVDC) systems for AC gird interconnection. The maximum transmission power from a DC-voltage-controlled converter to a power-controlled converter is less than that of the opposite transmission direction. In order to increase the transmission power from a DC-voltage-controlled converter to a power-controlled converter, an improved virtual impedance control strategy is proposed in this paper. Based on the proposed control strategy, the DC impedance model of the VSC–HVDC system is built, including the output impedance of two converters and DC cable impedance. The stability of the system with an improved virtual impedance control is analyzed in Nyquist stability criterion. The proposed control strategy can improve the transmission capacity of the system by changing the DC output impedance of the DC voltage-controlled converter. The effectiveness of the proposed control strategy is verified by simulation. The simulation results show that the proposed control strategy has better dynamic performance than traditional control strategies.

1. Introduction

With the development of power electronic devices, VSC–HVDC systems have been widely applied to AC grid interconnection because of their independent decoupling control of active and reactive power [1,2,3]. Recently, a large number of studies on modeling, control, and stability analysis of VSC–HVDC system have been published [4,5,6,7,8,9,10]. Previous studies have shown that the interaction between converters or between the converter and the grid influences the stability of a system. DC- side oscillation is a problem in VSC–HVDC and has been reported in a real project [11]. When DC side oscillation occurs, a DC system will not work and will impact on the power system. Therefore, the DC-side stability of VSC–HVDC should be evaluated before connecting it to the main grid.

In VSC–HVDC systems applied to AC grid interconnection, active power often needs bidirectional transmission [12]. However, studies show that the maximum transmission power of the DC-voltage-controlled converter to power-controlled converter is less than that in the opposite power flow direction [13]. An Impedance-based approach can be adopted to analyze the influence of VSC–HVDC systems with different directions of transmission power on stability [13].

The impedance stability criterion was proposed in [14] and used in grid-connected inverters [15]. It was applied as a stability criterion in a VSC–HVDC system [12,16,17,18,19]. The impedance model of two-terminal VSC–HVDCs was built in [12], and the cause of DC current resonance was analyzed with Nyquist stability criteria. Different subsystems were selected to analyze the DC-side stability of the VSC–HVDC system with a transfer function method in [16]. The influence of overhead transmission lines, DC cables, and the DC-side filter on system stability was investigated in [17]. The different performances of the lumped parameter and distributed parameter circuit models in stability analysis were discussed in [18]. It was found that the distributed parameter circuit model is more accurate in stability analysis.

In the condition of VSC–HVDC for AC Grid interconnection, the maximum transmission capacities of the different power flow directions are different. Thus, a control strategy is required to improve the transmission capacity from the DC-voltage-controlled converter to the power-controlled converter to improve resource utilization efficiency. To increase the maximum transmission power, the DC side oscillation must be suppressed. The suppression methods of DC side oscillation can be classified into passive methods [20,21] and active methods [22,23,24,25,26,27,28,29]. Passive methods suppress resonance by introducing a passive damper branch into the circuit to remodel the impedance of the source converter or load converter in a cascaded system. Active methods suppress resonance by introducing voltage and current feedback control in a controller to improve the impedance of the source converter or load converter. Virtual impedance is widely used in control systems as an active damping control method [24,25,26,27,28,29]. It can be introduced to suppress DC-side oscillation [24,25], to limit output current for voltage controlled inverters during overloads or faults [26,27], to improve the stability of a grid-connected inverter by change its input admittance [28], and to enhance the small-signal stability of a modular multilevel converter (MMC) based DC grid [29].

Virtual impedance in the DC voltage control loop can suppress the DC-side oscillation of a VSC–HVDC transmission system and improve its stability margin and the transmission capacity of the system [24,25]. However, virtual impedance control leads to steady-state errors in the DC output voltage of DC-voltage-controlled converters, due to different operating points [25]. An improved virtual impedance control strategy is proposed in this paper. To design an appropriate control strategy, a stability analysis is required. Thus, a DC impedance-based model of VSC–HVDC is built, and the stability of the system is analyzed based on impedance stability criteria.

The rest of the paper is organized as follows: Section 2 describes the system’s structure and the simulation of a VSC–HVDC system, as well as the design of an improved virtual impedance control. Section 3 presents the impedance model of an HVDC system. Section 4 conducts a stability analysis on the basis of impedance stability criteria, and Section 5 shows the simulation verification. Section 6 summarizes the proposed method.

2. Improved Virtual Impedance Control Principle

This paper mainly studies a two-level topology structure. The analysis in this paper can be also applicable to an MMC system if the dc bus voltage ripples are insignificant [12]. A two-level VSC–HVDC system used in AC grid interconnection is depicted in Figure 1. Figure 1 shows a DC voltage-controlled converter and a power-controlled converter on the left and right sides, respectively. The two converters have an identical structure. R_n1 + jX_n1 and R_n2 + jX_n2 are the equivalent impedance of the AC system, R_c1 + jω₁L₁ and R_c2 + jω₂L_c2 are the impedance of the filter reactor, C_f1 and C_f2 are the filter capacitors, ${\stackrel{·}{m}}_{{}_1}$ and $\stackrel{·}{m_{{}_2}}$ are the modulations of the converter station, ${\stackrel{·}{u}}_{s1}$ and ${\stackrel{·}{u}}_{s2}$ are the AC voltage at point of common coupling, ${\stackrel{·}{u}}_{g1}$ and ${\stackrel{·}{u}}_{g2}$ are the AC voltage of the AC system, ${\stackrel{·}{i}}_{s1}$ and ${\stackrel{·}{i}}_{s2}$ are the AC current flowing through the filter reactor, and ${\stackrel{·}{i}}_{g1}$ and ${\stackrel{·}{i}}_{g2}$ are the AC current flowing through the AC system. The DC cable is a π type, with an equivalent resistance of R_d, an equivalent inductance of L_d, and an equivalent capacitance of C_d.

The modeling and control of the VSC–HVDC system are presented in a synchronous rotating frame (SRF). The transformation of the three-phase quantity from stationary reference frame to the SRF is based on the amplitude-invariant Park transformation, with the d-axis aligned with the voltage vector u_s and q-axis leading the d-axis by 90°. The grid voltage defines the system’s dq reference. A phase-locked loop (PLL) defines the controller dq reference. The system reference is aligned with the PLL reference in a steady state. When a small disturbance occurs, the system reference is no longer aligned with the PLL reference. The relationship between the system reference and the PLL reference under a small disturbance is shown in Figure 2.

Here, subscript dq represent the components of the physical quantity in the SRF. Subscript 0 represents the value of the physical quantity at the static working point, subscript ref represents the given value of physical quantity, and subscript Δ represents the small disturbance components of the physical quantity. Superscript c represents the components of physical quantity in the PLL reference, and superscript s represents the components in the system reference.

The simulation model of VSC–HVDC in Figure 1 is built on a MATLAB/Simulink. The system parameters are shown in the following table. The vector current control [13] is adopted in the two converters, and the control is shown in Figure 3. For symmetry of the VSC–HVDC system, subscripts 1,2 of the system parameters in

Table 1. Simulation parameters.

Parameters		Values
Converter and AC system	System capacity Sn/MW	500
	Line voltage of grid ug/kV	110
	DC voltage Vdc/kV	250
	Grid internal resistance Rn/Ω	0.2
	Grid frequency ω0/Hz	50
	Grid internal inductance Ln/H	1 × 10−3
	Filter reactor inductance Lc/H	4.5 × 10−2
	Filter reactor resistance Rc/Ω	0.2
	DC side capacitance Cdc/μf	300
DC cable	DC cable resistance Rd/Ω/km	1.39 × 10−2
	DC cable inductance Ld/H/km	1.59 × 10−4
	DC cable capacitance Cd/F/km	2.31 × 10−7
Controller	DC voltage outer loop kpvdc/kivdc	15/100
	Current inner loop kpc/kic	0.5/0.1
	Active power outer loop kpp/kip	1/10
	Phase locked loop kpPLL/kiPLL	10/100

and the control diagram in Figure 3 are omitted. In the model, controller parameters are per unit. The base angular grid frequency is 50 Hz, the base grid voltage is 110 kV, the base system capacity is 500 MW, and the base DC voltage is 250 kV. According to the parameters in Table 1, the system’s closed-loop bandwidth with a DC voltage controller is 65 Hz, and the system’s open-loop phase margin is 58 degrees. The system’s closed-loop bandwidth with an active power controller is 8 Hz, and the system’s open-loop phase margin is 150 degrees. The system’s closed-loop bandwidth with the current controller is 180 Hz, and the system’s open-loop phase margin is 85 degrees.

The power flow direction from the power-controlled converter to the DC voltage-controlled converter is set to positive. Figure 4 shows the resulting time-domain responses of the DC voltage of the VSC–HVDC system. At 2 s, the active power instruction value steps from 500 MW to −500 MW, and the length of the DC cable is 50 km. It can be observed that the DC voltage starts to oscillate, the active power starts to fluctuate, and the system loses stability.

The power-controlled converter exhibits a constant power load (CPL) when the active power is transmitted from the DC-voltage controlled converter to the power-controlled converter. The incremental input resistance characteristic caused by CPL affects the stability of the VSC–HVDC system [24].

A virtual impedance control strategy is introduced in the DC-voltage-controlled converter to mitigate the DC-side oscillation caused by the negative incremental input resistance characteristic of the power-controlled converter. The expression of the virtual impedance control is

$$v_{dcref}=v_{dcn}-(R_{eq}+s{L}_{eq})i_{dc}$$

(1)

where v_dcref is the DC voltage reference value, v_dcn is the no-load DC voltage of the converter, and R_eq and L_eq are the set values for the virtual impedance. Due to the addition of current feedback, under loaded conditions, there will be a fixed steady-state error between the DC voltage reference value and the measured value, which almost equals $R_{eq}\ast i_{dc}$. Thus, the steady-state error increases with an increase in the transmission power (in both power flow directions).

In order to eliminate the steady-state error caused by virtual impedance, this paper modifies the voltage control loop, as shown by the blue dotted line frame in Figure 5.

$$i_{dcn}=\frac{k_i}{s}(v_{dcn}-v_{dc})$$

(2)

$$v_{dcref}=v_{dcn}-(R_{eq}+s{L}_{eq})(i_{dc}-i_{dcn})$$

(3)

3. Impedance Model of Converters with Improved Virtual Impedance Control Strategy

3.1. DC-Side Impedance Modeling of DC-Voltage-Controlled Converter

The linearized dynamic equations of the DC voltage-controlled converter are expressed as

$$\left[\begin{array}{l}{m}_{d0}\\ m_{q0}\end{array}\right]\mathsf{\Delta }{v}_{dc}+v_{dc0}\left[\begin{array}{l}\mathsf{\Delta }{m}_d^s\\ \mathsf{\Delta }{m}_q^s\end{array}\right]+Z_0(s)\left[\begin{array}{l}\mathsf{\Delta }{i}_{sd}^s\\ \mathsf{\Delta }{i}_{sq}^s\end{array}\right]=\left[\begin{array}{l}\mathsf{\Delta }{u}_{sd}^s\\ \mathsf{\Delta }{u}_{sq}^s\end{array}\right]$$

(4)

$$\left[\begin{array}{l}\mathsf{\Delta }{u}_{sd}^s\\ \mathsf{\Delta }{u}_{sq}^s\end{array}\right]=-Z_g(s)\left[\begin{array}{l}\mathsf{\Delta }{i}_{gd}^s\\ \mathsf{\Delta }{i}_{gq}^s\end{array}\right]$$

(5)

$$\left[\begin{array}{l}\mathsf{\Delta }{i}_{gd}^s\\ \mathsf{\Delta }{i}_{gq}^s\end{array}\right]=\left[\begin{array}{l}\mathsf{\Delta }{i}_{sd}^s\\ \mathsf{\Delta }{i}_{sq}^s\end{array}\right]+Y_{cf}(s)\left[\begin{array}{l}\mathsf{\Delta }{u}_{sd}^s\\ \mathsf{\Delta }{u}_{sq}^s\end{array}\right]$$

(6)

where

$$Z_0=\left[\begin{array}{cc}{R}_c+s{L}_c& -{\omega }_0{L}_c\\ {\omega }_0{L}_c& R_c+s{L}_c\end{array}\right]$$

(7)

$$Z_g=\left[\begin{array}{cc}{R}_n+s{L}_n& -{\omega }_0{L}_n\\ {\omega }_0{L}_n& R_n+s{L}_n\end{array}\right]$$

(8)

$$Y_{cf}(s)=\left[\begin{array}{cc}s{C}_f& -{\omega }_0{C}_f\\ {\omega }_0{C}_f& s{C}_f\end{array}\right]$$

(9)

Its controller and modulator linearized equations are expressed as

$$\left[\begin{array}{l}\mathsf{\Delta }{i}_{sd,ref}\\ \mathsf{\Delta }{i}_{sq,ref}\end{array}\right]=\left[\begin{array}{c}{k}_{pvdc}+\frac{k_{ivdc}}{s}\\ 0\end{array}\right](\mathsf{\Delta }{v}_{dcref}-\mathsf{\Delta }{v}_{dc})$$

(10)

$$v_{dc0}\left[\begin{array}{l}\mathsf{\Delta }{m}_d^c\\ \mathsf{\Delta }{m}_q^c\end{array}\right]=-G_{pwm}{G}_{cc}\left[\begin{array}{l}\mathsf{\Delta }{i}_{sd,ref}\\ \mathsf{\Delta }{i}_{sq,ref}\end{array}\right]+G_{pwm}\left[\begin{array}{l}\mathsf{\Delta }{u}_{sd}^c\\ \mathsf{\Delta }{u}_{sq}^c\end{array}\right]+G_{pwm}\left(G_{cc}+Z_{del}\right)\left[\begin{array}{l}\mathsf{\Delta }{i}_{sd}^c\\ \mathsf{\Delta }{i}_{sq}^c\end{array}\right]$$

(11)

where k_pvdc and k_ivdc are the proportional and integral gains of the DC voltage controller, respectively, G_pwm is the PWM delay, and G_cc is the current compensator transfer function, where k_pc and k_ic are the proportional and integral gains of the current compensator, respectively.

$$G_{pwm}=\left[\begin{array}{cc}{H}_{pwm}& 0\\ 0& H_{pwm}\end{array}\right]$$

(12)

$$H_{pwm}=e^{-s{T}_s}\frac{1-e^{-s{T}_s}}{s{T}_s}$$

(13)

$$G_{cc}=\left[\begin{array}{cc}{k}_{pc}+\frac{k_{ic}}{s}& 0\\ 0& k_{pc}+\frac{k_{ic}}{s}\end{array}\right]$$

(14)

$$Z_{del}=\left[\begin{array}{cc}0& {\omega }_{pLL}{L}_c\\ -{\omega }_{pLL}{L}_c& 0\end{array}\right]$$

(15)

The variables of the controller are based on the output of the PLL reference, whereas the variables of the circuit are based on the system reference. The relationship of physical quantity between the PLL and the system references is expressed as [13]

$$\left[\begin{array}{l}\mathsf{\Delta }{i}_{sd}^{\mathrm{c}}\\ \mathsf{\Delta }{i}_{sq}^{\mathrm{c}}\end{array}\right]=\left[\begin{array}{l}\mathsf{\Delta }{i}_{sd}^s\\ \mathsf{\Delta }{i}_{sq}^s\end{array}\right]+\stackrel{G_{PLL}^i}{\overbrace{\left[\begin{array}{cc}0& G_{PLL}(s)i_{sq0}\\ 0& -G_{PLL}(s)i_{sd0}\end{array}\right]}}\left[\begin{array}{l}\mathsf{\Delta }{u}_{sd}^s\\ \mathsf{\Delta }{u}_{sq}^s\end{array}\right]$$

(16)

$$\left[\begin{array}{l}\mathsf{\Delta }{u}_{\mathrm{s}d}^{\mathrm{c}}\\ \mathsf{\Delta }{u}_{\mathrm{s}q}^{\mathrm{c}}\end{array}\right]=\stackrel{G_{PLL}^v}{\overbrace{\left[\begin{array}{cc}1& G_{PLL}(s)u_{sq0}\\ 0& 1-G_{PLL}(s)u_{sd0}\end{array}\right]}}\left[\begin{array}{l}\mathsf{\Delta }{u}_{\mathrm{s}d}^{\mathrm{s}}\\ \mathsf{\Delta }{u}_{\mathrm{s}q}^{\mathrm{s}}\end{array}\right]$$

(17)

$$\left[\begin{array}{l}\mathsf{\Delta }{m}_d^c\\ \mathsf{\Delta }{m}_q^c\end{array}\right]=\left[\begin{array}{l}\mathsf{\Delta }{m}_d^s\\ \mathsf{\Delta }{m}_q^s\end{array}\right]-\stackrel{G_{PLL}^d}{\overbrace{\left[\begin{array}{cc}0& -G_{PLL}(s)m_{q0}\\ 0& G_{PLL}(s)m_{d0}\end{array}\right]}}\left[\begin{array}{l}\mathsf{\Delta }{u}_{sd}^s\\ \mathsf{\Delta }{u}_{sq}^s\end{array}\right]$$

(18)

where

$$t{f}_{PLL}=k_{pPLL}+\frac{k_{iPLL}}{s}$$

(19)

$$G_{PLL}=\frac{t{f}_{pLL}}{s+u_{sd0}{f}_{PLL}}$$

(20)

Here, tf_PLL is the PLL transfer function and k_pPLL and k_iPLL are the proportional and integral gains of the PLL compensator, respectively.

The linearized equation of the power balance between the AC and DC sides of the converter is expressed as

$$\mathsf{\Delta }{i}_{dc}=1.5(\left[\begin{array}{cc}{m}_{d0}& m_{q10}\end{array}\right]\left[\begin{array}{l}\mathsf{\Delta }{i}_{sd}^s\\ \mathsf{\Delta }{i}_{sq}^s\end{array}\right]+\left[\begin{array}{cc}{i}_{sd0}& i_{sq0}\end{array}\right]\left[\begin{array}{l}\mathsf{\Delta }{m}_d^s\\ \mathsf{\Delta }{m}_q^s\end{array}\right])$$

(21)

The small signal expression of the improved virtual impedance compensator is expressed as

$$\mathsf{\Delta }{i}_{dcn}=-\frac{k_i}{s}\mathsf{\Delta }{v}_d{}_c$$

(22)

$$\mathsf{\Delta }{v}_{dcref}=-(R_{eq}+s{L}_{eq})(\frac{k_i}{s}\mathsf{\Delta }{v}_d{}_c+\mathsf{\Delta }{i}_{dc}).$$

(23)

Inserting (22) and (23) into (10), the relation between the AC current reference values $\mathsf{\Delta }{i}_{sd,ref}$, $\mathsf{\Delta }{i}_{sq,ref}$, DC voltage $\mathsf{\Delta }{v}_d{}_c$, and DC current $\mathsf{\Delta }{i}_{dc}$ is expressed as

$$\left[\begin{array}{l}\mathsf{\Delta }{i}_{sd,ref}\\ \mathsf{\Delta }{i}_{sq,ref}\end{array}\right]=\left[\begin{array}{cc}{H}_{vdc}& H_{idc}\\ 0& 0\end{array}\right]\left[\begin{array}{l}\mathsf{\Delta }{v}_{dc}\\ \mathsf{\Delta }{i}_{dc}\end{array}\right]$$

(24)

where

$$H_{vdc}=-(k_{pvdc}+\frac{k_{ivdc}}{s})(\frac{k_i{R}_{eq}}{s}+k_i{L}_{eq}+1)$$

(25)

$$H_{idc}=-(k_{pvdc}+\frac{k_{ivdc}}{s})(R_{eq}+s{L}_{eq})$$

(26)

Formula (5) can be written as

$$\left[\begin{array}{l}\mathsf{\Delta }{i}_{gd}^s\\ \mathsf{\Delta }{i}_{gq}^s\end{array}\right]=-Y_g(s)\left[\begin{array}{l}\mathsf{\Delta }{u}_{sd}^s\\ \mathsf{\Delta }{u}_{sq}^s\end{array}\right].$$

(27)

Inserting (27) into (6), the relation between the AC voltage and AC current can be given as

$$\left[\begin{array}{l}\mathsf{\Delta }{u}_{sd}^s\\ \mathsf{\Delta }{u}_{sq}^s\end{array}\right]=\stackrel{Z_s}{\overbrace{{(Y_{cf}(s)-Y_g(s))}^{-1}}}\left[\begin{array}{l}\mathsf{\Delta }{i}_{sd}^s\\ \mathsf{\Delta }{i}_{sq}^s\end{array}\right].$$

(28)

Considering PLL, inserting (16)–(18) and (28) into (11), the modulation index can be written as

$$\left[\begin{array}{l}\mathsf{\Delta }{m}_d^s\\ \mathsf{\Delta }{m}_q^s\end{array}\right]v_{dc0}=-G_{pwm}{G}_{cc}\left[\begin{array}{cc}{H}_{vdc}& H_{idc}\\ 0& 0\end{array}\right]\left[\begin{array}{l}\mathsf{\Delta }{v}_{dc}\\ \mathsf{\Delta }{i}_{dc}\end{array}\right]+G_z^{vdc}(s)\left[\begin{array}{l}\mathsf{\Delta }{i}_{sd}^s\\ \mathsf{\Delta }{i}_{sq}^s\end{array}\right]$$

(29)

where

$$G_z^{vdc}(s)=G_{pwm}\left(G_{cc}+Z_{del}\right)+Z_s(s)G_c^i.$$

(30)

$$G_c^i=(G_{pwm}{G}_{PLL}^v+G_{pwm}\left(G_{cc}+Z_{del}\right)G_{PLL}^i+v_{dc0}{G}_{PLL}^d)$$

(31)

The relation between the DC voltage, DC current, and AC currents can be obtained from (4) by inserting (28) and (29):

$$Y_{AC}^{Vdc}(s)\left[\begin{array}{l}\mathsf{\Delta }{v}_{dc}\\ \mathsf{\Delta }{i}_{dc}\end{array}\right]=\left[\begin{array}{l}\mathsf{\Delta }{i}_{sd}^s\\ \mathsf{\Delta }{i}_{sq}^s\end{array}\right]$$

(32)

where

$$Y_{AC}^{Vdc}(s)={(Z_s(s)-Z_0(s)-G_z^{vdc}(s))}^{-1}(\left[\begin{array}{cc}{m}_{d0}& 0\\ m_{q0}& 0\end{array}\right]+G_{pwm}{G}_{cc1}\left[\begin{array}{cc}{H}_{vdc}& H_{idc}\\ 0& 0\end{array}\right])$$

(33)

and $Y_{AC}^{Vdc}$ can be expressed as a 2*2 order matrix:

$$Y_{AC}^{Vdc}=\left[\begin{array}{cc}{Y}_1& Y_2\\ Y_3& Y_4\end{array}\right]$$

(34)

Inserting (32) into (4), yields

$$\left[\begin{array}{l}\mathsf{\Delta }{m}_d^s\\ \mathsf{\Delta }{m}_q^s\end{array}\right]=\frac{1}{v_{dc0}}((Z_s(s)-Z_0(s))Y_{AC}^{Vdc}(s)-\left[\begin{array}{cc}{m}_{d0}& 0\\ m_{q0}& 0\end{array}\right])\left[\begin{array}{l}\mathsf{\Delta }{v}_{dc}\\ \mathsf{\Delta }{i}_{dc}\end{array}\right].$$

(35)

In the power balance relation, by inserting (34) and (35) into (21), (21) can be replaced by

$$\begin{array}{l}\mathsf{\Delta }{i}_{dc}=1.5\left[\begin{array}{cc}{m}_{d0}& m_{q0}\end{array}\right]\left[\begin{array}{l}\mathsf{\Delta }{i}_{sd}^s\\ \mathsf{\Delta }{i}_{sq}^s\end{array}\right]+1.5\left[\begin{array}{cc}{i}_{sd0}& i_{sq0}\end{array}\right]\left[\begin{array}{l}\mathsf{\Delta }{m}_d^s\\ \mathsf{\Delta }{m}_q^s\end{array}\right]=1.5\left[\begin{array}{cc}{m}_{d0}& m_{q0}\end{array}\right]Y_{AC}^{Vdc}(s)\left[\begin{array}{l}\mathsf{\Delta }{v}_{dc}\\ \mathsf{\Delta }{i}_{dc}\end{array}\right]+\\ 1.5\left[\begin{array}{cc}{i}_{sd0}& i_{sq0}\end{array}\right]\frac{1}{v_{dc0}}((Z_s(s)-Z_0(s))Y_{AC}^{Vdc}(s)-\left[\begin{array}{cc}{m}_{d10}& 0\\ m_{q10}& 0\end{array}\right])\left[\begin{array}{l}\mathsf{\Delta }{v}_{dc}\\ \mathsf{\Delta }{i}_{dc}\end{array}\right]=M_1\mathsf{\Delta }{v}_{dc}+M_2\mathsf{\Delta }{i}_{dc}\end{array}$$

(36)

where

$$\begin{array}{c}{M}_1=1.5m_{d0}{Y}_1+1.5m_{q0}{Y}_3+\frac{1.5}{v_{dc0}}{i}_{sd0}(R{Y}_1+sL{Y}_1-{\omega }_{0}L{Y}_3-m_{d0})+\\ i_{sq0}(R{Y}_3+sL{Y}_3-{\omega }_{0}L{Y}_1-m_{q0})\end{array}$$

(37)

$$M_2=1.5m_{q0}{Y}_2+\frac{1.5}{v_{dc0}}{i}_{sd0}(R{Y}_2+sL{Y}_2-i_{sq0}{\omega }_{0}L{Y}_4)+i_{sq0}(R{Y}_2+sL{Y}_2-{\omega }_{0}L{Y}_4)$$

(38)

$$R=R_n-R_c$$

(39)

$$L=L_n-L_c$$

(40)

The DC impedance of the converters can be calculated by solving (36) and can be expressed as

$$Z_{dc\mathrm{r}}=\frac{1-M_2}{M_1}.$$

(41)

Consider the DC-side capacitor,

$$Z_{dc1}=\frac{Z_{dcr}}{1+s{C}_{dc}{Z}_{dcr}}.$$

(42)

3.2. DC Side Impedance Modeling of the Power-Controlled Converter

The linearized dynamic equations of the power-controlled converter are the same as those of the DC-voltage-controlled converter, which are expressed as (4)–(6), and its outer loop controller linearized equation is expressed as

$$\left[\begin{array}{l}\mathsf{\Delta }{i}_{sd,ref}\\ \mathsf{\Delta }{i}_{sq,ref}\end{array}\right]=-H_p(\stackrel{G_{vp}}{\overbrace{\left[\begin{array}{cc}1.5u_{sd0}& 1.5u_{sq0}\\ 0& 0\end{array}\right]}}\left[\begin{array}{l}\mathsf{\Delta }{i}_{sd}^c\\ \mathsf{\Delta }{i}_{sq}^c\end{array}\right]+\stackrel{G_{ip}}{\overbrace{\left[\begin{array}{cc}1.5i_{sd0}& 1.5i_{sq0}\\ 0& 0\end{array}\right]}}\left[\begin{array}{l}\mathsf{\Delta }{u}_{sd}^c\\ \mathsf{\Delta }{u}_{sq}^c\end{array}\right])$$

(43)

where $H_p=k_{pp}+k_{ip}/s$ is the active power compensator and k_pp and k_ip are the proportional and integral gains of the compensator. Its current compensator and modulator is same as (11). Inserting (16)–(18) into (42) gives

$$\left[\begin{array}{l}\mathsf{\Delta }{i}_{sd,ref}\\ \mathsf{\Delta }{i}_{sq,ref}\end{array}\right]=-H_p{G}_{vp}\left[\begin{array}{l}\mathsf{\Delta }{i}_{sd}^s\\ \mathsf{\Delta }{i}_{sq}^s\end{array}\right]-(H_p{G}_{vp}{G}_{PLL}^i+H_p{G}_{ip}{G}_{PLL}^i)\left[\begin{array}{l}\mathsf{\Delta }{u}_{sd}^s\\ \mathsf{\Delta }{u}_{sq}^s\end{array}\right].$$

(44)

Inserting (16)–(18) and (28) into (11), the relation between the modulation index and AC current can be expressed as

$$\begin{array}{c}\left[\begin{array}{l}\mathsf{\Delta }{m}_d^s\\ \mathsf{\Delta }{m}_q^s\end{array}\right]v_{dc0}=(G_{pwm}{G}_{cc}{H}_p{G}_{vp}+G_{pwm}(G_{cc}+Z_{del}))\left[\begin{array}{l}\mathsf{\Delta }{i}_{sd}^s\\ \mathsf{\Delta }{i}_{sq}^s\end{array}\right]+\\ (G_{pwm}{G}_{cc}{H}_p(G_{vp}{G}_{PLL}^i+G_{ip}{G}_{PLL}^v)+G_C^i)\left[\begin{array}{l}\mathsf{\Delta }{u}_{sd}^s\\ \mathsf{\Delta }{u}_{sq}^s\end{array}\right]\end{array}$$

(45)

where

$$G_C^i=G_{PLL}^d+G_{pwm}{G}_{PLL}^v+G_{pwm}(G_{cc}+Z_{del})G_{PLL}^i.$$

(46)

Equation (45) can be rewritten as

$$\left[\begin{array}{l}\mathsf{\Delta }{m}_d^s\\ \mathsf{\Delta }{m}_q^s\end{array}\right]v_{dc0}=G_Z^P\left[\begin{array}{l}\mathsf{\Delta }{i}_{sd}^s\\ \mathsf{\Delta }{i}_{sq}^s\end{array}\right].$$

(47)

Inserting (47) and (28) into (4) yields

$$\stackrel{Y_{AC}^P}{\overbrace{{(Z_s(s)-Z_0(s)-G_Z^P(s))}^{-1}\left[\begin{array}{c}{m}_{d0}\\ m_{q0}\end{array}\right]}}\mathsf{\Delta }{v}_{dc}=\left[\begin{array}{l}\mathsf{\Delta }{i}_{sd}^s\\ \mathsf{\Delta }{i}_{sq}^s\end{array}\right].$$

(48)

The DC-side impedance of the converter can be obtained by inserting (47) and (48) into (21):

$$Z_{dcA}=\frac{1}{1.5(\left[\begin{array}{cc}{m}_{d0}& m_{q0}\end{array}\right]+\left[\begin{array}{cc}{i}_{sd0}& i_{sq0}\end{array}\right]G_Z^P)Y_{AC}^P}.$$

(49)

Consider the DC-side capacitor,

$$Z_{dcB}=\frac{Z_{dcA}}{1+s{C}_{dc}{Z}_{dcA}}$$

(50)

Adding the DC cable impedance to the DC-side impedance of the power-controlled converter yields

$$Z_{dc2}(s)=(Z_{dcB}(s)||\frac{2}{s{C}_d}+s{L}_d+R_d)\left|\right|\frac{2}{s{C}_d}.$$

(51)

3.3. Verifying Impedance Modeling Through Perturbation Signal Testing

Perturbation signal testing is used to verify the accuracy of the proposed small-signal model. An AC current source should be placed parallel to the DC side of the system as an input signal, as Figure 6a shows. It is necessary to inject AC current at different frequencies to measure the DC side impedance at different frequencies. At each injection frequency, a simulation experiment is conducted. The DC voltage and DC current data of each experiment are analyzed by fast Fourier transformation. The components under the disturbance frequency are taken out, and the ratio of DC voltage and DC current is calculated as the calculated impedance [13]. Figure 6b,c shows the DC-side impedance verification of the DC system rectifier and inverter sides, respectively. The solid line in Figure 6b represents the analytical impedance of the rectifier converter as in (42), and the points represent the simulation results. Figure 6b represents the analytical impedance of the inverter station and the DC cable as (51), and the points represent the simulation results.

4. Stability Analysis of VSC–HVDC with Improved Virtual Impedance Control Strategy

According to the results of small signal modeling, the DC side of the voltage-controlled converter is modeled by a DC voltage source (V_s), in series with an output impedance (Z_s), which equals to Z_dc1. The DC side of the power-controlled converter and DC cable is modeled by a DC current source shunted with an input impedance (Z_l), which equals to Z_dc2. Figure 7 shows the equivalent impedance model of the system.

According to Kirchhoff’s law, the output voltage of the DC side V_dc (s) can be expressed by Formula (52). The stability of the DC system depends on the ratio of Z_s to Z_l, which is the open-loop transfer function of system T_m. DC voltage is predicted to be stable when T_m satisfies the Nyquist stability criterion [12,13,14]:

$$V_{dc}(s)=(v_s(s)+i_l(s)Z_s(s))(\frac{1}{1+T_m})$$

(52)

$$T_m=\frac{Z_s(s)}{Z_l(s)}.$$

(53)

4.1. Impact of the Power Flow Direction

Figure 8a shows the Nichols plots of an open-loop transfer function T_m when the transmission power is ±500 MW and the length of the DC cable is 50 km. The traditional control strategy [13] shown in Figure 3 is adopted to a DC-voltage-controlled converter, and controller parameters are set as k_pvdc = 15, k_ivdc = 100.

As shown in Figure 8a, the red line does not encircle (−180°, 0), and the VSC–HVDC system is predicted to be stable. The blue encircles (−180°, 0), and the VSC–HVDC system is predicted to be unstable.

Figure 8b shows the impedance frequency responses of Z_dc1 and Z_dc2 when the active power is set as ±500 MW. Compared with the yellow line and the blue line, in the mid-frequency band, the blue line shows negative damping while the yellow line does not. Z_dc1 and Z_dc2 intersect at the mid-frequency band due to the influence of DC cable impedance. The phase difference at the red line and blue line in the mid-frequency band is approximately 180°, so the DC voltage is predicted to oscillate. The stability analysis results are consistent with the simulation results in Figure 4.

4.2. Impact of Virtual Impedance by Frequency Responses

Figure 9 shows the impedance frequency responses of Z_dc1 and Z_dc2 when the active power is set as −500 MW and the length of DC cable is 50 km. The proposed strategy in this paper is adopted for a DC-voltage-controlled converter, and the controller parameters are set as k_pvdc = 15, k_ivdc = 100, and k_i = 10. Figure 9a shows the impedance frequency responses of Z_dc1 under a different R_eqs. The pink line represents Z_dc2 and the blue, red, and yellow lines represents Z_dc1 when R_eq = 0.5, 2 and 5, respectively. The blue line shows that when the phase of Z_dc1 impedance in the mid-frequency band is below −90°, the system exhibits negative damping. The phase difference at the intersection of the pink and blue lines in the mid-frequency band is approximately 180°, and the DC voltage is predicted to oscillate. The red and yellow lines show that when the phase of Z_dc1 impedance in the mid-frequency band is above -90°, and the phase difference is less than 160 degrees, the DC voltage is predicted to stable. However, with the increase of R_eq, the phase difference at the intersection of the pink and blue lines in low-frequency bands increases, and the system tends to lose stability.

Figure 9b shows impedance frequency responses of Z_dc1 under a different L_eqs. The pink line represents Z_dc2 and the blue, red, and yellow lines represent Z_dc1 when L_eq = 0.002, 0.02, and 0.05, respectively. Blue line shows that phase of Z_dc1 impedance in mid-frequency band is below −90°, the system exhibits negative damping. The phase difference at the intersection of the pink and blue lines in the mid-frequency band is approximately 180°, and the DC voltage is predicted to oscillate. Red and yellow lines show that when the phase of Z_dc1 impedance in the mid-frequency band is above −90°, and the phase difference is less than 160 degrees, the DC voltage is predicted to be stable. However, with the increase of L_eq, the phase difference at the intersection of the pink and blue lines in the low-frequency band increases, and the system tends to lose stability.

The conclusion is that if the virtual impedance is too small, it will not be enough to suppress the oscillation. If the virtual impedance is too large, a new oscillation may occur in the low frequency band.

4.3. Impact of Virtual Impedance Parameters by Nichols Plots

Figure 10 shows the Nichols plots of T_m with different virtual impedance parameters. The DC cable length is 10 km and the transmission power is −500 MW. The proposed strategy in this paper is adopted to the DC-voltage-controlled converter, and the controller parameters are set as k_pvdc = 15, k_ivdc = 100, and k_i = 10. The blue, red, and yellow lines in Figure 10a show the Nichols plots of T_m when the virtual impedance parameters R_eq are 0.5 Ω, 2 Ω, and 5 Ω, respectively. Figure 10a shows that T_m encircles (−180°, 0), and the system is predicted to be unstable when R_eq = 0.5 Ω. The system is predicted to be stable when R_eq = 2 and 5 Ω. Increasing the R_eq value in a certain range helps improve the stability of the system. The phase margin of the system is insufficient to suppress DC-side oscillation when R_eq = 0.5 Ω.

The blue, red, and yellow lines in Figure 10b show the Nichols plots of T_m when virtual impedance parameters L_eq are 0.002 Ω, 0.02 Ω, and 0.05 Ω, respectively. Figure 10b shows that T_m encircles (−180°, 0), and the system is predicted to be unstable when L_eq = 0.002 Ω. The system is predicted to be stable when L_eq = 0.02 and 0.05 Ω. Increasing the L_eq value in a certain range helps improve the stability of the system. The phase margin of the system is insufficient to suppress DC-side oscillation when L_eq = 0.002 Ω.

4.4. Impact of DC Cable Length

Figure 11 shows the Nichols plots of the open-loop transfer function T_m under different lengths of DC cable when the transmission power is −500 MW. The control parameters are k_pvdc = 15, k_ivdc = 100, k_i = 10, R_eq = 0.5 Ω, and L_eq = 0.002 Ω. The blue, red and yellow lines in Figure 11 represent the Nichols plots of T_m at DC cable lengths of 50, 100, and 150 km, respectively. As shown in Figure 11, the Nichols plot gradually approaches (−180°, 0), with a decrease in DC cable length. The Nichols plot encircles (−180°, 0), and the system is predicted to be unstable when the DC cable length is reduced to 50 km.

4.5. Impact of DC Side Capacity

Figure 12 shows the Nichols plots of the open-loop transfer function T_m under a different capacitance of the DC side capacity when the transmission power is −500 MW. The control parameters are k_pvdc = 15, k_ivdc = 100, k_i = 10, R_eq = 0.5 Ω, and L_eq = 0.002 Ω. The blue, red, and yellow lines in Figure 12 represent the Nichols plots of T_m at the DC side capacity of 300, 450, and 600 µf, respectively. As shown in Figure 12, the Nichols plot gradually approaches (−180°, 0), with a decrease in the DC side capacity. The Nichols plot encircles (−180°, 0), and the system is predicted to be unstable when the DC side capacity is reduced to 300 µf.

From the above stability analysis, it can be concluded that there are three main factors affecting the stability of the system—power flow [24], main circuit parameters, and controller parameters. Among the main circuit parameters, the most important factors are the length of the circuit and the capacitance of the DC side. According to the stability, analysis results in 4.4 and 4.5. The stability margin of the system can be improved by increasing the DC capacitance and DC cable length. When the main circuit parameters are determined and the power flow is determined, the stability of the system can also be improved by optimizing the controller settings.

4.6. Impact of Grid Impedance

Figure 13 shows the Nichols plots of the open-loop transfer function T_m under different grid impedance when the transmission power is −500 MW. The control parameters are k_pvdc = 15, k_ivdc = 100, k_i = 10, and L_eq = 0.02 Ω. The blue and red lines in Figure 13 represent the Nichols plots of T_m when L_n = 1 and 5 mH, respectively. The blue line does not encircle (−180°, 0), while the red line encircles (−180°, 0), which means and DC-side oscillations are more likely to occur in weaker power grids. The yellow line in Figure 13 represents the Nichols plot of T_m when L_n = 5 mH and R_eq = 2. The yellow line does not encircle (−180°, 0), which means the system is predicted to be stable after choosing appropriate virtual impedance parameters.

5. Simulation Verification

5.1. Impact of DC Cable Length

Figure 14 shows the simulation results of the VSC–HVDC system with virtual impedance control strategy under different DC cable lengths. The voltage control parameters are k_pvdc = 15, k_ivdc = 100, k_i = 10, R_eq = 0.5 Ω, and L_eq = 0.002 Ω. At 2 s, the steady-state power command value is set from 500 MW to −500 MW. As shown in Figure 14, the blue line indicates the simulation results when the DC cable length is 50 km, and the red line indicates 100 km. The DC voltage in the blue line drops by approximately 5% and begins to oscillate, and the system loses stability. The DC voltage in the red line drops by approximately 5%, smoothly restoring the instruction value, and the system remains stable. The simulation results are consistent with the theoretical analysis in Section 4.4.

5.2. Impact of DC Side Capacity

Figure 15 shows the simulation results of the VSC–HVDC system with a virtual impedance control strategy under a different DC side capacity. The voltage control parameters are k_pvdc = 15, k_ivdc = 100, k_i = 10, R_eq = 0.5 Ω, and L_eq = 0.002 Ω. At 2 s, the steady-state power command value is set from 500 MW to −500 MW. As shown in Figure 15, the blue line indicates the simulation results when the DC side capacity is 300 µf, and the red line indicates 450 µf. The DC voltage in the blue line drops by approximately 5% and begins to oscillate, and the system loses stability. The DC voltage in the red line drops by approximately 5%, smoothly restoring the instruction value, and the system remains stable. The simulation results are consistent with the theoretical analysis in Section 4.5.

5.3. Dynamic Performance Comparison

According to [13], reducing the value of k_pvdc can improve the output impedance of the DC-voltage-controlled converter, thereby reinforcing the stability of the system. However, this condition influences the dynamic performance of the control. This paper compares the dynamic performance of the two control strategies. Similarly, the DC cable length is 50 km, and the active power instruction changes from 500 MW to −500 MW at 2 s. As shown in Figure 16a, the blue line represents the DC voltage under the traditional control strategy [13]. When k_pvdc = 5 and k_ivdc = 100, the red line represents the DC voltage under the proposed control strategy when k_pvdc = 15, k_ivdc = 100, k_i = 10 and R_eq = 2 Ω, and the yellow line represents the DC voltage under the proposed control strategy when k_pvdc = 15, k_ivdc = 10, k_i = 10, and L_eq = 0.02 Ω. The DC voltage in the blue line drops by approximately 9% when the instruction value is changed and gradually increases to the instruction value. The DC voltage in the red line drops by only 2% when the instruction value is changed and increases the instruction value by more than 2%. The DC voltage in the yellow line drops by only 4% when the instruction value is changed and gradually increases to the instruction value. The dynamic performance of the proposed control strategy is better than that of the traditional control method.

Figure 16b compares system DC voltages under the proposed control strategy with different virtual impedance parameters when k_pvdc = 15, k_ivdc = 100 and k_i = 10. The blue line represents R_eq = 0.5, L_eq = 0.02 Ω, the red line represents R_eq = 2 Ω, L_eq = 0.02 Ω, and the yellow line represents R_eq = 2 Ω, L_eq = 0.002 Ω. From the comparison of these three lines, it can be seen that the speed of DC voltage regulation mainly depends on R_eq. As can be seen from Figure 9a, increasing R_eq can reduce the amplitude response of Z_dc1 in the low-frequency band. However, increasing L_eq has little effect on the amplitude response of Z_dc1 in the low-frequency band, as in Figure 9b.

5.4. Steady State Error Elimination

On the basis of the previous analysis, although the traditional virtual impedance control strategy can enhance the transmission capacity of the system, it causes the steady-state error of DC voltage. Figure 17 shows the comparison of two virtual impedance control strategies. The length of the DC cable is 50 km. At 2 s, the steady-state power command value is set from 500 MW to −500 MW.

The DC voltage in the blue line represents the traditional virtual impedance, shown as the yellow frame in Figure 5, and the controller parameters are k_pvdc = 15, k_ivdc = 100, and R_eq = 2 Ω. The DC voltage in the red line represents the proposed control strategy, with k_pvdc = 15, k_ivdc = 100, R_eq = 2 Ω, and k_i = 10. Under the two control strategies, the DC voltage fluctuates in a short time and a small range only, and the active power can steadily step down. The DC voltage shown by the red line is close to the instruction value of 250 kV, and the steady-state error of the blue line is approximately 5 kV in both power flow directions, which are consistent with the theoretical analysis. The simulation results show that the improved virtual impedance control method can improve the stability of the DC system and eliminate the steady-state error of the DC voltage caused by the virtual impedance.

5.5. Impact of Gird Impedance

Figure 18 shows the simulation results of the VSC–HVDC system with a virtual impedance control strategy under a different grid impedance. The voltage control parameters are k_pvdc = 15, k_ivdc = 100, k_i = 10, and the transmission power is set as −500 MW. At 2 s, the grid impedance is switched from 1 mH to 5 mH. The blue line in Figure 18 indicates the simulation results when the virtual impedance parameter is L_eq = 0.02 Ω. The DC voltage in the blue line begins to oscillate, and the system loses stability. The red line in Figure 18 indicates the simulation results when virtual impedance parameters are L_eq = 0.02 Ω and R_eq = 2 Ω. The DC voltage in the red line stays stable, and the system remains stable. The simulation results are consistent with the theoretical analysis in Section 4.6.

6. Conclusions

This paper investigates the stability of VSC–HVDC operation in a bidirectional power flow mode. DC cable length affects the reverse power transmission power of the system. An improved virtual impedance control strategy is presented to increase the reverse power transmission power of the system. A system stability analysis based on the impedance model is applied to the proposed control strategy. System stability is affected by the power flow, controller parameters, DC cable length, and DC side capacity.

(1)

DC-side oscillation occurs when the transmission power of the system is large. The maximum transmission power of a DC voltage-controlled converter to a power-controlled converter is less than that in the opposite transmission direction.

(2)

The shorter the DC cable is, the more easily the oscillation of DC voltage will occur.

(3)

The smaller the DC side capacity is, the more easily the oscillation of DC voltage will occur.

(4)

The weaker the AC grid strength is, the more easily the DC side oscillation will occur.

(5)

Appropriate virtual impedance parameters can improve system stability. The phase margin of the system is insufficient to suppress DC-side oscillation when the virtual impedance parameter is small. If the virtual impedance parameters, R_eq or L_eq, are too large, then the system will enter a new unstable state.

The simulation results show that the proposed improved control strategy can eliminate the steady-state error of DC voltage caused by virtual impedance and maintain the advantage of a virtual impedance strategy to improve system stability. The proposed control method has better dynamic performance compared to the traditional control method.