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Review
Peer-Review Record

Rediscovering Majority Logic in the Post-CMOS Era: A Perspective from In-Memory Computing

J. Low Power Electron. Appl. 2020, 10(3), 28; https://0-doi-org.brum.beds.ac.uk/10.3390/jlpea10030028
Reviewer 1: Anonymous
Reviewer 2: Anonymous
J. Low Power Electron. Appl. 2020, 10(3), 28; https://0-doi-org.brum.beds.ac.uk/10.3390/jlpea10030028
Received: 5 August 2020 / Revised: 25 August 2020 / Accepted: 2 September 2020 / Published: 4 September 2020
(This article belongs to the Special Issue Low Power Memory/Memristor Devices and Systems)

Round 1

Reviewer 1 Report

In this review, the author discusses recent results from the memristor logic community and makes a case for majority logic based implementation of logic circuits using memristors. The author touches upon important issues such as latency and power consumption and compares how different hardware configurations such as 1T1R 1S1R compare with each other. Overall, the review is very well written and is suitable for publication. However, there is still some room for improvement.

1) The author has discussed 1S1R implementations but there was no discussion on selector devices that are made using memristors. Perhaps, adding some information regarding memristive selectors might be relevant.

2) There are some classic 1S1R works which have not been referenced.

3) Similarly, there are some highly cited 1T1R works which can be included in the reference list

Author Response

The author thanks the reviewer for the constructive comments to improve the manuscript. The 3 comments raised by the reviewer are addressed in the following manner.

  1. In the revised manuscript, a new figure (Fig.1-(a) ) is included to illustrate a selector and the 1S-1R configuration. Since the focus of the paper is not selector, information about memristive selectors is added by citing relevant references. See references 27,28,29 and 30 in the revised manuscript.   
  2. In the revised manuscript, the author has added 13 new references to include many relevant 1S-1R works. The author is not aware of any other adder implementation in 1S-1R array.
  3. In the revised manuscript, the author has added 13 new references to include many relevant 1T-1R works. The author is not aware of any other adder implementation in 1T-1R array.

Reviewer 2 Report

The review (jlpea-907216), Rediscovering Majority Logic in post-CMOS era: A perspective from In-memory Computing, summarize quite nice work comprehensively, specifically addressing on the Majority Logic with RRAM applications. Some minor points would like author to address before final consideration, shown as following:

  1. Reference is needed:
    1. Resistive RAMs are two terminal devices (usually a Metal-Insulator-Metal structure) capable of storing data as resistance (Please find a proper reference for this point, some information provide here for author: Simmons, J. G. & Verderber, R. R. New conduction and reversible memory phenomena in thin insulating films. Proc. R. Soc. London, Ser. A 301, 77–102 (1967)).
    2. In-memory computing (also called ‘processing-in-memory’) refers to any effort to process data at the residence of data (i.e. in the memory array) without moving it out to a separate processing unit. ‘Processing/computing’ could mean a wide variety of operations from arithmetic operations to cognitive tasks like machine learning and pattern recognition (Please find a proper reference for this point. Some information provide here for author: DOI: 10.1002/aisy.201900189).
    3. Although RRAM (memristor) was initially experimented as a non-volatile memory technology, it was later discovered that certain Boolean logic operations (IMPLY logic and NOR[19] were the first logic gates that were explored) can be implemented in the memory array (Please find a proper reference for this point. Some information provide here for author: DOI: 10.1063/1.4934835; J. Borghetti, G. S. Snider, P. J. Kuekes, J. J. Yang, D. R. Stewart, and R. S. Williams, Nature 464, 873 (2010)).
    4. Memristors are a class of emerging Non-Volatile Memories (NVMs) which store data as resistance (Please find a proper reference for this point. Some information provide here for author: D. B. Strukov, G. S. Snider, D. R. Stewart, and R. S. Williams, Nature 453, 80 (2008)).
    5. Under voltage/current stress, the resistance can be switched between a Low Resistance State (LRS) and a High Resistance State (HRS) (Hickmott, T. W. Low‐frequency negative resistance in thin anodic oxide films. J. Appl. Phys. 33, 2669–2682 (1962)).
    6. The word ‘memristor’ is used because such a device is basically a ‘resistor’ with a ‘memory’ (Chua, L. O. Memristor - the missing circuit element. IEEE Trans. Circuit Theory 18, 507–519 (1971)).
    7. Resistive Random Access Memory (RRAM) where the change in resistance is due to the formation and rupture of a conductive filament; Phase Change Memory (PCM) where the change in resistance is due to the amorphous or crystalline state of the chalcogenide phase-change material; Spin Transfer Torque-Magnetic RAM (STT-MRAM) where the change in resistance is due to the magnetic polarization (Please find a proper reference for this point; RRAM-DOI: 10.1186/s11671-015-0740-7, PCM, and MRAM).
    8. To construct a memory array using such devices, two configurations are common: 1Transistor-1 Resistor (1T–1R) and 1Selector-1 Resistor (1S–1R) (Please find a proper reference for this point; 1T1R, DOI: 10.23919/VLSIT.2019.8776570; 1S1R: 10.1039/C8NR04766A).
    9. The 1S–1R configuration uses a two-terminal device called a ‘selector’ which has a diode-like characteristic (DOI-10.1149/2.0041709jss; DOI-10.1039/C7NR02305G; DOI-10.1186/s11671-018-2660-9; DOI-10.1109/TED.2018.2862917).
  2. Edit needed: In literature, there are two viable ways in which a majority gate is implemented in Resistive RAM array. Both are non-stateful logic families. Following the naming convention introduced in [28] (‘input state variable-output state variable’ logic), a non-stateful logic family can be V–R logic (input state variable is voltage and the output is resistance) or R–V logic (input state variable is resistance and output is voltage), as illustrated in Fig.1-(b). => Here should be Fig. 1-(a). 
  3. In Table 3, author may want to add one more IMPLY, structure 1D1R, with 43 steps latency in following reference: DOI: 10.1109/TED.2017.2699679. 
  4. Can authors add one more briefly paragraphs discussing about the power of the majority logics before conclusion. What would be the main issue or improvement needed in the era of in-memory computing as compared to standard CMOS?

Due to the above comments, this referee would like to put the manuscript status as "Minor Revision" in current phase. 

Author Response

The author thanks the reviewer for the constructive comments to improve the manuscript. The reviewer's comments have been addressed in the following manner:

1.Reference comment. All the relevant references suggested by the reviewer have been added to the manuscript. See references 19, 20, 21, 23, 24, 26, 27, 28, 29  and 30  of the revised manuscript. 

2. Edit needed. The wrong reference to the figure is corrected.

3. In Table 3, the IMPLY logic suggested by you is added (See Reference 50 and Table 3)

4.The main drawback of in-memory computing compared to CMOS is “latency”. The power of majority logic lies in reducing this latency to compute in memory. The author has added a paragraph before conclusion, elaborating the power of majority logic.

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