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Article

Minimization of the Line Resistance Impact on Memdiode-Based Simulations of Multilayer Perceptron Arrays Applied to Pattern Recognition

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Unidad de Investigación y Desarrollo de las Ingenierías (UIDI), Facultad Regional Buenos Aires, Universidad Tecnológica Nacional (UTN-FRBA), Buenos Aires C1179AAQ, Argentina
2
Consejo Nacional de Investigaciones Científicas y Técnicas (CONICET), Buenos Aires C1425FQB, Argentina
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Departament d’Enginyeria Electrònica, Universitat Autònoma de Barcelona (UAB), 08193 Cerdanyola del Vallès, Spain
4
Departamento de Ingeniería Electrónica, Facultad Regional Buenos Aires, Universidad Tecnológica Nacional (UTN-FRBA), Buenos Aires C1179AAQ, Argentina
*
Authors to whom correspondence should be addressed.
Academic Editor: Alex Serb
J. Low Power Electron. Appl. 2021, 11(1), 9; https://0-doi-org.brum.beds.ac.uk/10.3390/jlpea11010009
Received: 4 January 2021 / Revised: 1 February 2021 / Accepted: 2 February 2021 / Published: 5 February 2021
(This article belongs to the Special Issue Low Power Memory/Memristor Devices and Systems)
In this paper, we extend the application of the Quasi-Static Memdiode model to the realistic SPICE simulation of memristor-based single (SLPs) and multilayer perceptrons (MLPs) intended for large dataset pattern recognition. By considering ex-situ training and the classification of the hand-written characters of the MNIST database, we evaluate the degradation of the inference accuracy due to the interconnection resistances for MLPs involving up to three hidden neural layers. Two approaches to reduce the impact of the line resistance are considered and implemented in our simulations, they are the inclusion of an iterative calibration algorithm and the partitioning of the synaptic layers into smaller blocks. The obtained results indicate that MLPs are more sensitive to the line resistance effect than SLPs and that partitioning is the most effective way to minimize the impact of high line resistance values. View Full-Text
Keywords: RRAM; resistive-switching; cross-point; memory; memristor; neuromorphic; pattern recognition; multilayer perceptron RRAM; resistive-switching; cross-point; memory; memristor; neuromorphic; pattern recognition; multilayer perceptron
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MDPI and ACS Style

Aguirre, F.L.; Gomez, N.M.; Pazos, S.M.; Palumbo, F.; Suñé, J.; Miranda, E. Minimization of the Line Resistance Impact on Memdiode-Based Simulations of Multilayer Perceptron Arrays Applied to Pattern Recognition. J. Low Power Electron. Appl. 2021, 11, 9. https://0-doi-org.brum.beds.ac.uk/10.3390/jlpea11010009

AMA Style

Aguirre FL, Gomez NM, Pazos SM, Palumbo F, Suñé J, Miranda E. Minimization of the Line Resistance Impact on Memdiode-Based Simulations of Multilayer Perceptron Arrays Applied to Pattern Recognition. Journal of Low Power Electronics and Applications. 2021; 11(1):9. https://0-doi-org.brum.beds.ac.uk/10.3390/jlpea11010009

Chicago/Turabian Style

Aguirre, Fernando L., Nicolás M. Gomez, Sebastián M. Pazos, Félix Palumbo, Jordi Suñé, and Enrique Miranda. 2021. "Minimization of the Line Resistance Impact on Memdiode-Based Simulations of Multilayer Perceptron Arrays Applied to Pattern Recognition" Journal of Low Power Electronics and Applications 11, no. 1: 9. https://0-doi-org.brum.beds.ac.uk/10.3390/jlpea11010009

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