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Article

Implementation of Power-Efficient Class AB Miller Amplifiers Using Resistive Local Common-Mode Feedback

1
Electrical Engineering & Renewable Engineering, Oregon Institute of Technology, 3201 Campus Drive, Klamath Falls, OR 97601, USA
2
Klipsch School of Electrical & Computer Engineering, New Mexico State University, Las Cruces, NM 88003, USA
3
Instituto Tecnológico Superior de Poza Rica, Tecnológico Nacional de México, Luis Donaldo Colosio Murrieta S/N, Arroyo del Maíz, Poza Rica 93230, Mexico
4
Department of Electronics, INAOE, Puebla 72840, Mexico
5
Facultad de Instrumentación Electrónica, Universidad Veracruzana, Cto. Gonzalo Aguirre Beltrán S/N, Xalapa 91000, Mexico
6
Consejo Veracruzano de Investigación Científica y Desarrollo Tecnológico (COVEICYDET), Av Rafael Murillo Vidal No. 1735, Cuauhtémoc, Xalapa 91069, Mexico
*
Author to whom correspondence should be addressed.
J. Low Power Electron. Appl. 2021, 11(3), 31; https://0-doi-org.brum.beds.ac.uk/10.3390/jlpea11030031
Submission received: 27 June 2021 / Revised: 19 July 2021 / Accepted: 22 July 2021 / Published: 26 July 2021

Abstract

:
An approach to implement single-ended power-efficient static class-AB Miller op-amps with symmetrical and significantly enhanced slew-rate and accurately controlled output quiescent current is introduced. The proposed op-amp can drive a wide range of resistive and capacitive loads. The output positive and negative currents can be much higher than the total op-amp quiescent current. The enhanced performance is achieved by utilizing a simple low-power auxiliary amplifier with resistive local common-mode feedback that increases the quiescent power dissipation by less than 10%. The proposed class AB op-amp is characterized by significantly enhanced large-signal dynamic, static current efficiency, and small-signal figures of merits. The dynamic current efficiency is 15.6 higher, the static current efficiency is 10.6 times higher, and the small-signal figure of merit is 2.3 times higher than the conventional class-A op-amp. A global figure of merit that determines an op-amp’s ultimate speed is 6.33 times higher than the conventional class A op-amp.

1. Introduction

The Miller op-amp is the essential building block of analog integrated circuits [1,2]. In the conventional class-A Miller op-amp with an NMOS input stage [2,3] shown in Figure 1a, the NMOS output transistor limits the peak negative output current to a value IoutQ corresponding to the output branch’s quiescent current. This imposes a severe limitation in the op-amp’s negative slew rate (SR). This can be expressed as SR = (IoutQ − IRL)/(CC + CL), where CC and CL are compensation and load capacitors and IRL is the current of the resistive load. Many approaches have been proposed to implement Miller op-amps with static class-AB [4,5] output stages. This type of amplifier can drive a wide range of capacitive and resistive loads down to very low frequencies or DC. They are required to have approximately symmetrical slew rates and to be able to generate symmetrical peak load positive and negative output currents IOutpk+ and IOutpk much larger than the total op-amp quiescent current ItotQ. A common figure of merit to characterize the op-amp current efficiency CE = IOutpk/ItotQ is defined as the ratio of the minimum of the positive and negative peak output currents IOutpk = MIN{IOutpk+, IOutpk} to ItotQ. The conventional class-A op-amp (Conv-A) is characterized typically by CE < 0.5. Many approaches to implementing class-AB op-amps are based on the floating battery [6] scheme shown in Figure 1b. The floating battery that exists between the gates of the PMOS and NMOS output transistors causes the voltage VY at the gate of the output NMOS transistor to follow the variations at node VX, which is the high impedance output node of the differential input stage. The voltage VX drives the output PMOS transistor MOP. The small signal model of the class-AB op-amps based on the floating battery [6] scheme is shown in Figure 1c. In this, the ideal floating battery has been replaced by an AC short circuit. The output resistance ROut is given by ROut = RoOP||roON||RL. As the conventional Miller compensation is used in the op-amp, the transfer function of the circuit of Figure 1c can be written as Equation (1).
H ( s ) = A OLDC ( 1 + s ω z ) ( 1 + s ω pOut ) ( 1 + s ω pDOMX )
Here, ωz, ωpOut, and ωpDOMX are given by the following expressions Equations (2)–(4).
ω z = 1 [ R C ( g mOP + g mON ) 1 ] C C
ω pOut = ( g mOP + g mON + R L ) C L
ω pDOMX = 1 / R X C X
where CX is given by CX = (1 + |AOut|) CC, RX = gmro2/2, and |AOut| is the gain of the output stage.
The operation of Class-AB op-amps based on the floating battery principle is discussed below:
(a)
Upon application of a positive step at Vin, the output of the op-amp provides a positive output current to the load. When the output slews in the positive direction, the voltage at node Vx is subject to a large negative variation, which is followed by the voltage at node VY until it reaches the bottom rail. This increases the current in MOP and decreases the current in MON, bringing it to zero for large negative variations in VY that lead to VGSON < VTN, where VTN is the threshold voltage of MON. Since VX can have large negative variations, the peak positive output current IOutpk+ provided by MOP can be much larger than its quiescent current IOutQ, and a large positive slew rate can be achieved. The situation is quite different for negative steps in Vin. In this case, VX has a relatively limited excursion in the positive direction, which is transferred (in practice with some attenuation) to VY. This causes the current in MOP to decrease (and eventually go to zero) and MON to increase. However, given that the variation in the positive direction of Vx and VY is much smaller than the variation in the negative direction, the op-amp’s peak negative output current IOutpk generated by MON is in general much smaller than IOutpk+. This leads to a negative slew rate, which can be much smaller than the positive slew rate. In practice, the smaller of the two slew rates determines the nominal op-amp’s slew rate SR ≡ MIN{SR+, SR}.
(b)
The practical implementation of the floating battery scheme requires a control circuit to achieve the desired nominal output quiescent current IOutQ, which adjusts the value of the floating battery VBAT so that its value is well defined and remains constant, independent of temperature, process parameters, and supply voltage variations. It can be shown that, in saturation, IOutQ is approximately given by, I outQ = [ ( V supply V BAT | V TP | V TN ) / ( 1 / β N + 1 / β P ) ] 2 where βN, βP, VTN, and VTP are the NMOS and PMOS output transistors’ gain factors and threshold voltages, respectively. A control circuit to adjust the value of VBAT is required since a fixed VBAT value would lead to large variations in IOutQ with changes in Vsupply, VTN, VTP, βN, or βP. An example of the class-AB output stage using a foating battery and a control circuit is shown in Figure 2. In this example, the floating battery is implemented using a voltage follower. The circuit implementation of both VBAT and the control circuit [7,8] can be relatively complex (as shown in Figure 2b and in the circuit of [8]) and increases the total op-amp’s quiescent current. This can significantly lower the current efficiency of the class-AB op-amp. In some cases, it can also increase the supply requirements beyond the nominal supply voltage of the implementation technology, which has been reduced to sub-volt values (Vsupply < 1 V) in modern CMOS technologies.
This paper introduces a simple scheme that overcomes the shortcomings discussed above, requiring minimal additional power dissipation and not increasing the supply requirements. This scheme is discussed in the next section. Traditionally, the performance of op-amps is compared using three well-known figures of merit: (a) the small-signal figure of merit FOMSS = fu·CL/PQ, where fu is the unity-gain frequency and PQ is the quiescent power of the op-amp; (b) the large-signal static current efficiency figure of merit FOMCEStat = IoutpkRL/PQ; and (c) the large-signal dynamic current efficiency figure of merit FOMCEDyn = SR·CL/PQ, which is related to the maximum dynamic output current in load capacitance CL. FOMCEStat is determined by the maximum DC output current in the load resistor RL (denoted IoutpkRL) relative to the total quiescent power PQ of the op-amp. In addition, as both FOMSS and FOMCEDyn determine the ultimate speed of an op-amp, a new global figure of merit FOMGlobal given by FOM Global = FOM SS FOM CEDyn is also used here.

2. Circuit Description

The scheme of the proposed op-amp is shown in Figure 3a. A telescopic input stage is used in the first stage to achieve high gain even in the presence of a low-valued load resistor RL (high loading conditions) that can degrade the second stage gain significantly. The proposed op-amp uses an auxiliary non-inverting amplifier with gain Aaux to generate a voltage variation VY, which is an amplified version of the variations in VX, that is, VY = AauxVX. This auxiliary amplifier consumes less than 10% of the op-amp’s total bias current and does not increase supply requirements. The transistor-level implementation of the auxiliary amplifier is shown in Figure 3b. It uses a differential stage with resistive common-mode feedback (RCMFB) that has approximately a gain Aaux = (gm4RCMF)/2, as shown in the analysis below. The auxiliary amplifier increases the op-amp’s output negative current; the open-loop DC gain shifts the output poles to the higher frequency, allowing for a higher unity gain frequency. The quiescent voltage of VY has a value VYQ = VGSQM5P independent of RCMF (and of AAux). This allows to accurately control the quiescent current IOutQ in the op-amp’s output branch independent of the gain Aaux, supply voltage, technology parameters variations, and temperature changes. Given that the variations generated at VY are amplified with respect to those at Vx, MON can provide large negative output currents even though the amplitude of positive variations in VX is smaller than that for negative variations. This overcomes one of the limitations of the conventional battery approach shown in Figure 1b.
In order to prevent degradation of the phase margin of the op-amp, the value of RCMF (and Aaux) is chosen in such a way that the pole at node Y is higher than the unity gain frequency fu of the op-amp by at least a factor of 3. Thus, the selection of the optimal value of RCMF is the crucial factor for the design of the proposed auxiliary amplifier. Larger values of RCMF lead to enhanced negative output currents and gains, resulting in lower values for the pole at node Y and lower phase margin.
In the presence of positive signals in VX larger than VSDsat4, all of the tail current of MTAILAUX flows through M4P and RCMF. This causes a large positive voltage change at node VY that generates large negative op-amp output currents. In order to achieve similar peak positive and negative output currents with the selected value of RCMF, the output transistors MON and MOP are scaled by factor 5/1 and factor 8/0.7 with respect to the unit PMOS and NMOS transistors of size 10/0.27 used in the input stage. In addition, conventional Miller compensation is used to achieve stability.

2.1. Operation

The working principle of the proposed op-amp can be explained by considering its voltage follower operation. In the presence of the positive input signal Vin, the voltage at node VX decreases and the voltage at node VY also decreases by a factor Aaux. As a result, MOP provides a large positive current, and the drain current of MON decreases and eventually reaches zero. On the other hand, for negative input signals, the voltage at node VY corresponds to the amplified version of the positive signals of node VX, which is VY = AauxVX. As a result, MON can also provide large negative output currents.

2.2. Frequency Response

Conventional Miller compensation is used in the proposed op-amp. The proposed op-amp has one dominant pole ωpDOMX at node VX and two high-frequency poles ωpY and ωpOut. The zero ωz approximately nullifies the effect of ωpOut.
Thus, the transfer function of the proposed op-amp is given by Equation (5).
H ( s ) A OLDC ( 1 + s / ω z ) ( 1 + s / ω pDOMX ) ( 1 + s / ω p Out ) ( 1 + s / ω p Y )
The gain of the first stage AI is given by Equation (6).
A I = g m 1 R X = g m 1 ( g m r o 2 / 2 )
Here, for simplicity, gm is the transconductance gain of all unit size NMOS and PMOS transistors, ro is their output resistance, and RX is resistance at node VX. The auxiliary amplifier’s gain is given by Aaux = (gm4RY)/2, where R Y = r o 4 P · g mCP 2 P r oCP 2 P | | R CMF | | r o 5 P . As RCMF << ro4P, roCP2P, ro5P, RY ≈ RCMF and Aaux ≈ (gm4RCMF)/2.
The gain of the output stage is given by Equation (7).
A Out = ( g mOP + A aux g mON ) R Out
where ROut is R Out = r oOP | | r oON | | R L .
Thus, the open-loop DC gain AOLDC of the proposed op-amp is expressed by Equation (8).
A OLDC = A I A Out = ( ( g m r o ) 2 / 2 ) ( g mouteff R Out )
where gmouteff = gmOP + AauxgmON and ROut = rOP||rON||RL.
The dominant pole is at node VX and is given by Equation (9).
f pDOMX = 1 / ( 2 π R X C X )
where CX is given by CX = (1 + |Aout|) CC.
Thus, the gain-bandwidth product (GBW) of the proposed op-amp is given by Equation (10).
GBW = A I A Out 1 2 π R X ( 1 + | A Out | ) C C = ( g m 1 A Out ) 1 2 π ( 1 + | A Out | ) C C
Besides the dominant pole, the proposed op-amp has two high-frequency poles: one at VY and another at VOut. The output high-frequency pole fpOut is given in Equation (11).
f pOut = ( g mOP + A aux g mON G L ) / ( 2 π C L )
The pole at node VY is expressed by Equation (12).
f pY = 1 / ( 2 π R Y C Y )
where CY is given by C Y = C gsON + C dBCP 2 P + C dB 5 P + C gdON ( 1 + ( A Out A VY ) ) + C gd 5 P and R Y = r o 4 p · g mCP 2 P · r oCP 2 P | | R CMF | | r o 5 P . The selection of RCMF plays an important role in determining a compromise between the gain of the auxiliary amplifier and the phase margin of the op-amp. To achieve a sufficient phase margin, fPY should be higher than the unity gain frequency of the op-amp. Thus, RCMF has to be selected in such a way that the pole of the node Y, i.e., fPY, is located at least a factor three higher than the op-amp’s unity gain frequency, and in that case, RCMF << ro5P,ro4PgmCP2ProCP2P and RY can be approximated as RY ≈ RCMF. In this case, fPY has a minor effect on the op-amp’s frequency response up to the unity gain frequncy fu, and Equation (12) can be simplified as below.
f p Y = 1 / ( 2 π R CMF C Y )
The zero is given by Equation (14).
f z = 1 / ( 2 π C C [ R C ( g m O P + A Aux g m O N ) 1 ] )
The simplified transfer function of the proposed op-amp neglecting the pole at node Y can be approximated by Equation (15).
H ( s ) A OLDC ( 1 + s / ω z ) ( 1 + s / ω p D O M X ) ( 1 + s / ω p Out )
The small-signal model of the proposed op-amp is given in Figure 4.

3. Results

The proposed and conventional class-A op-amps are designed in 130 nm CMOS technology. The unit size transistors used in both op-amps are (W/L)N = (W/L)P = 10/0.27 (µm/µm). The compensation capacitor has a value CC = 4 pF for both op-amps. The compensation resistor RC has a value 8 kΩ for the proposed op-amp and 19 kΩ for the Conv-A op-amp. For a fair comparison, the output transistors of the Conv-A op-amp MOP are scaled by the same factor 8/0.7 and MON is by the same factor 5/1 as the proposed op-amp compared to the unit size transistors used in the circuit. They are simulated using the same bias current IB = 15 µA, and dual supply voltages VDD = +0.6 V and VSS = −0.6 V. Figure 5 shows the open-loop frequency response of the proposed op-amp. The proposed op-amp has open-loop gains AOLDC = 89.7 dB with RL = 1 MΩ and 57 dB with RL = 200 Ω, and CL = 300 pF in both cases. On the other hand, the conventional class-A(Conv-A) op-amp can provide a maximum AOLDC of 75.8 dB for RL = 1 MΩ and only 43.4 dB with RL = 200 Ω. Figure 6 shows the corresponding frequency response of the Conv-A op-amp with CL = 300 pF.
The unity gain frequency fu of the proposed op-amp for RL = 1 MΩ is 16.9 MHz and for RL = 200 Ω is 16.01 MHz. The small-signal figures of merit FOMSS of the proposed op-amp are 28.8 and 27.2 for RL = 1 MΩ and 200 Ω. The Conv-A op-amp’s FOMSS for similar loading conditions are 12.4 and 10.8. Thus, the proposed op-amp can drive a low-value resistive load (high-loading condition) by maintaining a relatively high open-loop gain. It can be seen that, as expected, the introduction of the auxiliary amplifier in the proposed op-amp leads to lower gain degradation (and consequently, lower gain errors) for lower-valued load resistors.
Figure 7 shows the transient response of the proposed and Conv-A op-amp with RL = 1 MΩ and CL = 300 pF for a 500 kHz input pulse with 500 mVpp amplitude. It can be observed that the Conv-A op-amp cannot follow the input signal. From Figure 8, it can be asserted that this is because of the limitation of the peak negative output current, which corresponds to the quiescent current of the output branch in the Conv-A op-amp. From the pulse responses and load currents of the proposed and Conv-A op-amp for RL = 1 MΩ, it can be asserted that the proposed op-amp increases the negative slew rate by a factor of 20 compared with the Conv-A op-amp. The SR enhances by a large factor close to 20 from 0.36 V/µs for the Conv-A to 7.4 V/µs for the proposed op-amp. Therefore, the CE of the proposed and Conv-A op-amps are 15.6 and 0.8, respectively.
From Figure 9, it can be asserted that the proposed op-amp can drive both large capacitive and low-valued resistive loads. Figure 10 shows the output current in the 200 Ω load resistor for the Conv-A and proposed op-amps for 500 mVpp and 500 kHz input pulse. It can be seen that the proposed op-amp can provide 1.24 mA positive and negative peak output currents to a 200 Ω resistive load for a 500 mVpp and 500 kHz input pulse. In contrast, the Conv-A op-amp with the same input signal can provide only a 105 μ A negative output current, which is limited by the quiescent current of the output branch.
Figure 11 and Figure 12 show the closed-loop frequency response of the proposed and Conv-A op-amps in the voltage follower configuration (VF). The proposed op-amp has 3 dB.
The bandwidth (BW) is 29 MHz for RL = 1 MΩ and 26.4 MHz for RL = 200 Ω. In comparison, the Conv-A op-amp has 8.37 MHz and 4.6 MHz 3 dB bandwidths for similar loading conditions. It can be seen that the proposed op-amp has a higher bandwidth than the Conv-A op-amp.
A corner analysis of the proposed op-amp was performed to verify its robustness against temperature, process variations, and mismatches in the values of the design components. Table 1 shows the corner analysis of the op-amp employing typical 2% mismatches in the differential pair and the resistors used in the auxiliary amplifier. It can be asserted that, from the corner analysis, the proposed op-amp is robust against the temperature and process variations.
Figures of merit FOMCEDyn and FOMCEStat of the proposed op-amp are 12.6 and 7. FOMCEDyn and FOMCEStat of the Conv-A op-amp are 0.8 and 0.66. Thus, the proposed op-amp achieved 16 times higher FOMCEDyn and 10.6 times higher FOMCEStat than the Conv-A op-amp.
Comprehensive comparisons of the proposed op-amp’s performance with state-of-the-art op-amps and Conv-A op-amp are shown in Table 2. The proposed op-amp has the highest small-signal, dynamic, static current efficiency, and global figures of merits. It can be asserted that, from the comparison table, the proposed architecture can drive both resistive and capacitive load efficiently. The presence of the auxiliary amplifier in the prosed architecture makes this possible.

4. Conclusions

A simple class-AB Miller op-amp that can drive both resistive and capacitive loads is presented here. A compact auxiliary amplifier is used to provide the static class-AB operation and helps to achieve higher gain, bandwidth, and a well-defined output quiescent current. The proposed op-amp can provide a 13.9 dB higher open-loop gain, a factor 20 higher slew-rate, and a factor 3.3 to 5.7 higher bandwidth (in VF configuration) than the conventional op-amp at the expense of only 10% additional quiescent current compared to the Conv-A op-amp.

Author Contributions

Investigation, writing, review, and editing were completed by A.P., M.R.-P., J.R.-A., R.B.-P., H.V.-L., J.H.-C. and A.D.-S. All authors have read and agreed to the published version of the manuscript.

Funding

This work was supported in part by the Mexican Consejo Nacional de Ciencia y Tecnologia (CONACYT) under grant A1-S-43214.

Data Availability Statement

Data is contained within the article.

Acknowledgments

The authors thank MOSIS for providing the simulation model.

Conflicts of Interest

There are no conflicts of interest.

References

  1. Cruz, S.C.D.; Reyes, M.G.T.D.; Gaffud, T.C.; Abaya, T.V.F.; Gusad, M.T.A.; Rosales, M.D. Design and implementation of operational amplifiers with programmable characteristics in a 90 nm CMOS process. In Proceedings of the 2009 European Conference on Circuit Theory and Design, Antalya, Turkey, 23–27 August 2009; pp. 209–212. [Google Scholar]
  2. Razavi, B. Design of Analog CMOS Integrated Circuits; McGraw-Hill: New York, NY, USA, 2001. [Google Scholar]
  3. William, S.M.C. Analog Design Essentials; Springer: New York, NY, USA; Berlin, Germany, 2006. [Google Scholar]
  4. Monticelli, D.M. A quad CMOS single-supply op amp with rail-to-rail output swing. IEEE J. Solid State Circuits 1986, 21, 1026–1034. [Google Scholar] [CrossRef] [Green Version]
  5. De Langen, K.-J.; Huijsing, J. Compact low-voltage power-efficient operational amplifier cells for VLSI. IEEE J. Solid State Circuits 1998, 33, 1482–1496. [Google Scholar] [CrossRef] [Green Version]
  6. Gregorian, R.; Temes, G.C. Analog MOS Integrated Circuits for Signal Processing; Wiley Series on Filters: Design Manufacturing and Applications; Wiley-Interscience: New York, NY, USA, 1986. [Google Scholar]
  7. Torralba, A.; Carvajal, R.G.; Ramirez-Angulo, J.; Tombs, J.; Galán, T. Class AB output stages for low voltage CMOS opamps with accurate quiescent current control by means of dynamic biasing. In Proceedings of the ICECS 2001 8th IEEE International Conference on Electronics, Circuits and Systems (Cat. No.01EX483), Malta City, Malta, 2–5 September 2001; Volume 2, pp. 967–970. [Google Scholar] [CrossRef]
  8. Padilla-Cantoya, I.; Molinar-Solis, J.E.; Medina-Vazquez, A.S.; Gurrola-Navarro, M.A.; Rizo-Dominguez, L.; Gutierrez-Frias, E.F. Class AB Op-Amp with Accurate Static Current Control for Low and High Supply Voltages. IEEE Trans. Circuits Syst. II Express Briefs 2021, 1. [Google Scholar] [CrossRef]
  9. Sutula, S.; Dei, M.; Terés, L.; Serra-Graells, F. Variable-Mirror Amplifier: A New Family of Process-Independent Class-AB Single-Stage OTAs for Low-Power SC Circuits. IEEE Trans. Circuits Syst. I Regul. Pap. 2016, 63, 1101–1110. [Google Scholar] [CrossRef] [Green Version]
  10. Cabrera-Bernal, E.; Pennisi, S.; Grasso, A.D.; Torralba, A.; Carvajal, R.G. 0.7-V Three-Stage Class-AB CMOS Operational Transconductance Amplifier. IEEE Trans. Circuits Syst. I Regul. Pap. 2016, 63, 1807–1815. [Google Scholar] [CrossRef]
  11. Anisheh, S.M.; Abbasizadeh, H.; Shamsi, H.; Dadkhah, C.; Lee, K.-Y. 98-dB Gain Class-AB OTA with 100 pF Load Capacitor in 180-nm Digital CMOS Process. IEEE Access 2019, 7, 17772–17779. [Google Scholar] [CrossRef]
  12. Grasso, A.D.; Pennisi, S.; Scotti, G.; Trifiletti, A. 0.9-V Class-AB Miller OTA in 0.35μm CMOS with Threshold-Lowered Non-Tailed Differential Pair. IEEE Trans. Circuits Syst. I Regul. Pap. 2017, 64, 1740–1747. [Google Scholar] [CrossRef]
  13. Kuo, P.-Y.; Tsai, S.-D. An Enhanced Scheme of Multi-Stage Amplifier with High-Speed High-Gain Blocks and Recycling Frequency Cascode Circuitry to Improve Gain-Bandwidth and Slew Rate. IEEE Access 2019, 7, 130820–130829. [Google Scholar] [CrossRef]
  14. Renteria-Pinon, M.; Ramirez-Angulo, J.; Diaz-Sanchez, A. Simple Scheme for the Implementation of Low Voltage Fully Differential Amplifiers without Output Common-Mode Feedback Network. J. Low Power Electron. Appl. 2020, 10, 34. [Google Scholar] [CrossRef]
Figure 1. (a) Conventional class-A Miller op-amp, (b) Miller op-amp with class-AB output stage based on floating battery, and (c) small-signal model of the class-AB op-amp based on the floating battery scheme.
Figure 1. (a) Conventional class-A Miller op-amp, (b) Miller op-amp with class-AB output stage based on floating battery, and (c) small-signal model of the class-AB op-amp based on the floating battery scheme.
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Figure 2. (a) Example of the class-AB output stage based on the floating battery principle using a VF with level shift and (b) a replica bias control circuit for the generation of VCNTR so that the quiescent output current has a nominal well-defined value independent of VDD, technology parameters, and temperature.
Figure 2. (a) Example of the class-AB output stage based on the floating battery principle using a VF with level shift and (b) a replica bias control circuit for the generation of VCNTR so that the quiescent output current has a nominal well-defined value independent of VDD, technology parameters, and temperature.
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Figure 3. (a) Scheme of the proposed class-AB Miller op-amp and (b) transistor level implementation.
Figure 3. (a) Scheme of the proposed class-AB Miller op-amp and (b) transistor level implementation.
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Figure 4. Small-signal model of the proposed op-amp.
Figure 4. Small-signal model of the proposed op-amp.
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Figure 5. Frequency response of the proposed op-amp in open-loop configuration for RL = 1 MΩ and RL = 200 Ω.
Figure 5. Frequency response of the proposed op-amp in open-loop configuration for RL = 1 MΩ and RL = 200 Ω.
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Figure 6. Open-loop frequency response of the Conv-A op-amp for RL = 1 MΩ and RL = 200 Ω.
Figure 6. Open-loop frequency response of the Conv-A op-amp for RL = 1 MΩ and RL = 200 Ω.
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Figure 7. Transient response of the Conv-A and proposed op-amps for 500 kHz and 500 mVpp amplitude input pulses with RL = 1 MΩ and CL = 300 pF.
Figure 7. Transient response of the Conv-A and proposed op-amps for 500 kHz and 500 mVpp amplitude input pulses with RL = 1 MΩ and CL = 300 pF.
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Figure 8. Current in the load capacitance CL = 300 pF in the Conv-A and proposed op-amps for 500 kHz and 500 mVpp amplitude pulse inputs.
Figure 8. Current in the load capacitance CL = 300 pF in the Conv-A and proposed op-amps for 500 kHz and 500 mVpp amplitude pulse inputs.
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Figure 9. Transient response of the Conv-A and proposed op-amps for 500 kHz and 500 mVpp pulse inputs with RL = 200 Ω and CL = 300 pF.
Figure 9. Transient response of the Conv-A and proposed op-amps for 500 kHz and 500 mVpp pulse inputs with RL = 200 Ω and CL = 300 pF.
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Figure 10. Current in RL = 200 Ω in the Conv-A and Proposed op-amps 500 kHz and 500 mVpp amplitude pulse inputs.
Figure 10. Current in RL = 200 Ω in the Conv-A and Proposed op-amps 500 kHz and 500 mVpp amplitude pulse inputs.
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Figure 11. Frequency response of the proposed op-amp in a close-loop VF configuration for RL = 1 MΩ and RL = 200 Ω.
Figure 11. Frequency response of the proposed op-amp in a close-loop VF configuration for RL = 1 MΩ and RL = 200 Ω.
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Figure 12. Closed-loop frequency response of the conventional class-A op-amp for RL = 1 MΩ and RL = 200 Ω in the VF mode.
Figure 12. Closed-loop frequency response of the conventional class-A op-amp for RL = 1 MΩ and RL = 200 Ω in the VF mode.
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Table 1. Corner analysis of the op-amp at different temperatures.
Table 1. Corner analysis of the op-amp at different temperatures.
At T = 27 °CAt T = 120 °CAt T = −20 °C
CornerttfffssfssSDttfffssfssSDttfffssfssSD
ITotalQ (µA)1471481461461460.81631671631641602.21351351331341340.75
THD (dB)
at RL = 200 Ω
−66−65−66−62−602.4−55−50−50−49−522.13−65−60−61−60−621.9
fu (MHz)
at RL = 200 Ω
16.91716.716.7160.311.6211.1211.3611.5911.830.2419.1419.41918.918.40.33
PM (°)
at RL = 1 MΩ
64.1636565671.3170687269681.562626062641.26
Gain9087.789.485.7901.6574707871793.691.390.791.590.3900.57
SR (V/µs)7.477.17.77.10.2577.097.67.37.90.37.37.77.47.26.90.26
IoutpkRL = 200 Ω (mA)1.241.231.241.231.240.0041.191.21.211.151.200.021.241.231.11.251.240.06
Table 2. Summary of the results and performance comparison.
Table 2. Summary of the results and performance comparison.
Parameter (Units)ProposedConv-A[8]
2020
[9]
2016
[10]
2016
[11]
2019
[12]
2017
[13]
2019
[14]
2020
Inversion levelSISISISISBTSISBTSISBT
CMOS process (µm)0.130.130.50.180.180.180.350.180.18
Supply voltage (V)±0.6±0.61.2/2/2.51.80.71.80.91.8±0.3
Capacitive load (pF)300300162002010010510
Resistive Load (Ω)1 M/2001 M/200-----1 k-
SR (V/μs)7.40.363.9/4.3/4.374.12.8510.2513.258.4
DC gain (dB)89.7/5775.8/43.4469/70/707257.59865105.542.2
PM (°)64.1/7675/9758/58/58.5506071605354
fu (MHz)16.9/16.06.6/5.728.3/8.4/8.586.53211231.716.1
CMRR at DC (dB)71 at RL = 1 M52 at RL = 1 M69/70/64NA19-45-85.12
PSRR + at DC (dB)109 at RL = 1 M69 at RL = 1 M73/73/73NA52.1---53.25
PSRR − at DC (dB)99 at RL = 1 M57 at RL = 1 M73/73/72NA66.4---56.89
IOutpk+RL = 200 Ω (µA)12411241-----1200-
IOutpkRL = 200 Ω (µA)1241105-------
ItotQ (µA)147133162/166/168661136.31666.72747241.33
Power (μW)176159.6244/332/4201190025.4300024.385024.8
FOMCEDyn
(V.pF/µs.µW)
12.60.80.25/0.21/0.161.252.21.70.10.0783.3
FOMSS
(MHz.pF/µW)
28.8/27.212.4/10.80.54/0.4/0.31.452.360.70.41.46.49
FOMCEStat
(µA/µW)
70.66-----1.4-
FOMGlobal1930.4/0.29/0.221.342.271.090.21.44.6
SI, strong inversion; SBT, sub-threshold.
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Paul, A.; Renteria-Pinon, M.; Ramirez-Angulo, J.; Bolaños-Pérez, R.; Vázquez-Leal, H.; Huerta-Chua, J.; Diaz-Sánchez, A. Implementation of Power-Efficient Class AB Miller Amplifiers Using Resistive Local Common-Mode Feedback. J. Low Power Electron. Appl. 2021, 11, 31. https://0-doi-org.brum.beds.ac.uk/10.3390/jlpea11030031

AMA Style

Paul A, Renteria-Pinon M, Ramirez-Angulo J, Bolaños-Pérez R, Vázquez-Leal H, Huerta-Chua J, Diaz-Sánchez A. Implementation of Power-Efficient Class AB Miller Amplifiers Using Resistive Local Common-Mode Feedback. Journal of Low Power Electronics and Applications. 2021; 11(3):31. https://0-doi-org.brum.beds.ac.uk/10.3390/jlpea11030031

Chicago/Turabian Style

Paul, Anindita, Mario Renteria-Pinon, Jaime Ramirez-Angulo, Ricardo Bolaños-Pérez, Héctor Vázquez-Leal, Jesús Huerta-Chua, and Alejandro Diaz-Sánchez. 2021. "Implementation of Power-Efficient Class AB Miller Amplifiers Using Resistive Local Common-Mode Feedback" Journal of Low Power Electronics and Applications 11, no. 3: 31. https://0-doi-org.brum.beds.ac.uk/10.3390/jlpea11030031

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