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Article

A New Physical Design Flow for a Selective State Retention Based Approach

1
Department of Electrical and Computer Engineering, Ben Gurion University, Beer-Sheva 84105, Israel
2
Department of Electrical Engineering, Sami Shamoon College of Engineering, Beer-Sheva 84100, Israel
*
Author to whom correspondence should be addressed.
Academic Editor: Alex Serb
J. Low Power Electron. Appl. 2021, 11(3), 35; https://0-doi-org.brum.beds.ac.uk/10.3390/jlpea11030035
Received: 28 July 2021 / Revised: 5 September 2021 / Accepted: 9 September 2021 / Published: 13 September 2021
(This article belongs to the Special Issue Low Power Memory/Memristor Devices and Systems)
This research presents a novel approach for physical design implementation aimed for a System on Chip (SoC) based on Selective State Retention techniques. Leakage current has become a dominant factor in Very Large Scale Integration (VLSI) design. Power Gating (PG) techniques were first developed to mitigate these leakage currents, but they result in longer SoC wake-up periods due to loss of state. The common State Retention Power Gating (SRPG) approach was developed to overcome the PG technique’s loss of state drawback. However, SRPG resulted in a costly expense of die area overhead due to the additional state retention logic required to keep the design state when power is gated. Moreover, the physical design implementation of SRPG presents additional wiring due to the extra power supply network and power-gating controls for the state retention logic. This results in increased implementation complexity for the physical design tools, and therefore increases runtime and limits the ability to handle large designs. Recently published works on Selective State Retention Power Gating (SSRPG) techniques allow reducing the total amount of retention logic and their leakage currents. Although the SSRPG approach mitigates the overhead area and power limitations of the conventional SRPG technique, still both SRPG and SSRPG approaches require a similar extra power grid network for the retention cells, and the effect of the selective approach on the complexity of the physical design has not been yet investigated. Therefore, this paper introduces further analysis of the physical design flow for the SSRPG design, which is required for optimal cell placement and power grid allocation. This significantly increases the potential routing area, which directly improves the convergence time of the Place and Route tools. View Full-Text
Keywords: physical design; power grid; power-gating; SRPG; selective SRPG; floorplanning; place and route physical design; power grid; power-gating; SRPG; selective SRPG; floorplanning; place and route
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MDPI and ACS Style

Rabinowicz, J.; Greenberg, S. A New Physical Design Flow for a Selective State Retention Based Approach. J. Low Power Electron. Appl. 2021, 11, 35. https://0-doi-org.brum.beds.ac.uk/10.3390/jlpea11030035

AMA Style

Rabinowicz J, Greenberg S. A New Physical Design Flow for a Selective State Retention Based Approach. Journal of Low Power Electronics and Applications. 2021; 11(3):35. https://0-doi-org.brum.beds.ac.uk/10.3390/jlpea11030035

Chicago/Turabian Style

Rabinowicz, Joseph, and Shlomo Greenberg. 2021. "A New Physical Design Flow for a Selective State Retention Based Approach" Journal of Low Power Electronics and Applications 11, no. 3: 35. https://0-doi-org.brum.beds.ac.uk/10.3390/jlpea11030035

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