J. Low Power Electron. Appl., Volume 11, Issue 4 (December 2021) – 13 articles

Medication safety administration is a complicated process involving the information of patients, drugs, and data storage. The sensitive data transmitted through wireless sensor networks (WSNs) from Internet of things (IoT) over an insecure channel is vulnerable to several threats and needs proper attention to be secured from adversaries. Taking medication safety into consideration, this paper presents a secure authentication protocol for wireless medical sensor networks. The XOR scheme-based algorithm is applied to achieve the purposes of data confidentiality. The proposed architecture is realized as hardware in a field-programmable gate array (FPGA) device which acts as a secure edge computing device. The performance of the proposed protocol is evaluated and simulated via Verilog hardware description language. The functionality of the proposed protocol is verified using the Altera Quartus II software tool and implemented in the Altera Cyclone II DE2-70 FPGA development module. Furthermore, the output signals from the FPGA are measured in the 16702A logic analyzer system to demonstrate real-time functional verification. Full article

In this work, a multi-independent-output, multi-string, high-efficiency, boost-converter-based white LED (WLED) driver architecture is proposed. It utilizes a single inductor main switch with a common maximum duty cycle controller (MDCC) in the feedback loop. A simple pulse skipping controller (PSC) is utilized in each high-side switch of the multiple independent outputs. Despite the presence of multiple independent outputs, a single over-voltage protection (OVP) circuit is used at the output to protect the circuit from any voltage above 27 V. An open circuit in any of the strings is addressed, in addition to the LED’s short-circuit conditions. Excellent current matching between strings is achieved, despite the low ON-resistance ($R_{dson}$) of transistors used in the 40 nm process. Most circuits are designed in digital CMOS logic to overcome the extreme process variations in the 40 nm node. Compared to a single output parallel strings topology, a $50\%$ improvement in efficiency is achieved relative to extremely unbalanced strings. Three strings are used in this proposal, but more strings can be supported with the same topology. Each string is driven by a 25 mA current sink. An input voltage of 3.2–4.2 V and an output voltage up to 27 V are supported. Full article

IoT designers face the dual complexity of obtaining good application-level performance and user satisfaction under constraints on computing and power resources. We introduce a new IoT device for paper roll supply management in bathrooms and kitchens, both for homes and businesses, that is extremely cost effective and battery power-efficient. The device can be installed on practically any paper roll dispenser and makes use of existing Wi-Fi infrastructure. Despite Wi-Fi’s reputation as “unsupportive for power saving,” we introduce and experimentally validate a methodology for using Wi-Fi networks with low power utilization, resulting in a system that provides very good management of paper supplies while only requiring battery charging once every 3–4 months. The new device has the potential to provide more households and businesses with real-time, data-driven automated supply chains. Full article

Computational methods in memory array are being researched in many emerging memory technologies to conquer the ‘von Neumann bottleneck’. Resistive RAM (ReRAM) is a non-volatile memory, which supports Boolean logic operation, and adders can be implemented as a sequence of Boolean operations in the memory. While many in-memory adders have recently been proposed, their latency is exorbitant for increasing bit-width ($O\left(n\right)$). Decades of research in computer arithmetic have proven parallel-prefix technique to be the fastest addition technique in conventional CMOS-based binary adders. This work endeavors to move parallel-prefix addition to the memory array to significantly minimize the latency of in-memory addition. Majority logic was chosen as the fundamental logic primitive and parallel-prefix adders synthesized in majority logic were mapped to the memory array using the proposed algorithm. The proposed algorithm can be used to map any parallel-prefix adder to a memory array and mapping is performed in such a way that the latency of addition is minimized. The proposed algorithm enables addition in $O\left(log\right(n\left)\right)$ latency in the memory array. Full article

Data collection is one of the most relevant topics of modern automation and industry. It is usually a costly and time-consuming task, especially in continuous processes. Our case study takes place in a sugar cane mill. The required continuous operation of a belt conveyor for bagasse transportation makes it a critical system in the overall production process. Therefore, a predictive maintenance tool is highly applicable here. We identified bearing housings as critical points for data collection intended for prognostics of the conveyor. However, given the number of points, the cost of a commercial solution becomes unfeasible by our company. This paper reports the development of low-cost devices for measurements and wireless transmission of vibration and temperature data from bearing housings. We assessed several sensor options and made decisions based on a cost-suitability commitment, which led to the design of the electronic devices. The devices were tested for correct operation, reliability (99%), and relative measurement errors under 1.2%. From the tests, we conclude that our proposal is appropriate for our case study’s industrial needs and budget restrictions. Full article

The elliptic curve cryptosystem (ECC) has been proven to be vulnerable to non-invasive side-channel analysis attacks, such as timing, power, visible light, electromagnetic emanation, and acoustic analysis attacks. In ECC, the scalar multiplication component is considered to be highly susceptible to side-channel attacks (SCAs) because it consumes the most power and leaks the most information. In this work, we design a robust asynchronous circuit for scalar multiplication that is resistant to state-of-the-art timing, power, and fault analysis attacks. We leverage the genetic algorithm with multi-objective fitness function to generate a standard Boolean logic-based combinational circuit for scalar multiplication. We transform this circuit into a multi-threshold dual-spacer dual-rail delay-insensitive logic ($MT{D}^{3}L$) circuit. We then design point-addition and point-doubling circuits using the same procedure. Finally, we integrate these components together into a complete secure and dependable ECC processor. We design and validate the ECC processor using Xilinx ISE $14.7$ and implement it in a Xilinx Kintex-7 field-programmable gate array (FPGA). Full article

This paper presents a novel implementation of a digital-based Operational Transconductance Amplifier (OTA) which has been recently introduced in the technical literature as a fully digital alternative to the conventional differential pair to implement low voltage analog amplifiers and comparators. The proposed implementation does not make use of resistors, floating gate resistors nor C-Muller elements and is made up of only digital gates usually available in the standard cell libraries. The resulting analog circuit schematic can be described using structural VHDL or Verilog languages and is suitable to be integrated in an automatic synthesis and place and route flow for digital circuits. The proposed digital-based amplifier has been implemented in a commercial 130 nm CMOS process by using an automatic place and route flow for layout generation starting from the Verilog netlist. Post layout simulations are presented to show the performance of the proposed circuit and compare it against the state of the art. Full article

This paper describes the design methodology and calibration technique for a low-power digital pulse width modulation demodulator to enhance its robustness against the process, voltage, and temperature variations in different process corners, in addition to intra-die variability, which makes it a very good choice for implantable monitoring sensors. Furthermore, the core of the proposed demodulator is fully digital. Thus, along with the proposed design methodology, the proposed demodulator can be simply redesigned in advanced subnanometer CMOS technologies without much difficulty as compared to analog demodulators. The proposed demodulator consists of an envelope detector, a digitizer, a ring oscillator, and a data detector with digital calibration. All the proposed circuits are designed and simulated in the standard 1P9M TSMC’s 40 nm CMOS technology. Simulation results have shown that the circuit is capable of demodulating and recovering data from an input signal with a carrier frequency of 13.56 MHz and a data rate of 143 kB/s with an average power consumption of 5.62 $\mathsf{\mu }$W. Full article

In this paper, a new technique for improvement on the DC voltage gain, while keeping the high-linearity in symmetrical operational transconductance amplifier (OTA) bulk-driven (BD) topology is proposed. These features are achieved by allying two topological solutions: enhanced forward-body-biasing self-cascode current mirror, and source degeneration. The proposed concept is demonstrated through simulations with typical process parameters and Monte Carlo analysis on nominal transistors of the CMOS TSMC 180 nm node. Results indicate that the proposed OTA can achieve a very small transconductance, only 542 pA/V while keeping a voltage gain higher than 60 dB, 150 dB CMRR, and high linearity of 475 mVpp (1% THD), consuming only 1.9 nW for a supply voltage of 0.6 V. This set of features allows the proposed OTA to be an attractive solution for implementing OTA-C filters for the analog front-ends in wearable devices and bio-sensing. Full article

Today’s on-chip systems technology has grounded impressive advances in computing power and energy consumption. The choice of the right architecture depends on the application. In our case, we were studying vegetation monitoring algorithms in precision agriculture. This study presents a system based on a monitoring algorithm for agricultural fields, an electronic architecture based on a CPU-FPGA SoC system and the OpenCL parallel programming paradigm. We focused our study on our own dataset of agricultural fields to validate the results. The fields studied in our case are in the Guelmin-Oued noun region in the south of Morocco. These fields are divided into two areas, with a total surface of 3.44 Ha2 for the first field and 3.73 Ha2 for the second. The images were collected using a DJI-type unmanned aerial vehicle and an RGB camera. Performance evaluation showed that the system could process up to 86 fps versus 12 fps or 20 fps in C/C++ and OpenMP implementations, respectively. Software optimizations have increased the performance to 107 fps, which meets real-time constraints. Full article

Emerging Non-Volatile Memories (NVMs) such as Magnetic RAM (MRAM), Spin-Transfer Torque RAM (STTRAM), Phase Change Memory (PCM) and Resistive RAM (RRAM) are very promising due to their low (static) power operation, high scalability and high performance. However, these memories bring new threats to data security. In this paper, we investigate their vulnerability against Side Channel Attack (SCA). We assume that the adversary can monitor the supply current of the memory array consumed during read/write operations and recover the secret key of Advanced Encryption Standard (AES) execution. First, we show our analysis of simulation results. Then, we use commercial NVM chips to validate the analysis. We also investigate the effectiveness of encoding against SCA on emerging NVMs. Finally, we summarize two new flavors of NVMs that can be resilient against SCA. To the best of our knowledge, this is the first attempt to do a comprehensive study of SCA vulnerability of the majority of emerging NVM-based cache. Full article

A two-stage CMOS transconductance amplifier based on the inverter topology, suitable for very low supply voltages and exhibiting rail-to-rail output capability is presented. The solution consists of the cascade of a noninverting and an inverting stage, both characterized by having only two complementary transistors between the supply rails. The amplifier provides class-AB operation with quiescent current control obtained through an auxiliary loop that utilizes the MOSFETs body terminals. Simulation results, referring to a commercial 28 nm bulk technology, show that the quiescent current of the amplifier can be controlled quite effectively, even adopting a supply voltage as low as 0.5 V. The designed solution consumes around 500 nA of quiescent current in typical conditions and provides a DC gain of around 51 dB, with a unity gain frequency of 1 MHz and phase margin of 70 degrees, for a parallel load of 1 pF and 1.5 MΩ. Settling time at 1% is 6.6 μs, and white noise is 125 nV/$\sqrt{Hz}$. Full article

Several promising non-volatile memories (NVMs) such as magnetic RAM (MRAM), spin-transfer torque RAM (STTRAM), ferroelectric RAM (FeRAM), resistive RAM (RRAM), and phase-change memory (PCM) are being investigated to keep the static leakage within a tolerable limit. These new technologies offer high density and consume zero leakage power and can bridge the gap between processor and memory. The desirable properties of emerging NVMs make them suitable candidates for several applications including replacement of conventional memories. However, their unique characteristics introduce new data privacy and security issues. Some of them are already available in the market as discrete chips or a part of full system implementation. They are considered to become ubiquitous in future computing devices. Therefore, it is important to ensure their security/privacy issues. Note that these NVMs can be considered for cache, main memory, or storage application. They are also suitable to implement in-memory computation which increases system throughput and eliminates von Neumann bottleneck. Compute-capable NVMs impose new security and privacy challenges that are fundamentally different than their storage counterpart. This work identifies NVM vulnerabilities and attack vectors originating from the device level all the way to circuits and systems, considering both storage and compute applications. We also summarize the circuit/system-level countermeasures to make the NVMs robust against security and privacy issues. Full article