Journal of Low Power Electronics and Applications

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Open AccessEditorial

Acknowledgement to Reviewers of the Journal of Low Power Electronics and Applications in 2013

by JLPEA Editorial Office

J. Low Power Electron. Appl. 2014, 4(1), 63-64; https://0-doi-org.brum.beds.ac.uk/10.3390/jlpea4010063 - 28 Feb 2014

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Abstract

The editors of the Journal of Low Power Electronics and Applications would like to express their sincere gratitude to the following reviewers for assessing manuscripts in 2013. [...] Full article

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Open AccessArticle

Two-Layer Error Control Codes Combining Rectangular and Hamming Product Codes for Cache Error

by Meilin Zhang and Paul Ampadu

J. Low Power Electron. Appl. 2014, 4(1), 44-62; https://0-doi-org.brum.beds.ac.uk/10.3390/jlpea4010044 - 27 Feb 2014

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Abstract

We propose a novel two-layer error control code, combining error detection capability of rectangular codes and error correction capability of Hamming product codes in an efficient way, in order to increase cache error resilience for many core systems, while maintaining low power, area [...] Read more.

We propose a novel two-layer error control code, combining error detection capability of rectangular codes and error correction capability of Hamming product codes in an efficient way, in order to increase cache error resilience for many core systems, while maintaining low power, area and latency overhead. Based on the fact of low latency and overhead of rectangular codes and high error control capability of Hamming product codes, two-layer error control codes employ simple rectangular codes for each cache line to detect cache errors, while loading the extra Hamming product code checks bits in the case of error detection; thus enabling reliable large-scale cache operations. Analysis and experiments are conducted to evaluate the cache fault-tolerant capability of various existing solutions and the proposed approach. The results show that the proposed approach can significantly increase Mean-Error-To-Failure (METF) and Mean-Time-To-failure (MTTF) up to 2.8×, reduce storage overhead by over 57%, and increase instruction per-cycle (IPC) up to 7%, compared to complex four-way 4EC5ED; and it increases METF and MTTF up to 133×, reduces storage overhead by over 11%, and achieves a similar IPC compared to simple eight-way single-error correcting double-error detecting (SECDED). The cost of the proposed approach is no more than 4% external memory access overhead. Full article

(This article belongs to the Special Issue Resiliency, Robustness, and Reliability (R3) for VLSI Circuits and Systems)

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681 KiB

Open AccessArticle

Design of Processors with Reconfigurable Microarchitecture

by Andrey Mokhov, Maxim Rykunov, Danil Sokolov and Alex Yakovlev

J. Low Power Electron. Appl. 2014, 4(1), 26-43; https://0-doi-org.brum.beds.ac.uk/10.3390/jlpea4010026 - 20 Jan 2014

Cited by 10 | Viewed by 7064

Abstract

Energy becomes a dominating factor for a wide spectrum of computations: from intensive data processing in “big data” companies resulting in large electricity bills, to infrastructure monitoring with wireless sensors relying on energy harvesting. In this context it is essential for a computation [...] Read more.

Energy becomes a dominating factor for a wide spectrum of computations: from intensive data processing in “big data” companies resulting in large electricity bills, to infrastructure monitoring with wireless sensors relying on energy harvesting. In this context it is essential for a computation system to be adaptable to the power supply and the service demand, which often vary dramatically during runtime. In this paper we present an approach to building processors with reconfigurable microarchitecture capable of changing the way they fetch and execute instructions depending on energy availability and application requirements. We show how to use Conditional Partial Order Graphs to formally specify the microarchitecture of such a processor, explore the design possibilities for its instruction set, and synthesise the instruction decoder using correct-by-construction techniques. The paper is focused on the design methodology, which is evaluated by implementing a power-proportional version of Intel 8051 microprocessor. Full article

(This article belongs to the Special Issue Selected Papers from FTFC 2013 Conference)

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598 KiB

Open AccessArticle

Mechanisms of Low-Energy Operation of XCT-SOI CMOS Devices—Prospect of Sub-20-nm Regime

by Yasuhisa Omura and Daiki Sato

J. Low Power Electron. Appl. 2014, 4(1), 15-25; https://0-doi-org.brum.beds.ac.uk/10.3390/jlpea4010015 - 10 Jan 2014

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Abstract

This paper describes the performance prospect of scaled cross-current tetrode (XCT) CMOS devices and demonstrates the outstanding low-energy aspects of sub-30-nm-long gate XCT-SOI CMOS by analyzing device operations. The energy efficiency improvement of such scaled XCT CMOS circuits (two orders higher) stems from [...] Read more.

This paper describes the performance prospect of scaled cross-current tetrode (XCT) CMOS devices and demonstrates the outstanding low-energy aspects of sub-30-nm-long gate XCT-SOI CMOS by analyzing device operations. The energy efficiency improvement of such scaled XCT CMOS circuits (two orders higher) stems from the “source potential floating effect”, which offers the dynamic reduction of effective gate capacitance. It is expected that this feature will be very important in many medical implant applications that demand a long device lifetime without recharging the battery. Full article

(This article belongs to the Special Issue Selected Papers from FTFC 2013 Conference)

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Open AccessArticle

Compact Modeling Solutions for Oxide-Based Resistive Switching Memories (OxRAM)

by Marc Bocquet, Hassen Aziza, Weisheng Zhao, Yue Zhang, Santhosh Onkaraiah, Christophe Muller, Marina Reyboz, Damien Deleruyelle, Fabien Clermidy and Jean-Michel Portal

J. Low Power Electron. Appl. 2014, 4(1), 1-14; https://0-doi-org.brum.beds.ac.uk/10.3390/jlpea4010001 - 09 Jan 2014

Cited by 27 | Viewed by 8667

Abstract

Emerging non-volatile memories based on resistive switching mechanisms attract intense R&D efforts from both academia and industry. Oxide-based Resistive Random Acces Memories (OxRAM) gather noteworthy performances, such as fast write/read speed, low power and high endurance outperforming therefore conventional Flash memories. To fully [...] Read more.

Emerging non-volatile memories based on resistive switching mechanisms attract intense R&D efforts from both academia and industry. Oxide-based Resistive Random Acces Memories (OxRAM) gather noteworthy performances, such as fast write/read speed, low power and high endurance outperforming therefore conventional Flash memories. To fully explore new design concepts such as distributed memory in logic, OxRAM compact models have to be developed and implemented into electrical simulators to assess performances at a circuit level. In this paper, we present compact models of the bipolar OxRAM memory based on physical phenomenons. This model was implemented in electrical simulators for single device up to circuit level. Full article

(This article belongs to the Special Issue Selected Papers from FTFC 2013 Conference)

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J. Low Power Electron. Appl., Volume 4, Issue 1 (March 2014) – 5 articles , Pages 1-64

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