Analysis of Threshold Voltage Flexibility in Ultrathin-BOX SOI FinFETs ^†

Abstract

A threshold voltage (V_th) controllable multigate FinFET on a 10-nm-thick ultrathin BOX (UTB) SOI substrate have been investigated. It is revealed that the V_th of the FinFET on the UTB SOI substrate is effectively modulated thanks to the improved coupling between the Si channel and the back gate. We have also carried out analysis of the V_th controllability in terms of the size dependence such as the gate length (L_G) and the fin width (T_Fin).

1. Introduction

Recently, complementary metal oxide semiconductor (CMOS) device technology has faced several difficulties. Short channel effects (SCEs) such as threshold voltage roll-off and sub-threshold slope (s-slope) degradation caused by the reduced drivability of the gate electrode cause significant increase in power consumption and become a limiting factor in MOS devices [1,2]. In addition, variability of the CMOS device increases and reduces the yield of the CMOS circuit [3]. Fortunately, fin-type MOS field effect transistors (FinFETs) provide a potential solution for the nano-scale CMOS technology thanks to their high drive current while maintaining a low sub-threshold (s-) slope [4,5]. However, for FinFETs, adjustment of the threshold voltage (V_th) is still a tough issue. One way of controlling the V_th of the MG MOSFET is to tune the work function of the gate electrode [6]. However, selection of the metal with the appropriate work function is difficult. A doped silicon channel is effective for V_th tuning; however, it cause severe variability due to the random dopant fluctuation [7,8].

The other way of controlling the V_th of the FinFET is by using the substrate back bias using the SOI substrate [9,10]. In fact, V_th control by the substrate back bias has been investigated for the planar devices [11,12,13,14]. However, effectiveness of the back gate bias on the V_th of the FinFET is different due to the narrow channel. Recently, we have demonstrated a flexible V_th tuning for the FinFET by controlling the back bias using a 10-nm-thick ultra-thin (UT) buried oxide (BOX) silicon on insulator (SOI) substrate to demonstrate effectiveness of UTBOX for the vth control of the FinFET [15,16]. Moreover, we have flexibly controlled the V_th by adding the second gate of the independent-double-gate FinFET [17]. In this study, we have extended the analysis of V_th flexibility in terms of the L_G and the T_Fin dependence of the V_th controllability using the 10 nm-thick UTBOX SOI substrate.

2. Experimental

2.1. MOS Capacitor

Prior to the device fabrication, we have evaluated the quality of the UTBOX by comparing the characteristics with thermal SiO₂. The test structure used in this study is illustrated in Figure 1. The thermal SiO₂ grown at 850 °C is covered with the chemical-vapor-deposited 50-nm-thick poly-Si. Ion implantation was carried out into the top Si layer to fabricate the gate electrode. The thermally grown SiO₂ with the polycrystalline-Si electrode is used as a reference sample.

Figure 1. The MOS capacitor test structure. (a) Ultrathin (UT) buried oxide (BOX) silicon on insulator (SOI) substrate; (b) Thermal SiO₂ test structure.

Figure 1. The MOS capacitor test structure. (a) Ultrathin (UT) buried oxide (BOX) silicon on insulator (SOI) substrate; (b) Thermal SiO₂ test structure.

2.2. Device Fabrication

In this study, we have used 200-mm UTBOX SOI wafers as an initial material and have fabricated the FinFET devices on a UTBOX SOI substrate. The ellipsometrically measured thickness of the UTBOX was 10 nm. We have also fabricated the FinFET on the 120-nm-thick BOX for comparison. The fabrication process flow is summarized in Figure 2. A 50-nm-thick non-doped silicate glass (NSG) layer and the electron beam (EB) resist masks were formed to make hard masks on the wafer. To fabricate vertical Si-fins, the SOI layer was etched by a conventional reactive ion etching (RIE) using a Cl₂ inductively coupled plasma (ICP) as schematically shown in Figure 2. After the Si-fin etching, a 2.5-nm-thick gate-oxide was formed at 850 °C followed by the TiN and n+ polycrystalline-Si (poly-Si) gate formation using EB lithography and the RIE. After the gate electrode was formed, a shallow implantation into the extension of the source/drain (S/D) was performed. To distribute impurity atoms uniformly into the vertical channel, 60-degree tilted implantation was carried out at an acceleration energy of 5 keV and a dose of 2 × 10¹⁴ cm⁻² in each side [18]. S/D implantation was performed at an acceleration energy of 10 keV and a dose of 1.5 × 10¹⁵ cm⁻² after a 50-nm-thick gate-sidewall was formed by using CVD grown SiO₂. The acceleration energy was set to 10 keV to preserve the seed-crystal layer for the recrystalline annealing. Figure 3 shows the cross sectional transmission electron microscope (TEM) image of the fabricated FinFET and the plane scanning electron microscope (SEM) image of the SRAM cell. The FinFET on the UTBOX SOI is successfully fabricated. The fin height was measured as 30 nm.

Figure 2. Schematic process flow for the fabrication of fin-type MOS field effect transistors (FinFETs).

Figure 2. Schematic process flow for the fabrication of fin-type MOS field effect transistors (FinFETs).

Figure 3. (a) SEM image of the fabricated FinFET, (b) Cross-sectional TEM image of the fabricated FinFET.

Figure 3. (a) SEM image of the fabricated FinFET, (b) Cross-sectional TEM image of the fabricated FinFET.

3. Results and Discussion

Figure 4 compares capacitance-voltage (C-V) characteristics of the UTBOX layer and the thermal SiO₂. It is found that the C-V characteristics of the UTBOX layer are similar to that of the thermal SiO₂. The capacitance equivalent thickness (CET) of the UTBOX is measured as 11.5 nm and the uniformity of the UTBOX thickness is as good as that of the thermal SiO₂. Figure 5 compares the current-voltage (I-V) characteristics of the MOS capacitor using the UTBOX and the thermal SiO₂. The I-V characteristics of the MOS capacitor with the same dielectric thickness are also the same. Figure 6 shows the gate voltage of the MOS capacitor where the leakage current exceeds 10⁻⁷ A/cm² as a function of the oxide thickness. The gate voltage of the UTBOX completely follows the trend of the thermal SiO₂. These results strongly indicate that quality of the UTBOX and its interface is as good as that of the thermal SiO₂.

Figure 4. C-V characteristics of the MOS capacitor: (a) UTBOX; (b) thermal SiO₂.

Figure 4. C-V characteristics of the MOS capacitor: (a) UTBOX; (b) thermal SiO₂.

Figure 5. I-V characteristics of the MOS capacitor: (a) UTBOX; (b) Thermal SiO₂. The glitches in the figure indicate the fluctuation of the breakdown in different MOS capacitors.

Figure 5. I-V characteristics of the MOS capacitor: (a) UTBOX; (b) Thermal SiO₂. The glitches in the figure indicate the fluctuation of the breakdown in different MOS capacitors.

Figure 6. The gate voltage of the MOS capacitor where the leakage current exceeds 10⁻⁷ A/cm² as a function of the oxide thickness.

Figure 6. The gate voltage of the MOS capacitor where the leakage current exceeds 10⁻⁷ A/cm² as a function of the oxide thickness.

Figure 7 shows the I_D-V_G characteristics of the FinFET with the UTBOX SOI and the conventional thick BOX SOI. We revealed that the I_D-V_G characteristics the FinFET on the UTBOX SOI could be flexibly modified by applying the substrate bias voltage. We also found that the FinFET with the thick T_Fin was effective for the V_th modulation. Figure 8 shows the V_th as a function of the V_sub. The V_th is taken by the constant current method. The I_D-V_G characteristics are fixed and thus the V_th is fixed with the conventional thick BOX substrate. Also, the effectiveness of the thick T_Fin for the V_th modulation is clearly shown. This is caused by the increased coupling between the Si body and the back gate.

Figure 7. I_D-V_G characteristics of the FinFETs with the UTBOX and the conventional thick BOX SOI. The substrate bias voltages are ranging from −1 V to 1 V with a 0.5 V step: (a) T_Fin= 50 nm, L_G= 40nm, BOX 10 nm; (b) T_Fin= 70 nm, L_G= 40nm, BOX 10 nm; (c) T_Fin= 50 nm, L_G= 40nm, BOX 120 nm.

Figure 7. I_D-V_G characteristics of the FinFETs with the UTBOX and the conventional thick BOX SOI. The substrate bias voltages are ranging from −1 V to 1 V with a 0.5 V step: (a) T_Fin= 50 nm, L_G= 40nm, BOX 10 nm; (b) T_Fin= 70 nm, L_G= 40nm, BOX 10 nm; (c) T_Fin= 50 nm, L_G= 40nm, BOX 120 nm.

Figure 8. The V_th of the FinFET as a function for the substrate bias.

Figure 8. The V_th of the FinFET as a function for the substrate bias.

Figure 9 summarizes the size dependence of the body factor γ determined by the ΔV_th/ΔV_sub. The γ is increased by increasing the T_Fin supporting the effectiveness of the thick T_Fin for the V_th modulation. In contrast to the T_Fin dependence, the opposite trend with the L_G is shown and the γ is increased by reducing the L_G. Moreover, the γ exceeded more than 0.1 with the 70-nm-thick fin thanks to the 10-nm-thick UTB SOI. To understand this L_G dependence, the short channel effect represented by the V_th roll-off is evaluated as shown in Figure 10. We found that the V_th roll-off is more sever for the FinFET with the positive V_sub, small L_G, and the thick T_Fin. Thus, the γ becomes higher for the FinFET with the small L_G and the thick T_Fin due to the V_th roll-off. This result is consistent with the previous report on the nanowire FET with the 20-nm-thick BOX SOI [19].

Figure 11 shows the s-slope of the FinFET as a function of the L_G. The increase of the s-slope by reducing the L_G due to the short channel effect is clearly shown. It is noteworthy that the s-slope of the FinFET with the negative V_sub is smaller than that of the positive V_sub. Thus, the body bias is also effective for suppressing the short channel effects.

Figure 9. The size dependence of the body factor γ determined by the ΔV_th/ΔV_sub, (a) TFin dependence; (b) L_G dependence.

Figure 9. The size dependence of the body factor γ determined by the ΔV_th/ΔV_sub, (a) TFin dependence; (b) L_G dependence.

Figure 10. V_th roll-off characteristics for the FinFET with the different T_Fin.

Figure 10. V_th roll-off characteristics for the FinFET with the different T_Fin.

Figure 11. The s-slope of the FinFET as a function of the L_G.

Figure 11. The s-slope of the FinFET as a function of the L_G.

4. Conclusions

The V_th controllable FinFETs using the 10-nm-thick UTB SOI substrate have been successfully fabricated and controllability of the V_th is analyzed in terms of the size dependence. It is shown that the body factor is increased by increasing the T_Fin and reducing the L_G and it exceeded above 0.1 thanks to the 10-nm-thick UTBOX SOI. The back gate bias is also effective for the reduction of the s-slope. Thus, the UTBOX SOI is promising for the modulation of the V_th and improvement of the short channel effects for the scaled FinFET.