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Ultralow-Power SOTB CMOS Technology Operating Down to 0.4 V

1
Low-Power Electronics Association & Project, Tsukuba, Ibaraki 305-8569, Japan
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Department of Engineering Science, Graduate School of Informatics and Engineering Departments, The University of Electro-Communications, Chofu, Tokyo 182-8585, Japan
3
Institute of Industrial Science, The University of Tokyo, Meguro, Tokyo 153-8505, Japan
*
Author to whom correspondence should be addressed.
This article is based on “Vmin = 0.4 V LSIs are the real with Silicon-on-Thin-Buried-Oxide (SOTB)—How is the application with ‘Perpetuum-Mobile’ micro-controller with SOTB?”, which appeared in Proceedings of the IEEE 2013 SOI-3D-Subthreshold Microelectronics Technology Unified Conference (S3S) ©2013 IEEE.
J. Low Power Electron. Appl. 2014, 4(2), 65-76; https://0-doi-org.brum.beds.ac.uk/10.3390/jlpea4020065
Received: 27 February 2014 / Revised: 7 April 2014 / Accepted: 10 April 2014 / Published: 24 April 2014
(This article belongs to the Special Issue Selected Papers from IEEE S3S Conference 2013)
Ultralow-voltage (ULV) CMOS will be a core building block of highly energy efficient electronics. Although the operation at the minimum energy point (MEP) is effective for ULP CMOS circuits, its slow operation speed often means that it is not used in many applications. The silicon-on-thin-buried-oxide (SOTB) CMOS is a strong candidate for the ultralow-power (ULP) electronics because of its small variability and back-bias control. Proper power and performance optimization with adaptive Vth control taking advantage of SOTB’s features can achieve the ULP operation with acceptably high speed and low leakage. This paper describes our results on the ULV operation of logic circuits (CPU, SRAM, ring oscillator and other logic circuits) and shows that the operation speed is now sufficiently high for many ULP applications. The “Perpetuum-Mobile” micro-controllers operating down to 0.4 V or lower are expected to be implemented in a huge number of electronic devices in the internet-of-things (IoT) era. View Full-Text
Keywords: ultralow power; ultralow voltage; CMOS; minimum energy point; variability; back bias; FDSOI; silicon-on-thin-buried-oxide (SOTB); thin BOX ultralow power; ultralow voltage; CMOS; minimum energy point; variability; back bias; FDSOI; silicon-on-thin-buried-oxide (SOTB); thin BOX
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MDPI and ACS Style

Sugii, N.; Yamamoto, Y.; Makiyama, H.; Yamashita, T.; Oda, H.; Kamohara, S.; Yamaguchi, Y.; Ishibashi, K.; Mizutani, T.; Hiramoto, T. Ultralow-Power SOTB CMOS Technology Operating Down to 0.4 V. J. Low Power Electron. Appl. 2014, 4, 65-76. https://0-doi-org.brum.beds.ac.uk/10.3390/jlpea4020065

AMA Style

Sugii N, Yamamoto Y, Makiyama H, Yamashita T, Oda H, Kamohara S, Yamaguchi Y, Ishibashi K, Mizutani T, Hiramoto T. Ultralow-Power SOTB CMOS Technology Operating Down to 0.4 V. Journal of Low Power Electronics and Applications. 2014; 4(2):65-76. https://0-doi-org.brum.beds.ac.uk/10.3390/jlpea4020065

Chicago/Turabian Style

Sugii, Nobuyuki, Yoshiki Yamamoto, Hideki Makiyama, Tomohiro Yamashita, Hidekazu Oda, Shiro Kamohara, Yasuo Yamaguchi, Koichiro Ishibashi, Tomoko Mizutani, and Toshiro Hiramoto. 2014. "Ultralow-Power SOTB CMOS Technology Operating Down to 0.4 V" Journal of Low Power Electronics and Applications 4, no. 2: 65-76. https://0-doi-org.brum.beds.ac.uk/10.3390/jlpea4020065

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