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Journal: J. Low Power Electron. Appl., 2014
Volume: 4
Number: 168

Article: Study of Back Biasing Schemes for ULV Logic from the Gate Level to the IP Level
Authors: by Guerric De Streel and David Bol
Link: https://0-www-mdpi-com.brum.beds.ac.uk/2079-9268/4/3/168

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