Next Article in Journal
39 fJ/bit On-Chip Identification ofWireless Sensors Based on Manufacturing Variation
Previous Article in Journal
Embedded Memory Hierarchy Exploration Based on Magnetic Random Access Memory
Article

The Impact of Process Scaling on Scratchpad Memory Energy Savings

1
Department of Electrical & Computer Engineering, University of Utah, 1692 Warnock Engineering Bldg., 72 S. Central Campus Dr., Salt Lake City, UT 84112, USA
2
Division of Biology and Biological Engineering, California Institute of Technology, Mail Code 216-76, 1200 E, California Blvd., Pasadena, CA 91125, USA
3
Charleston Rd, Palo Alto, CA 94303, USA
*
Author to whom correspondence should be addressed.
The manuscript is an extended version of a conference paper titled “Scratchpad Memories in the Context of Process Scaling”, which was presented at the 2011 IEEE 54th International Midwest Symposium on Circuits and Systems (MWSCAS).
J. Low Power Electron. Appl. 2014, 4(3), 231-251; https://0-doi-org.brum.beds.ac.uk/10.3390/jlpea4030231
Received: 11 June 2014 / Revised: 22 August 2014 / Accepted: 1 September 2014 / Published: 9 September 2014
Scratchpad memories have been shown to reduce power consumption, but the different characteristics of nanometer scale processes, such as increased leakage power, motivate an examination of how the benefits of these memories change with process scaling. Process and application characteristics affect the amount of energy saved by a scratchpad memory. Increases in leakage as a percentage of total power particularly impact applications that rarely access memory. This study examines how the benefits of scratchpad memories have changed in newer processes, based on the measured performance of the WIMS (Wireless Integrated MicroSystems) microcontroller implemented in 180- and 65-nm processes and upon simulations of this microcontroller implemented in a 32-nm process. The results demonstrate that scratchpad memories will continue to improve the power dissipation of many applications, given the leakage anticipated in the foreseeable future. View Full-Text
Keywords: scratchpad memory; loop cache; process scaling; low power; microprocessor; computer architecture; embedded scratchpad memory; loop cache; process scaling; low power; microprocessor; computer architecture; embedded
Show Figures

Graphical abstract

MDPI and ACS Style

Redd, B.; Kellis, S.; Gaskin, N.; Brown, R. The Impact of Process Scaling on Scratchpad Memory Energy Savings. J. Low Power Electron. Appl. 2014, 4, 231-251. https://0-doi-org.brum.beds.ac.uk/10.3390/jlpea4030231

AMA Style

Redd B, Kellis S, Gaskin N, Brown R. The Impact of Process Scaling on Scratchpad Memory Energy Savings. Journal of Low Power Electronics and Applications. 2014; 4(3):231-251. https://0-doi-org.brum.beds.ac.uk/10.3390/jlpea4030231

Chicago/Turabian Style

Redd, Bennion, Spencer Kellis, Nathaniel Gaskin, and Richard Brown. 2014. "The Impact of Process Scaling on Scratchpad Memory Energy Savings" Journal of Low Power Electronics and Applications 4, no. 3: 231-251. https://0-doi-org.brum.beds.ac.uk/10.3390/jlpea4030231

Find Other Styles

Article Access Map by Country/Region

1
Only visits after 24 November 2015 are recorded.
Back to TopTop