J. Low Power Electron. Appl., Volume 8, Issue 1 (March 2018) – 8 articles

Due to their high power density and appropriateness for small circuits integration, switched-capacitor (SC) converters have gotten more interests. Applying the soft-charging technique effectively eliminates the current transient that results in a higher power density and a higher fundamental efficiency. Achieving the complete soft-charging operation is impossible by using the conventional control diagram for any SC converter topology. In this paper, we proposed a split-phase control to achieve the complete soft-charging operation in a power switched-capacitor (PSC) converter. The proposed control diagram was designed for a 1-to-4 PSC converter (two-level of the PSC converter). The implemented split-phase diagram successfully controls eight switches to exhibit eight modes of operation. In addition to the current transient elimination, the complete soft-charging allows us to reduce capacitor sizes. However, reducing capacitor size negatively increases the output voltage ripple; hence, an output LC filter is needed. The complete soft-charging achievement accomplishes a 96% efficiency due to the lower output impedance and the dead time switching. LT-Spice software has been used to verify the proposed control and the results were compared with hard-charging and incomplete soft-charging operations. Full article

Connected component analysis is one of the most fundamental steps used in several image processing systems. This technique allows for distinguishing and detecting different objects in images by assigning a unique label to all pixels that refer to the same object. Most of the previous published algorithms have been designed for implementation by software. However, due to the large number of memory accesses and compare, lookup, and control operations when executed on a general-purpose processor, they do not satisfy the speed performance required by the next generation high performance computer vision systems. In this paper, we present the design of a new Connected Component Labeling hardware architecture suitable for high performance heterogeneous image processing of embedded designs. When implemented on a Zynq All Programmable-System on Chip (AP-SOC) 7045 chip, the proposed design allows a throughput rate higher of 220 Mpixels/s to be reached using less than 18,000 LUTs and 5000 FFs, dissipating about 620 μJ. Full article

The Internet-of-Things (IoT) paradigm is under constant development and is being enabled by the latest research work from both industrial and academic communities. Among the many contributions in such diverse areas as sensor manufacturing, network protocols, and wireless communications, energy harvesting techniques stand out as a key enabling technology for the realization of batteryless IoT end-node systems. In this paper, we give an overview of the recent developments in circuit design for ultra-low power management units (PMUs), focusing mainly in the architectures and techniques required for energy harvesting from multiple heterogeneous sources. The paper starts by discussing a general structure for IoT end-nodes and the main characteristics of PMUs for energy harvesting. Then, an overview is given of different published works for multisource power harvesting, observing their main advantages and disadvantages and comparing their performance. Finally, some open areas of research in multisource harvesting are observed and relevant conclusions are given. Full article

With aggressive scaling of device geometries, density of manufacturing faults is expected to increase. Therefore, yield of complex Multi-Processor Systems-on-Chips (MP-SoCs) will decrease due to higher probability of manufacturing defects especially, in dies with large area. Therefore, disintegration of large SoCs into smaller chips called chiplets will improve yield and cost of complex platform-based systems. This will also provide functional flexibility, modular scalability as well as the capability to integrate heterogeneous architectures and technologies in a single unit. However, with scaling of the number of chiplets in such a system, the shared resources in the system such as the interconnection fabric and memory modules will become performance bottlenecks. Additionally, the integration of heterogeneous chiplets operating at different frequencies and voltages can be challenging. State-of-the-art inter-chip communication requires power-hungry high-speed I/O circuits and data transfer over long wired traces on substrates. This increases energy consumption and latency while decreasing data bandwidth for chip-to-chip communication. In this paper, we explore the advances and the challenges of interconnecting a multi-chip system with millimeter-wave (mm-wave) wireless interconnects from a variety of perspectives spanning multiple aspects of the wireless interconnection design. Our discussion on the recent advances include aspects such as interconnection topology, physical layer, Medium Access Control (MAC) and routing protocols. We also present some potential paradigm-shifting applications as well as complementary technologies of wireless inter-chip communications. Full article

Low power, low cost inductively powered passive biotelemetry system involving fully customized RFID/NFC interface base SoC has gained popularity in the last decades. However, most of the SoCs developed are application specific and lacks either on-chip computational or sensor readout capability. In this paper, we present design details of a programmable passive SoC in compliance with ISO 15693/NFC5 standard for biomedical applications. The integrated system consists of a 32-bit microcontroller, a sensor readout circuit, a 12-bit SAR type ADC, 16 kB RAM, 16 kB ROM and other digital peripherals. The design is implemented in a 0.18 $\mathsf{\mu }$ m CMOS technology and used a die area of 1.52 mm × 3.24 mm. The simulated maximum power consumption of the analog block is 592 $\mathsf{\mu }$ W. The number of external components required by the SoC is limited to an external memory device, sensors, antenna and some passive components. The external memory device contains the application specific firmware. Based on the application, the firmware can be modified accordingly. The SoC design is suitable for medical implants to measure physiological parameters like temperature, pressure or ECG. As an application example, the authors have proposed a bioimplant to measure arterial blood pressure for patients suffering from Peripheral Artery Disease (PAD). Full article

This paper deals with the modeling of bond graph buck converter systems. The bond graph formalism, which represents a heterogeneous formalism for physical modeling, is used to design a sub-model of a power MOSFET and PiN diode switchers. These bond graph models are based on the device’s electrical elements. The application of these models to a bond graph buck converter permit us to obtain an invariant causal structure when the switch devices change state. This paper shows the usefulness of the bond graph device’s modeling to simulate an implicit bond graph buck converter. Full article

This paper presents an algorithm/architecture and Hardware/Software co-designs for implementing a digital edge computing layer on a Zynq platform in the context of the Internet of Multimedia Things (IoMT). Traditional cloud computing is no longer suitable for applications that require image processing due to cloud latency and privacy concerns. With edge computing, data are processed, analyzed, and encrypted very close to the device, which enable the ability to secure data and act rapidly on connected things. The proposed edge computing system is composed of a reconfigurable module to simultaneously compress and encrypt multiple images, along with wireless image transmission and display functionalities. A lightweight implementation of the proposed design is obtained by approximate computing of the discrete cosine transform (DCT) and by using a simple chaotic generator which greatly enhances the encryption efficiency. The deployed solution includes four configurations based on HW/SW partitioning in order to handle the compromise between execution time, area, and energy consumption. It was found with the experimental setup that by moving more components to hardware execution, a timing speedup of more than nine times could be achieved with a negligible amount of energy consumption. The power efficiency was then enhanced by a ratio of 7.7 times. Full article