An Improved CMOS Design of Op-Amp Comparator with Gain Boosting Technique for Data Converter Circuits

Abstract

A modified architecture of a comparator to achieve high slew rate and boosted gain with an improvement in gain design error is introduced and investigated in this manuscript. It employs the conventional architecture of common-mode current feedback with the modified gain booster topology to increase gain, slew rate, and reduced gain error from the conventional structure. Observation from the simulation results concludes that the modified structure using 24 transistors shows power dissipation of 362.29 μW in 90 nm CMOS technology by deploying a supply voltage of 0.7 V, which is a 70% reduction as compared to the usual common mode feedback (CMFD) structure. The symmetric slew rate of 839.99 V/µs for both charging and discharging is obtained, which is 173% more than the standard CMFD structure. A reduction of 0.61% in gain error is achieved through this architecture. A SPICE simulation tool based on 90 nm CMOS technology is employed for executing the Monte Carlo simulations. A brief comparison with earlier CMFD structures shows improved performance parameters in terms of power consumption and slew rate with the reduction in gain error.

1. Introduction

One of the most significant and critical elements of analog integrated circuits are comparators [1,2]. Comparators play a pivotal role in regulating the decisive parameters of many imperative analog and digital circuits [3]. Data converters are one such kind of circuit as their speed of conversion, resolution, and power consumption, along with other prominent parameters, depends directly on it [4,5,6]. The CMOS fabrication technologies have entered the submicron domain, and transistor sizing is scaling down to nano-dimension levels. This, in turn, restrains the maximum power supply voltage in ICs eventually allowing an audit of the fidelity of these MOS transistors [6,7,8]. This effect is positive for digital ICs, but has an adverse impact on analog ICs. The primary consequences of this scaling are reduced output conductance and small output voltage swing and, hence, led to decreased DC gains [9]. Thus, the op-amp comparators designed under such CMOS technologies with restrained supply voltage will not be able to comply with the designer requisites and, thus, adversely affect the performance parameters of abstract circuits that employ these comparators as their core element [10]. Data converters, such as ADC and DAC conversion speed and accuracy, sturdily depend upon the comparator’s capability to detect the smallest voltage levels [11,12]. The op-amp comparators with a high slew rate and high gain with high accuracy are to be designed in order to attain these excellent parameters in data converters [13,14].

A modified architecture is proposed in this paper, which suggests useful data information in understanding the performance of op-amp comparators. Better optimization for providing an accurate differential mode gain and high slew rate is achieved through this design [14]. Thus, to meet the requirement of gain in the op-amp comparator modified architecture with gain a boosting block is used. Common mode feedback (current feedback) is used in the circuit of the op-amp comparator to maintain the output node at constant DC [15]. Current biasing of the modified design is done by using current mirrors [16]. The common mode feedback with modified architecture and gain boosting block provides a very high gain with an improved gain error by more than 95% [17]. The use of the cascode current mirror structure in the current feedback amplifier, in addition to the high gain, also provides a very high slew rate [18].

This manuscript is further assembled as follows: Section 2 dispenses a quick overview of the modified circuit description in the form of a circuit. Section 3 provides details about the simulation results and explanations of the analysis of the modified architecture. Section 4 contains comparisons of the modified architecture with existing op-amp comparators, like DCFIA, SCFIA [19], and CMFD [20,21,22,23], which utilize common mode current feedback through tables and graphs. The paper concludes with Section 5.

2. Circuit Description

Figure 1 depicts the block architecture for common-mode feedback structure [20]. It incorporates three major blocks. First, there is a fully differential pair amplifier that works in balanced mode. Next, there is a sensing circuit stage which senses common mode output signal. In the final stage, there is a comparator which compares this output common mode signal with a reference voltage and feeds the rectified signal back to the fully differential pair that, in turn, adjusts according to this signal [21]. The reference voltage ideally equals 0 V. Thus, a rectified signal is formed and applied to the fully differential pair, such that, finally, the alteration signal becomes near to zero. The rectified signal is a subtracted value taken by subtracting the reference voltage and the common-mode signal [22,24].

Figure 2 shows the entire architecture of the modified op-amp comparator (GB-CMFD) with gain boosting and common mode current feedback [23,24,25]. Inputs are given to the dual input fully differential pair that comprises of M1 and M2 MOSFETS. The output of this differential pair is taken from the output node which incorporates folded cascode current mirrors as source and sink. M4, M5, M6, and M7 form a current source while, on the other hand, M8, M9, M10, and M11 forms a current sink [26]. The sensing circuit comprises Ms1 and Ms2, which sense the common mode signal from the output node. Next, this signal is compared with the reference voltage through a comparator circuit through M3 and M12.

Further, the correction signal is fed to the fully differential pair through M3 and, thus, it adjusts its operating current according to the correction signal and reduces the common mode gain. A gain booster block which includes MG1, MG2, MG3, and MG4 is also added along with this circuit. This block is responsible for the gain boosting.

The difference signal taken from the differential pair M1 and M2 is amplified further by the next stage, which comprises of eight MOS devices. R_A and R_B are the output resistances at output nodes vout(+) and vout(−), respectively. These output resistances are responsible for the high output gain of the op-amp comparator circuit as the gain of any amplifier is estimated by the product of its transconductance and output resistance. M8, M9, M10, and M11 MOS devices are arranged and biased in such a manner as to provide high resistance to the output nodes.

In the final segment of the operational amplifier comparator, the gain booster block interacts with the M8 and M9 MOS devices. The output from the drain terminal of M8 and M9 NMOS devices is fed into the gate terminal of MG4 and MG3 MOSFET devices, respectively, which are working in a common source amplifier configuration. The MOS devices MG2 and MG1 are biased with a voltage vb3 and connected to the drain terminal of MG4 and MG3 devices to increase the resistance at the output terminal. Thus, the output of the op-amp comparator gets enhanced by the gain of the gain booster block and is again fed back to the gate terminal of M8 and M9 devices and, thus, the overall output gain of operational amplifier comparator gets boosted.

Major differences in this modified schematic with respect to the general CMFD topology [23,24,25] are the less complicated structure by utilizing fewer MOS devices, which ultimately reduces power consumption of this modified structure. For gain boosting this structure employs only one gain boosting block in the pull-down section. As there are fewer MOS devices in the pull-up section, it results in the fast charging of the output node, which eventually leads to a high slew rate.

Mathematical Analysis

Gain for the differential pair is given as:

$$Gain=Effective g_m·Effective R_{out}$$

(1)

where, g_m is the effective trans-conductance and R_out is the effective output resistance [1,13]. Looking at the output node V_out the resistance R_B can be calculated as given in Equation (1):

$$R_{B }=\frac{\left(rd{s}_7+g_{m9}·rd{s}_9·rd{s}_{11}\right)}{g_{m7 } rd{s}_7}$$

$$R_{B }=\frac{\left(r{o}_7+g_{m9}·r{o}_9·r{o}_{11}\right)}{g_{m7 } r{o}_7}$$

(2)

Additionally, the current I₇ that flows through this output node can be calculated as:

$$I_7=\left\{\frac{g_{m2}\left(r{o}_2\Vert r{o}_5\right)}{2 \left[\left(\frac{g_{m9} . r{o}_9 . r{o}_{11}}{g_{m7 }r{o}_7}\right)+\left(r{o}_2\Vert r{o}_5\right)\right]}\right\}.V_{in}(-)$$

$$I_7=\left\{\frac{g_{m2} . V_{in}(-)}{2 \left\{1+\left[\left(\frac{g_{m9} . r{o}_9 . r{o}_{11}}{g_{m7} r{o}_7}\right). \left(gd{s}_2+gd{s}_5\right)\right]\right\}}\right\}$$

(3)

From Equations (1) and (3) the output voltage gain comes out to be:

$$\frac{V_{out}}{V_{in}}=\left\{\frac{g_{m1}}{2}+\left\{\frac{g_{m2} . V_{in}(-)}{2 \left\{1+\left[\left(\frac{g_{m9} . r{o}_9 . r{o}_{11}}{g_{m7} r{o}_7}\right). \left(gd{s}_2+gd{s}_5\right)\right]\right\}}\right\}\right\} . R_{out}$$

(4)

where R_out is given as:

$$R_{out}=\left[g_{m9} . r{o}_9 . r{o}_{11}\right] \Vert \left[g_{m7} r{o}_7\left(r{o}_2\Vert r{o}_5\right)\right]$$

Rearranging and solving the Equation (4) by assuming trans-conductance and output resistance of all mirrors as g_m and ro:

$$\frac{V_{out}}{V_{in}}=\left\{\frac{g_{m1}^2 . r{o}^2}{4}\right\}$$

(5)

Now, solving for the gain boosting circuit, R_out can be calculated as:

$$R_{out}=\left[A. g_{m9} . r{o}_9 . r{o}_{11}\right] \Vert \left[ g_{m7} r{o}_7\left(r{o}_2\Vert r{o}_5\right)\right]$$

Again, solving for gain:

$$\frac{V_{out}}{V_{in}}=\left\{\frac{A . g_{m1}^2 . r{o}^2}{4}\right\}$$

(6)

Comparing Equations (5) and (6) it can be easily concluded that with the modified architecture the gain improves in comparison to the general common feedback structure [23,24,25].

3. Results

In this segment, all the required simulations, such as transient, AC analysis, along with parameter variations of the modified circuit using a closed loop configuration is demonstrated. Monte Carlo simulations have been performed by using SPICE in 90 nm CMOS technology. At least 20 iterations are performed by utilizing the Monte Carlo simulation methods for concluding the final results.

An op-amp with a feedback circuit is designed to have a gain of 20. The design schematic blocks of that are shown in Figure 3 [15,27].

Figure 4 represents the modified circuit of the op-amp comparator employing common mode current feedback with folded cascoded current mirrors along with gain-boosting circuit. The channel length of 90 nm and the channel width of 1 µm is used as the dimension of MOS devices in the proposed op-amp comparator modified architecture.

Table 1. Power consumption, current drawn, and rise and fall times of the modified GB-CMFD.

Supply Voltage = 0.7 V			Temp = 25 °C
Width (µm)	Power Consumption (µW)	Current Drawn (µA)	Rise Time (ps)	Fall Time (ps)
1.0	362	517	7	7
1.5	390	558	7	7
2.0	416	595	7	7
2.5	436	623	7	7
3.0	454	649	7	7
3.5	472	674	7	7
4.0	489	699	7	7
4.5	506	724	7	7
5.0	524	748	7	7

shows the power consumption, maximum current drawn, and the rise time and fall time of the modified op-amp (GB-CMFD) comparator. Simulation is done on a supply voltage of 0.7 V at 25 °C.

Variations in the parameters when the channel width is varied from 1 µm to 5 µm are also included in Table 1. This circuit draws a maximum current of 517 µA by consuming the power of 362 µW at 1 µm channel width. The values of power consumption and current drawn are increased by 44% when the channel width is increased to 5 µm. Figure 5a,b shows these variations graphically.

Table 1 also gives the details regarding the rising and falling duration for the output pulse and its variation with channel width. Rise and fall times of 7 ps are observed for both rising and falling edges. The variations in these values are negligible with the variation in channel width.

Figure 6 gives details regarding the output waveforms that are recorded with respect to the input waves for the modified structure (CMFD-GB). The input voltage at the negative terminal is kept constant at 350 millivolts and then a varying voltage is applied at the positive terminal. The output waveform at the non-inverting terminal, which is recorded, is shown in Figure 6.

Table 2. Power consumption, gain error, slew rate, and closed and open loop gain of the modified GB-CMFD at different temperatures.

Temp (°C)	Power Consumption (µW)	Observed Closed Loop Gain (dB)	Open Loop Gain	Gain Error %	Slew Rate (Rise Time) (V/µs)	Slew Rate (Fall Time) (V/µs)
−5	365	13	953	0.69	839	839
0	364	13	953	0.69	839	839
5	364	13	953	0.69	839	839
15	363	13	1075	0.61	839	839
25	362	13	1075	0.61	839	839
35	361	13	1229	0.53	839	839
45	361	13	1229	0.53	839	839
55	362	13	1229	0.53	839	839

shows power consumption, observed closed loop gain, open loop gain, gain error, and slew rate of the modified GB-CMFD comparator. Simulation is done at a supply voltage of 0.7 V by varying the temperature from −5 °C to 55 °C.

In Table 2 the variations in the power consumption are detailed. The modified circuit consumes 362 µW at 25 °C. This value increases marginally but remains close to 362 µW when the temperature is raised to 55 °C. On the other hand, when the temperature was reduced to −5 °C the power consumption increased further and attained the value of 365 µW at −5 °C. Figure 7a shows the variations of power consumption with temperature.

Figure 7b,c exhibit the observed closed loop gain and open loop gain variations with temperature. An observed closed loop gain of 12.93 decibels at 25 °C is recorded, which is very close to the designed closed loop gain of 13.01 decibels. Diminutive level variations are recorded when the temperature varied from −5 to 55 °C. Open loop gain is then detailed with its variations with temperature. The open loop gain of 1075 is observed for the GB-CMFD structure at 25 °C, which is quite large as compared to standard comparator structures. The open loop gain of 1075 is recorded for the modified architecture at 25 °C, which increases to 1229 when the temperature is raised to 55 °C. However, the open loop gain reduced to 953 when the temperature is reduced to −5 °C. Overall, the percentage variations of the open loop gain are 11% to 14% with the variations in temperature.

The gain error variations with temperature are shown in Table 2. Though the circuit is designed in a closed loop configuration for the power gain of 20, which equals 13.01 dB, the values that are obtained from the magnitude plot are marginally different at different temperatures. The gain error is almost constant for the temperature range of −5 to 25 °C and has an error of 0.1% from the expected value, which is relatively acceptable. Figure 7d shows the variations of gain error with temperature.

Figure 8 represents the frequency response of the closed loop CMFD-GB structure. The variations in the closed loop gain with respect to temperature can be easily observed from this response.

In the end Table 2 gives the details regarding the slew rate of the modified gain boosting CMFD comparator and its variations with temperature. Slew rate is the measure of the rate at which the output voltage rises with respect to time [28]. Thus, if a comparator has a high slew rate, it will lead to the high speed of comparison [29].

$$SLEWRATE=\frac{VOLTAGELEVEL\left(V\right)}{RISETIME \left(\mathsf{\mu }\mathrm{s}\right)orFALLTIME \left(\mathsf{\mu }\mathrm{s}\right)}$$

Thus, from the above relation, if a circuit has a very small value of rising time and fall time then it will eventually have a very high slew rate.

From Table 1 the rise time and fall time for this modified GB-CMFD circuit are seven picoseconds and the maximum minus minimum voltage range that is observed after the simulation is 0.006 V for both the rising and falling edge. Thus, using these values, a slew rate of 839 V/µs is obtained for the circuit, which is quite a high value as compared to the other comparators. Figure 9a,b shows the variations of the slew rate for charging and discharging edge with temperature.

It can be seen that this variation is very minute and, thus, this circuit has a high slew rate which is almost stable with temperature variations.

Table 3. Comparison of results at 25 °C.

Temperature	25 °C
Technology	CMOS
No. Of Mosfets	24
Channel Length	90 nm
Channel Width	1 µm
Supply voltage	0.7 V
Power consumption	362 µW
Current drawn	517 µA
Observed closed loop gain	13 decibels
Gain error %	0.6
Open loop gain	1075
Slew rate	839 V/µs

summarizes the performance of the modified gain boosting CMFD comparator. CMOS technology is used to design this circuit with the channel length of 90 nm and channel width of 1 µm. A supply voltage of 0.7 V is deployed for the simulations. Twenty-four MOS transistors are used for designing the circuit, along with four capacitors and two resistors. The value of power consumption at 25 °C is 362 µW while drawing a current of 517 µA, both having a variation of approximately 2%. A total of 12.93 decibels of closed loop gain is observed at 25 °C, which is quite close to the calculated gain of 13.01 decibels.

The open loop gain of 1075 is attained by this structure at 25 °C, which is large, compared to normal comparator structures. A gain error of 0.6% is obtained after simulation of this circuit at 25 °C, which is relatively acceptable. A very high slew rate is achieved by this modified design that is 839 V/µs that will eventually lead to a very high speed of comparison and, thus, this comparator can be utilized in designing high-speed analog circuits, such as ADCs and DACs [30,31,32].

Table 4. Percentage variation with temperature.

Temperature	−5 °C to +55 °C
Power consumption	≅0%
Observed closed loop gain	≅0%
Open loop gain	12% to 14%
Gain error	12% to 0.07%
Slew rate	≅0%

summarizes the percentage variation of these parameters with temperature. Power consumption varies substantially with the decrease in temperature. A total of 0.07% of marginal variations are recorded for observed closed loop gain, which almost equals zero and is acceptable. Open loop gain variations are then shown in the table, which varies from 12% at −5 °C and 14% at 55 °C. Significant variations in the gain error are recorded when the temperature scales down to −5 °C on the other hand, when the temperature increased to 55 °C the variations are minimal. Almost null variations are observed for the slew rate.

4. Comparison

To evaluate the proposed modified architecture of the op-amp comparator (GB-CMFD) three more structures of the op-amp comparator are utilized for analyses and comparison. These three structures are DCFIA, SCFIA [19], and CMFD [23,24]. The structural design of these three architectures are depicted in Appendix A (Figure A1, Figure A2 and Figure A3). DCFIA and SCFIA are the amplifiers which employ common mode current feedback from drain and source terminals [10]. CMFD is a common mode current feedback with conventional cascode amplifier [23,24].

These three structures are again simulated in 90 nm CMOS technology. Results that are obtained after Monte Carlo simulation are shown in

Table 5. Comparison of simulations results at 25 °C.

	DCFIA [19]	SCFIA [19]	CMFD [23,24]	GB-CMFD (Proposed Modified Architecture)
Technology	CMOS	CMOS	CMOS	CMOS
No. Of Mosfets	19	21	20	24
Channel Length	90 nm	90 nm	90 nm	90 nm
Channel Width	1 µm	1 µm	1 µm	1 µm
Supply voltage	0.8 V	0.8 V	1.8 V	0.7 V
Power consumption	10 µW	119 µW	1179 µW	362 µW
Observed closed loop gain(dB)	13.2	13.5	13.1	13
Gain error %	1	3	0.8	0.6
Open loop gain	467	177	801	1075
Slew rate	1 V/µs	1 V/µs	307 V/µs	839 V/µs

.

Figure 10 shows the variations in the power consumptions for all four comparators structures when the temperature is varied from −5 to +55 °C. The proposed modified architecture, despite using 24 MOS transistors, consumes power at a moderate level, which is approximately in the range of 360 µW. It also shows marginal variations with temperature variations.

Figure 11 shows the comparison of the gain error value for all four structures. It can be observed from the curves that GB-CMFD has the least value of the percentage gain error. Maximum variations in the gain error is shown by DCFIA and CMFD structures which increased substantially when temperature varies from −5 to +55 °C. SCFIA show the least variation with temperature but has more gain error value than GB-CMFD.

Figure 12 illustrates the variations of observed closed loop gain for all four comparator structures. All four structures are employed in the circuit shown in Figure 3, which is designed for a closed loop gain of 13.01 decibel. The values of actual closed-loop gain that are observed at different temperatures in the simulations are then plotted in Figure 12. The magnitude of the observed closed loop gain for GB-CMFD is almost constant and very close to the designed closed loop value. The magnitude of observed closed loop gain for DCFIA decreases with the increase in temperature opposite to that of the observed CMFD closed loop gain value, which increases with the increase in temperature. The observed SCFIA closed loop gain values are small as compared to DCFIA and CMFD, but substantially large as compared to GB-CMFD.

Figure 13 depicts the variations in open loop gain with temperature. The GB-CMFD structure again shows the maximum magnitude of the open loop gain at different temperatures in comparison to other structures.

Table 6. Percentage variations in parameters when the temperature changes from −5 to 55 °C.

Parameters	DCFIA [19]	SCFIA [19]	CMFD [23,24]	GB-CMFD (Proposed Modified Architecture)
Power consumption	23 to 16	4 to 5	≅3	≅0
Observed closed loop gain	15 to 12	3 to 2	16 to 15	≅0
Open loop gain	88 to 89	212 to 30	96 to 94	11 to 14
Gain error	16 to 11	1 to 6	15 to 16	12 to 0.07
Slew rate (charging)	≅0	≅0	1 to 6	≅0
Slew rate (discharging)	≅1	≅1	29 to 27	≅0

summarizes these parametric variations of all four structures at different temperatures. The modified op-amp comparator (GB-CMFD) shows the least variation in comparison to others in all six parameters which are taken into consideration for comparison.

Table 7. Comparison with other associated studies.

	Technology CMOS	Supply Voltage	Slew Rate	Channel Length	Power Consumption
[29]	350 nm	2.5 V	161 V/µs	350 nm	456 µW
	350 nm	2.5 V	176 V/µs	350 nm	195 µW
[32]	130 nm	1.0 V		130 nm	100 µW
[33]	180 nm	1.1 V	--	180 nm	1300 µW
[34]	180 nm	--	--	180 nm	≅750 µW
[35]	65 nm	1.2 V	--	65 nm	2800 µW
[36]	65 nm	1.2 V		65 nm	370 µW
[37]	180 nm	0.7 V to 1.1 V		180 nm	420 µW
GB-CMFD (Proposed-architecture)	90 nm	0.7 V	839 V/µs	90 nm	362 µW

gives details regarding the comparison on the basis of power consumption of this comparator with other pertinent associated studies.

5. Conclusions

A modified architecture of an op-amp comparator to achieve a high slew rate and boosted gain with an improvement in gain design error is proposed and investigated in this manuscript. Deploying the gain booster block and common-mode current feedback structure, the modified architecture of the op-amp comparator (CMFD-GB) achieves an improvement in the overall gain and slew rate with the reduction in gain error and power consumption. An overall gain of 1075 is attained by implementing an additional gain booster block at the end segment of the op-amp comparator that is approximately a 34% improvement as compared to the general common-mode current feedback structure. The rise and fall time also get reduced due to this boosted gain which, in turn, leads to the very high slew rate for this modified op-amp comparator structure. A slew rate of 839 V/µs is observed for this modified op-amp comparator structure, which is quite high and which makes this comparator a prominent contender for high-speed data converters circuits. Closed loop analysis of the modified op-amp comparator structure is done by utilizing this structure for designing a closed feedback amplifier with a gain of 13.01 dB. Results from the simulations depict that the observed and design gain is almost equal for the CMFD-GB comparator with the value of 12.93 decibels. Comparing it to the general CMFD structure, this is an approximately 27% reduction. Considerable reduction in power consumption is also attained through this modified op-amp comparator structure. In spite of using more MOS devices, the power consumption observed for this modified architecture is 362.29 µW, which almost equals a 70% reduction as compared to general CMFD structure. The modified architecture of the op-amp comparator along with high slew rate also shows symmetry for charging and discharging output edges which makes it perfect for the designing of accurate and linear data converter circuits. Temperature sensitivity of these parameters is also observed for the modified comparator architecture by simulating this circuit at different temperatures. The results show an optimum variation of these critical parameters with varying temperature for the modified op-amp comparator architecture (CMFD-GB) as compared to three other architectures. Boosted gain and a large slew rate with optimum power consumption of this modified op-amp comparator structure (CMFD-GB) increases its applicability in high-speed analog and digital circuits, which are designed in ultra deep submicron technologies where high-speed and low-power consumption are the essential design constraints.