Analytical Performance of the Threshold Voltage and Subthreshold Swing of CSDG MOSFET

Abstract

In this research work, the threshold voltage and subthreshold swing of cylindrical surrounding double-gate (CSDG) MOSFET have been analyzed. These analyses are based on the analytical solution of 2D Poisson equation using evanescent-mode analysis (EMA). This EMA provides the better approach in solving the 2D Poisson equation by considering the oxide and Silicon regions as a two-dimensional problem, to produce physically consistent results with device simulation for better device performance. Unlike other models such as polynomial exponential and parabolic potential approximation (PPA) which consider the oxide and silicon as one-dimensional problem. Using the EMA, the 2D Poisson equation is decoupled into 1D Poisson equation which represent the long channel potential and 2D Laplace equation describing the impacts of short channel effects (SCEs) in the channel potential. Furthermore, the derived channel potential close-form expression is extended to determine the threshold voltage and subthreshold behavior of the proposed CSDG MOSFET device. This model has been evaluated with various device parameters such as radii Silicon film thickness, gate oxide thickness, and the channel length to analyze the behavior of the short channel effects in the proposed CSDG MOSFET. The accuracy of the derived expressions have been validated with the mathematical and numerical simulation.

1. Introduction

The downscale of the conventional MOSFETs devices to nanoscale regime has been the driving force of the semiconductor industry [1,2,3]. The main objective behind the transistor scaling is to enhance device performance, speed, low operating power, and packing density of the IC [4,5]. However, the downscaling of the device has led to problems of short channel effects (SCEs), such as threshold voltage roll-off, degradation of the subthreshold threshold swing, and subthreshold leakage current [6,7,8,9]. To overcome this problem several device structures has been proposed. Double gate structures [10,11,12] introduce the concept of volume inversion leading to higher current, better scalability, and increased conductance than conventional MOSFETs, but its use is limited based on the cost of production and process complexity.

In order to overcome these shortcomings of cost of production and process complexity, several novel geometric structures have been proposed. One of such structures is a three-dimensional cylindrical surrounding-gate (CSG) MOSFET [13,14,15,16,17]. The surrounding gate on the silicon pillar provides better coupling and its fabrication is less complex compared to DG MOSFET [18]. Additionally, CSG MOSFETs poses a better immunity to SCEs than conventional single gate MOSFETs and DG MOSFETs [19,20]. The most enhancing feature of the CSG MOSFET when compared to other novel structures, like single gate, pi gate, and double gate, is its geometric structure. This device structure increases the packing density, and most importantly leads to better controllability of the gate over the channel [17,21]. The gate control results to enhancement of the subthreshold characteristics and greater immunity to SCEs. However, in terms of current drive the CSG MOSFETs have lesser current compared with the DG MOSFET, hence, its extensive use is limited for high performance application [22]. Thus, there is need to improve on the geometric structure of the CSG MOSFET to enhance the current drive, the gate control over the channel and further improve the SCEs immunity at the nanoscale regime.

A novel structure, the cylindrical surrounding double gate (CSDG) MOSFET, was proposed by Srivastava et al. [12]. The geometry is similar to that of the CSG MOSFET with an internal core gate. The core gate enhances the channel control and improves the SCEs immunity. Additionally, the device allows for higher packing density and higher volume inversion than DG MOSFETs and CSG MOSFETs [23,24]. The explicit charge model based on the unified charge model was carried out by Srivastava et al. [25,26]. The authors analyzed the channel current for the novel structure to be higher than the single, DG MOSFET, and CSG MOSFET. However, the authors did not consider the subthreshold regime. Verma et al. [27] worked on the subthreshold regime of the CSDG MOSFET in which only the threshold voltage was analyzed.

The proposed CSDG MOSFET is designed on a hollow concentric cylindrical structure in which a simple analytical channel potential model has been derived at subthreshold regime. The 2D Poisson equation is solved with the EMA as a boundary valued problem to obtain the minimum surface potential. The minimum surface potential is further extended in the derivation of the threshold voltage model, subthreshold current, and subthreshold swing of the device structure. Its performance is investigated with the device parameters. However, we neglected the quantum mechanical effect by assuming a minimum silicon body thickness of 5 nm [28]. This paper is organized as follows: The structure of CSDG MOSFET with the boundary conditions and modelling of the minimum surface potential with EMA is presented in Section 2. The threshold voltage model for the proposed CSDG MOSFET structure is derived using the minimum surface potential in Section 3. The subthreshold swing is derived in the Section 4. The results have been discussed in the Section 5. Finally, Section 6 concludes the work and recommends future aspects.

2. Structure of CSDG MOSFET and Potential Distribution Model using EMA Model

2.1. CSDG MOSFET Structure

The CSDG MOSFET is an extended version of DG MOSFET and CSG MOSFET in terms of form factor and current drive, respectively. The DG MOSFET has two gates (blue color), the oxides (yellow color), the drain/source (red color) and a silicon substrate (P, green color). When this DG MOSFET is rotated with respect to the reference point, the first gate (G₁) forms the internal radius (r = a) with a circular thin oxide to immune the effect of SCEs. The second gate (G₂) forms the external radius (r = b) with circular thin oxide, forming a hollow concentric cylinder [29]. Between the oxides is the silicon substrate, while the extension forms the source and drain part of the cylinder as shown in the Figure 1.

The internal and external gates of the CSDG MOSFET can be biased either separately or simultaneously to form separate inversion or volume inversion, respectively. However, the simultaneous biasing of the CSDG MOSFET is usually preferred due to higher current drive (volume inversion). Assuming the gate of an n-channel CSDG MOSFET are positively biased simultaneous. Below threshold voltage, the minority carrier electrons are attracted towards the oxide-silicon interface forming weak inversion. As the biasing voltage exceeds the threshold voltage, the onset of strong inversion occurs in CSDG MOSFET in similar manner with traditional MOSFET [30]. Both biasing gates voltage forms the internal and external channel of the device structure at subthreshold region. However, above threshold voltage the two channels contribute to higher current drive know as volume inversion.

2.2. Potential Model Derivation with EMA Model

2.2.1. Evanescent Mode Analysis (EMA) Model

The evanescent mode analysis is a mathematical model for solving the 2D Poisson equation as a function of transverse confinement of the device structure with respect to its boundary condition [20].

The 2D Poisson solution yields the electrostatic potential distribution confinement of the CSDG MOSFET as shown in the flowchart of Figure 2. The SCEs on the CSDG MOSFETs are governed analytically by the electrostatic potential caused by biasing the inner and outer gate simultaneously. The derived potentials are extended in modelling the threshold voltage and subthreshold swing. Since, the threshold voltage roll-off are consequences of electrostatic charge sharing effect, it is typically considered as one major indicator of SCEs [31]. Another indicator of SCEs is the subthreshold swing degradation which results to higher off-state current.

2.2.2. 2D Poisson Equation

In the subthreshold (weak inversion) regime, the 2D channel potential region, ψ (r, z) is determined from cylindrical Poisson’s equation in the cylindrical coordinate system. Assuming uniform channel doping and the independency of the channel potential on the angle θ as highlighted by [14], the 2D Poisson equation (in cylindrical coordinate) is expressed as [32]:

$$\frac{d^2\psi (r,z)}{d{r}^2}+\frac{1}{r}\frac{d^2\psi (r,z)}{d{r}^2}+\frac{d^2\psi (r,z)}{d{z}^2}=\frac{q{N}_A}{{\epsilon }_{si}}$$

(1)

where ψ(r, z), N_A, q, and ε_si, are the electrostatic potential distribution in the radii silicon film, doping concentration in radii silicon film, electric charge, and dielectric permittivity of the silicon, respectively.

The electrostatic potential, ψ(r, z) can be modeled by decoupling the 2D Poisson equation into two-part as shown in Figure 2: (i) 1D in the silicon region through the oxide thickness, and (ii) 2D based on the source and drain impact on the channel using method of separation of variables [33], that is:

$$\psi (r,z)={\psi }_{1D}(r)+{\psi }_{2D}(r,z)$$

(2)

where ψ_1D (r) is the channel potential approximation which satisfies 1D Poisson’s equation under depletion approximation, along the silicon thickness and it is given as [34]:

$$\frac{d^2{\psi }_{1D}(r)}{d{r}^2}+\frac{1}{r}\frac{d{\psi }_{1D}(r)}{dr}=\frac{q{N}_A}{{\epsilon }_{si}}$$

(3a)

Additionally, ψ_2D (r, z) accommodates the 2D variation of the channel potential at the oxide-silicon interface with zero charges which satisfies the 2D Laplace equation [35]. The Laplace equation describes the impact of the source and drain on the channel potential. It is given as:

$$\frac{d^2{\psi }_{2D}(r,z)}{d{r}^2}+\frac{1}{r}\frac{d^2{\psi }_{2D}(r,z)}{d{r}^2}+\frac{d^2{\psi }_{2D}(r,z)}{d{z}^2}=0$$

(3b)

2.2.3. Boundary Condition for the CSDG MOSFET

The boundary conditions for the silicon body and gate oxide are used to solve the decoupled Poisson given Equations (3) and (4) with respect the structures in Figure 3 and Figure 4.

Based on Gauss’ Law [36], zero electric field must exist within the center of the silicon subtract region indicated by the circular dash line known as the Gaussian surface in Figure 4a and Figure 5a. The CSDG MOSFET is an advanced version of double-gate MOSFET as shown in Figure 1 and Figure 3. It can also be treated as CSG MOSFET since the total electric field beyond E = 0 does not have effect on the enclosed surface within the circular dash line and likewise the electric field at the hollow center is zero assuming no charge exist in the center [37]. Hence, the internal and the external radius of CSDG MOSFET can be treated separately as two CSG MOSFET as shown in Figure 4.

In order to obtain the boundary condition for the CSDG MOSFET, Figure 3 and Figure 4 are considered as follows:

(I) The potential at the gate surface for internal and external gates respectively are obtained as:

$$\begin{array}{l}\psi (r=a,z)={\psi }_a(a)\\ \psi (r=b,z)={\psi }_b(b)\end{array}\}$$

(4)

Potential at the center of silicon for the internal and external gates respectively with respect to the hollow structure:

$$\begin{array}{l}\psi (r=0,z)={\psi (r=b,z)|}_{r=b}{\psi }_{1D}(0)\\ \psi (r=0,z)={\psi (r=a,z)|}_{r=a}{\psi }_{1D}(0)\end{array}\}$$

(5)

(II)

The electric field at the channel center for internal and external potential, respectively:

$$\begin{array}{l}{\frac{d\psi (r,z)}{dr}|}_{r=0}={\frac{d\psi (r,z)}{dr}|}_{r=b}=0\\ {\frac{d\psi (r,z)}{dr}|}_{r=0}={\frac{d\psi (r,z)}{dr}|}_{r=a}=0\end{array}\}$$

(6)

(III)

The electric field at the silicon-oxide interface for internal and external potential, respectively:

$$\begin{array}{l}{C}_{ox1}(V_{gs}-V_{FB}-{\psi }_{1D}(a,z))={\epsilon }_{si}\frac{d\psi (r,z)}{dr}{|}_{r=a}\\ C_{ox1}(V_{gs}-V_{FB}-{\psi }_{1D}(b,z))={\epsilon }_{si}\frac{d\psi (r,z)}{dr}{|}_{r=b}\end{array}\}$$

(7)

(IV)

The internal electrostatic field boundary condition based on 1D Poisson equation:

$$\begin{array}{l}{C}_{ox1}(V_{gs}-V_{FB}-{\psi }_{1D}(a))={\epsilon }_{si}\frac{d{\psi }_{1D}(r)}{dr}{|}_{r=a}\\ C_{ox1}(V_{gs}-V_{FB}-{\psi }_{1D}(b))={\epsilon }_{si}\frac{d{\psi }_{1D}(r)}{dr}{|}_{r=0}={\epsilon }_{si}\frac{d{\psi }_{1D}(r)}{dr}{|}_{r=b}=0\end{array}\}$$

(8)

where:

$$C_{ox1}=\frac{{\epsilon }_{ox}}{\left[aIn\left(1+\frac{t_{ox}}{a}\right)\right]}$$

(9)

(V)

The external electrostatic field boundary condition based on 1D Poisson equation:

$$\begin{array}{l}{C}_{ox2}(V_{gs}-V_{FB}-{\psi }_{1D}(b))=-{\epsilon }_{si}\frac{d{\psi }_{1D}(r)}{dr}{|}_{r=b}\\ C_{ox2}(V_{gs}-V_{FB}-{\psi }_{1D}(a))=-{\epsilon }_{si}\frac{d{\psi }_{1D}(r)}{dr}{|}_{r=0}={\epsilon }_{si}\frac{d{\psi }_{1D}(r)}{dr}{|}_{r=a}=0\end{array}\}$$

(10)

where:

$$C_{ox2}=\frac{{\epsilon }_{ox}}{\left[bIn\left(1+\frac{t_{ox}}{b}\right)\right]}$$

(11)

(VI)

The boundary condition along the Z-direction can be used to solve the 2D Laplace equation at the source and drain end. Therefore, the Potential at the source end where (Z = 0) is given as:

$$\psi (r,0)=V_{bi}$$

(12a)

Potential at the drain end (Z = L) is given as:

$$\psi (r,L)=V_{bi}+V_{DS}$$

(12b)

$$\begin{array}{l}{C}_{ox1}(V_{GS}-V_{FB}-{\psi }_{1D}(0))={\epsilon }_{si}\frac{d\psi (r,z)}{dr}{|}_{r=0}\\ {\psi }_{1D}(0)=\frac{\left({\psi }_{1D}(a)+{\psi }_{1D}(b)\right)}{2}\end{array}\}$$

(13)

By substituting Equation (13) into Equation (2), we obtained:

$$\begin{array}{l}\psi (r,0)={\psi }_{1D}(r)+{\psi }_{2D}(r,0)=V_{bi}\\ \Rightarrow {\psi }_{2D}(r,0)=V_{bi}-{\psi }_{1D}(r)\\ \Rightarrow {\psi }_{2D}(r,L)=V_{bi}+V_{DS}-{\psi }_{1D}(r)\end{array}\}$$

(14)

where V_bi, V_FB, V_GS, and V_DS, are the built-in voltage, flat band voltage, gate to source voltage, and drain voltage, respectively. C_ox1 and C_ox2 are internal gate and external gate oxide capacitance, respectively, and ε_si and ε_ox are dielectric permittivity of silicon and the dielectric permittivity of the oxide. Additionally, r varies to a when considering the internal potential and to b when considering the external potential in Equations (9) and (11), respectively.

Using the boundary conditions Equations (4)–(14), the surface potential for the internal and external gate of the proposed CSDG structure is (Appendix A contains the detailed procedure):

$$\begin{array}{cc}\hfill {\psi }_S(z)=(V_{GS}-V_{FB})-{\psi }_{1D}(0)+\frac{q{N}_A{a}^2}{4{\epsilon }_{si}}-& \frac{q{N}_A{t^2}_{si}}{16{\epsilon }_{si}}-\frac{q{N}_A{t_{si}}^2{C}_{si}}{4{\epsilon }_{si}{C}_{ox-a}}\hfill \\ & +\left(A_0{e}^{(z{\lambda }_0)}+B_0{e}^{(-z{\lambda }_0)}\right)J_0(a{\lambda }_0)\hfill \end{array}$$

(15)

$$\begin{array}{cc}\hfill {\psi }_S(z)=(V_{GS}-V_{FB})-{\psi }_{1D}(0)+& \frac{q{N}_A{b}^2}{4{\epsilon }_{si}}-\frac{q{N}_A{t^2}_{si}}{16{\epsilon }_{si}}-\frac{q{N}_A{t_{si}}^2{C}_{si}}{4{\epsilon }_{si}{C}_{ox-a}}\hfill \\ & +\left(A_0{e}^{(z{\lambda }_0)}+B_0{e}^{(-z{\lambda }_0)}\right)J_0(b{\lambda }_{01})\hfill \end{array}$$

(16)

The surface potential obtained in Equations (15) and (16) is extended in the modelling of the threshold voltage and subthreshold swing of the proposed CSDG MOSFET which predicts the device characteristics and performance.

3. Threshold Voltage Model for the Proposed CSDG

The CSDG MOSFET as a switch requires an external source to be able to determine the On-OFF nature of the device. Since MOSFET are voltage-controlled device, a DC voltage is required to control the CSDG MOSFET. This DC voltage required for the ON—switching of the device when a reasonable drain current is achieved is known as the threshold voltage.

Threshold voltage can also be defined as the gate voltage at which the minimum surface potential is twice the Fermi potential, 2ϕ_f [38]. Hence, Equations (2), (15), and (16) is simplified further by setting its first derivative at z = 0 along the z-axis to obtain the minimum surface potential position (z_min) which equates the Fermi potential level of the device structure. After mathematical transformation, the minimum surface potential in terms of z_min is given as:

$${\psi }_{s_{\min }}(z_{\min })={\psi }_{1D}(r)+2J_0({\lambda }_{0}r)\sqrt{A_m{B}_m}=2{\varphi }_f$$

(17)

where:

$${\varphi }_f=\frac{KT}{q}In\left(\frac{N_A}{n_i}\right)$$

where n_i is the intrinsic carrier concentration, r = a for internal cylinder and r = b for external cylinder, and m = 0 and m = 1 for the internal and external coefficient. K, T, q, N_A, and n_i are the Boltzmann’s constant, Temperature (K), electronic charge, and doping concentration, respectively.

The threshold voltage for the proposed CSDG structure is given as:

$$V_{T{H_S}_i\_CSDG}=V_{T{H}_L\_CSDG}-V_{T{H}_i\_CSDG}$$

(18)

where V_{THL_CSDG} are the threshold voltage for the long channel assuming the drain and source has no the effect on the channel, V_{THi_CSDG} are the threshold voltage roll-off due to drain and source effects with respect to internal or external gate, and V_{THsi_CSDG} is the short channel threshold voltage for the internal and external gate surface potential.

Considering the Long channel condition and assuming gradual channel approximation [39], the threshold voltage for the internal and external gates are given based on Equation (17) as:

$$\begin{array}{cc}\hfill {\psi }_{1D}(r)=& {2{\varphi }_f|}_{V_{GS}=V_{TH\_L}}\Rightarrow \hfill \\ & V_{TH\_L}=2{\varphi }_f+V_{FB}+{\psi }_{1D}(0)-\frac{q{N}_A{a}^2}{4{\epsilon }_{si}}+\frac{q{N}_A{t}^2{}_{si}}{16{\epsilon }_{si}}+\frac{q{N}_A{t}_{si}{}^2{C}_{si}}{4{\epsilon }_{si}{C}_{ox1}}\hfill \end{array}$$

(19)

$$V_{TH\_L}=2{\varphi }_f+V_{FB}+{\psi }_{1D}(0)-\frac{q{N}_A{b}^2}{4{\epsilon }_{si}}+\frac{q{N}_A{t^2}_{si}}{16{\epsilon }_{si}}+\frac{q{N}_A{t_{si}}^2{C}_{si}}{4{\epsilon }_{si}{C}_{ox2}}$$

(20)

Considering the short channel condition, we included the drain and source effect in the model based on Equation (17) as given:

$${\psi }_{1D}(r)+2J_0({\lambda }_{01}r)\sqrt{A_0{B}_0}=2{\varphi }_f$$

(21)

(a) Considering the internal gate (r = a) for the short channel model:

$$\begin{array}{l}{{\psi }_S(r=a,z_{\min })|}_{V_{GS}={\psi }_{1D}(a)=V_{th}}={\psi }_{1D}(a)\\ +\left(A_0{e}^{(z_{\min }{\lambda }_0)}+B_0{e}^{(-z_{\min }{\lambda }_0)}\right)J_0(a{\lambda }_0)=2{\varphi }_f\end{array}$$

(22)

From Equation (17) we obtain:

$$V_{T{H}_{a\_CSDG}}+2J_0(a{\lambda }_0)\sqrt{A_0{B}_0}=2{\varphi }_f$$

(23)

This can be expressed in polynomial form of second order as given:

$$X_1{V}_{T{H}_{a\_CSDG}}^2+X_2{V}_{T{H}_{a\_CSDG}}+X_3$$

(24)

where:

$$\begin{array}{l}{X}_1=4a_1-a_2-2\\ X_2=(2V_{bi}+V_{DS})(2-4a_1)\\ X_3=\left[4a_1\left[\left(V_{bi}(V_{bi}+V_{DS})\right)\right]-{\left(V_{bi}+V_{DS}\right)}^2-4{\varphi }_f{}^2{a}_2-V_{DS}{}^2\right]\\ \begin{array}{l}{a}_1=2J^2(a{\lambda }_0)\sinh (L{\lambda }_0)\\ a_2=4J^2(a{\lambda }_0){\sinh }^2(L{\lambda }_0)\end{array}\}\end{array}\}$$

(25)

Therefore, the threshold voltage for the internal gate surface potential due to the short channel is given as:

$$V_{T{H}_a\_CSDG}=\frac{-X_2+\sqrt{{X_2}^2-4X_1{X}_3}}{2X_1}$$

(26)

Hence the closed-form expression of the threshold voltage roll-off for the internal gate of CSDG MOSFET is given with the practical assumption of λ_nL >> 1 [40]:

$$V_{T{H}_{Sa}\_CSDG}=\left(2{\varphi }_f+V_{FB}+{\psi }_{1D}(0)-\frac{q{N}_A{a}^2}{4{\epsilon }_{si}}+\frac{q{N}_A{t}^2{}_{si}}{16{\epsilon }_{si}}+\frac{q{N}_A{t}_{si}{}^2{C}_{si}}{4{\epsilon }_{si}{C}_{ox-a}}\right)-\left(\frac{-X_2+\sqrt{X_2{}^2-4X_1{X}_3}}{2X_1}\right)$$

(27)

(b) Considering the External gate (r = b) for the short channel model:

$$V_{T{H}_{b\_CSDG}}+2J_0(b{\lambda }_0)\sqrt{A_0{B}_0}=2{\varphi }_f$$

(28)

Similarly, this can be expressed as a quadratic equation as given:

$$Y_1{V}_{T{H}_{b\_CSDG}}^2+Y_2{V}_{T{H}_{T{H}_{b\_CSDG}}}+Y_3$$

(29)

where:

$$\begin{array}{l}{X}_1=4a_1-a_2-2\\ X_2=(2V_{bi}+V_{DS})(2-4a_1)\\ X_3=\left[4a_1\left[\left(V_{bi}(V_{bi}+V_{DS})\right)\right]-{\left(V_{bi}+V_{DS}\right)}^2-4{\varphi }_f{}^2{a}_2-V_{DS}{}^2\right]\\ \begin{array}{l}{a}_1=2J^2(a{\lambda }_0)\sinh (L{\lambda }_0)\\ a_2=4J^2(a{\lambda }_0){\sinh }^2(L{\lambda }_0)\end{array}\}\end{array}\}$$

(30)

Therefore, the threshold voltage for the short channel is:

$$V_{T{H}_b}=\frac{-Y_2+\sqrt{{Y_2}^2-4Y_1{Y}_3}}{2Y_1}$$

(31)

Like the closed-form expression of the short channel threshold voltage for the external gate of CSDG MOSFET is given as:

$$V_{T{H}_{Sb}\_CSDG}=\left(2{\varphi }_f+V_{FB}+{\psi }_{1D}(0)-\frac{q{N}_A{b}^2}{4{\epsilon }_{si}}+\frac{q{N}_A{t^2}_{si}}{16{\epsilon }_{si}}+\frac{q{N}_A{t_{si}}^2{C}_{si}}{4{\epsilon }_{si}{C}_{ox-b}}\right)-\left(\frac{-Y_2+\sqrt{Y_2{}^2-4Y_1{Y}_3}}{2Y_1}\right)$$

(32)

Therefore, the threshold voltage of the short channel can be determined either through the internal gate minimum surface potential or the external gate minimum surface potential of the CSDG MOSFET as given in Equations (27) and (32).

4. Subthreshold Current and Subthreshold Swing

This section presents the subthreshold current and the subthreshold swing close-form expression using the minimum surface potential derived from Equation (17). Subthreshold swing determines the device’s behavior by showing the effect of the change in external gate voltage on the subthreshold current. In an ideal MOSFET, the subthreshold current is zero when the applied gate voltage is lesser than threshold voltage. However, in the practical aspect, such behavior is never obtainable. The ideal subthreshold swing value at room temperature is 60 mV/dec. Furthermore, the analyses are verified with the numerical simulation.

4.1. Subthreshold Current

The subthreshold current flows from source to drain along the channel length through diffusion mechanism. Hence, the subthreshold current is given by integration with respect to the circular area as given [41]:

$$\begin{array}{l}{I}_{Sub}=q\pi t_{si}{D}_n\frac{n_m(r,z)}{L}\left[1-e^{\frac{-V_{DS}}{V_T}}\right]\\ D_n=\mu V_T\end{array}\}$$

(33)

where n_m is the electron density at subthreshold regime in relation to classical Boltzmann’s equation. it is given as:

$$n_m(r,z)=\frac{n_i{}^2}{N_A}{e}^{\left(\frac{\psi (r,z)}{V_T}\right)}$$

(34)

D_n, V_T, and n_i are the diffusion constant, thermal voltage, and intrinsic concentration respectively. Using the Equation (33), assuming the subthreshold current occurs at the virtual cathode (z = zmin), the subthreshold current of CSDG MOSFT (I__CSDG) is obtained by:

$$I_{CSDG\_sub}=I_a+I_b$$

(35a)

$$I_{CSDG}=\frac{q\pi t_{si}{D}_n{n}_m(r,z_{\min })\left[1-e^{\frac{-V_{DS}}{V_T}}\right]}{{\displaystyle \underset{0}{\overset{l}{\int }}{M}^{-1}(z)dz}}+\frac{q\pi t_{si}{D}_n{n}_m(r,z_{\min })\left[1-e^{\frac{-V_{DS}}{V_T}}\right]}{{\displaystyle \underset{0}{\overset{l}{\int }}{N}^{-1}(z)dz}}$$

(35b)

where:

$$M(z)=\frac{q{n}_i{}^2}{N_A}{\displaystyle \underset{\frac{t_{si}}{2}}{\overset{a}{\int }}{f}_a(r)}dr , N(z)=\frac{q{n}_i{}^2}{N_A}{\displaystyle \underset{a}{\overset{b}{\int }}{f}_b(r)dr},f(r)=e^{\frac{q\psi (r,z_{\min })}{KT}}\}$$

(36)

M(z) and N(z) can be obtained by integrating the indefinite f_a(r) and f_b(r) through the trapezoidal rule of numerical approach as given by [40]:

$$\begin{array}{l}M=\frac{q{n}_i{}^2}{N_A}{G}_a\left[\left(e^{\frac{q{\psi }_{\min }}{kT}}\right)+\left({\displaystyle \sum _{k=1}^{n-1}\left(e^{\frac{\psi (G_{a}k,z_{\min })}{KT}}\right)+e^{\frac{q\psi (0,z_{\min })}{KT}}}\right)\right]\\ G_a=\frac{a}{2n}\end{array}\}$$

(37a)

$$\begin{array}{l}N=\frac{q{n}_i{}^2}{N_A}{G}_b\left[\left(e^{\frac{q{\psi }_{\min }}{kT}}\right)+\left({\displaystyle \sum _{k=1}^{n-1}\left(e^{\frac{\psi (G_{b}k,z_0{}_{\min })}{KT}}\right)+e^{\frac{q\psi (0,z_{0\min })}{KT}}}\right)\right]\\ G_b=\frac{b}{2n}\end{array}\}$$

(37b)

By equating the partition number to one (n = 1) in Equations (37a) and (37b), the subthreshold current for CSDG MOSFET can be obtained in Equation (35b).

4.2. Subthreshold Swing

Subthreshold swing (SS) is defined as the change in gate bias voltage required for a change of one decade of subthreshold drain current [42]. Since, subthreshold swing is an important device parameter to represents the switching characteristics of MOS device, Hence, its evaluation is a necessity and it is given as [43]:

$$SS={\left[\frac{d\log I_{CSDG\_sub}}{d{V}_{GS}}\right]}^{-1}$$

(38)

By substituting Equation (35b) into Equation (38), the subthreshold swing can be calculated, since the ψ (r, z_min) is a function of change in voltage (dv) from Equation (38) and dV is a function of gate voltage. However, the subthreshold swing is very difficult to obtain using the subthreshold current due to its complicated dependency of the minimum radius (r_min) on the gate voltage and the numerical integration involved. In a simpler approach, the subthreshold current can be related to the minimum surface potential, ψ_{s_min}(r, z_min) through the electron concentration at the virtual cathode [44]. This is because at subthreshold operation, the subthreshold current is dominated by a diffusion process. This leads to a probability of mobile electron surmounting the source end of the energy barrier. Thus, it can be assumed that the subthreshold current is proportional to the carrier concentration at the virtual cathode n_min (r, z_min), given as [42]:

$$I_{sub}·\alpha ·n_{\min }(r,z_{\min })\alpha ·e^{\left(\frac{{\psi }_{\min }}{V_T}\right)}$$

(39)

Since the electron density follows Boltzmann distribution according [45] we can express the SS by substituting Equation (39) in Equation (38) as given:

$$S{S}_{CSDG}=\frac{V_{T}In10}{\left(\frac{d{\psi }_{s_{\min }}(r,z_{\min })}{d{V}_{GS}}\right)}$$

(40)

where $V_T=\frac{KT}{q}$.

From Equation (39) minimum surface potential can be obtained as:

$$\psi (r,z_{\min })=\psi (r)+\psi (r,z_{\min })=\psi (r)+2J_0(r\lambda )\sqrt{A_1{B}_1}$$

(41)

$$\begin{array}{r}{\psi }_{s_{\min }}(r_{\min })=(V_{GS}-V_{FB})+\frac{q{N}_A{r}^2}{4{\epsilon }_{si}}-\frac{q{N}_A{t}^2{}_{si}}{16{\epsilon }_{si}}-\frac{q{N}_A{t}_{si}{}^2{C}_{si}}{4{\epsilon }_{si}{C}_{ox-a}}\\ +\left(A_0{e}^{(z_{\min }{\lambda }_0)}+B_0{e}^{(-z_{\min }{\lambda }_0)}\right)J_0(r{\lambda }_0)\end{array}$$

(42)

$$\frac{d{\psi }_{s_{\min }}(r,z_{\min })}{d{V}_{GS}}=\frac{d\psi (r)}{d{V}_{GS}}+\frac{d\psi (r,z_{\min })}{d{V}_{GS}}$$

(43)

Therefore, the subthreshold swing can be obtained using Equations (40), (42), and (43). The simulation results of the close form expression obtained and the numerical results are explained in the further sections.

5. Results and Discussions

In this section, the theoretical and numerical simulation results are presented using Equations (27), (32), (35), and (40). The list of parameters used for the CSDG MOSFETs are given in

Table 1. The device parameters for simulation.

Parameters	Values
tox1, tox2	2–5 nm (each)
L	9–90 nm
a	3–6 nm
b	13 nm
tsi = (b − a)	10 nm
NA	1017 cm−3
ΦMS1, ΦMS2	4.8 eV
VDS	0.1 V

.

The threshold voltage of the internal and external gate CSDG MOSFET with variation of channel length is shown in Figure 5. It has been observed that the decrease in channel length, causes a corresponding rapid decrease in the threshold voltage. The phenomenon is called the threshold roll-off which can be determined with either the internal gate or external gate model. Although, the threshold voltage between the internal and external gate are almost the same. However, the external gate has lightly higher threshold voltage than the internal gate due to higher minimum surface potential as shown in Figure 5. The external gate is in perfect match with the numerical simulation.

The thin gate oxide of the internal and external structure of the CSDG MOSFET enables the dominance of the vertical electrical fields over the lateral electric field resulting from the drain and source ends. This enables the two gates to have better control of the channels created within the structure. Furthermore, the dominance of the vertical electric field will result to less leakage of current when the device is turned off. The variation of threshold voltage with channel length at different oxide thickness is shown in Figure 6. It is clearly observed that the decrease in channel length, results to the decrease in threshold voltage which affects the device performance. Additionally, the lower the threshold voltage, the more unpredictable the device switching performance. This degrades the switching characteristics of the device during the turn-OFF stage. However, higher threshold voltage enhances stability and accurate switching of the device. We optimized the threshold voltage with different oxide thickness. The threshold voltage increases with decrease in gate oxide, hence, thin gate oxide tends to provide better gate controllability than the thicker oxide. Additionally, thin gate oxide reduces SCEs in CSDG MOSFETs. The result is in good agreement with the numerical simulation of the proposed structure.

Furthermore, the thinner radii silicon film difference of the CSDG MOSFET structure enhances the internal and external gate controls of the channel carriers over the drain and source ends. The reduction in radii difference further reduces the drain and source sizes, and their impact on the channel is significantly reduced. Hence, the gates have better control of the channel carriers. The variation of threshold voltage with channel length at different radii silicon film thickness is shown in Figure 7. It is observed that as the silicon film thickness decreases, the threshold voltage of CSDG MOSFET increases because the drain ends losses control of the channel. As a result, the thin silicon film provides better gate controllability leading to low threshold voltage degradation and better suppression of SCEs. The result matches the numerical simulation of the proposed structure.

The CSDG MOSFETs provides higher drain current due to the coupled internal and external gates. These gates increase the average electric field of the structure. This enables rapid acceleration of carriers at the interface towards the drain terminal, resulting to the enhancement of the carrier transportation efficiency for the proposed structure. However, an increase in the drain current causes slight increase in the subthreshold leakage current, which needs to be minimized at less than 30 nm gate length. The subthreshold current versus the gate voltage with different variation in channel length is shown in Figure 8. The channel length is varied from 60 nm to 20 nm. It is clearly observed that the subthreshold current increases as the channel length decreases with an upward shift as clearly observed. This implies lesser control of the gate over the channel at lower channel length resulting to more leakage current. It is should be noted that the model is considered at the subthreshold regime. The slight deviation of the numerical simulation from model towards 0.5 V of the gate voltage shows the inversion onset phase. The model matches with the numerical simulation for the proposed structure within the subthreshold regime.

Furthermore, the presence of the thin gate oxide on the proposed CSDG MOSFET reduces the subthreshold leakage current by enabling greater gate control over the channel and minimal lateral Electric Field effects. The subthreshold current versus the gate voltage with respect to different variation of the gate oxide thickness is shown in Figure 9. It is observed that the as the gate-oxide thickness increases, the subthreshold current leakage also increases. The increased gate oxide reduces the gate control over the channel and the leakage due to impacts from the drain is added to the channel. Hence, the thin oxide is preferred over thicker oxide. However, a balance must be maintained to prevent gate-tunneling. The deviation of the numerical simulation toward 0.5 V shows the onset of the strong inversion. The numerical simulation is in good agreement with the model within the subthreshold regime.

Additionally, the internal and external gates voltage describes the exponential behavior of the current in the CSDG MOSFET at subthreshold. This exponential behavior known as the subthreshold swing which increases at shorter gate lengths is minimized in CSDG MOSFET with thin oxide thickness. The smaller subthreshold swing enables better channel control by the gates at micro power application. The subthreshold swing versus channel length for different oxide thickness is presented in Figure 10. Subthreshold swing decreases significantly as the oxide thickness decreases because the gates enhances effective channel control. Hence, a thin oxide thickness provides excellent immunity over SCEs. Furthermore, the model matches the numerical simulation of the proposed structure.

Furthermore, the reduction in radii Silicon film difference of the CSDG MOSFET enhances the device performance. The subthreshold swing has been minimized by thin radii silicon film. The internal and external gate control over the channel minimizes the lateral field effects from drain end. This results to increase in the threshold voltage. Since the subthreshold swing depends on the gate voltage, increasing the threshold voltage leads to gradual reduction in the subthreshold swing. The subthreshold swing versus channel length at various silicon film thickness is shown in Figure 11. It is obviously seen that as the channel length decrease, the subthreshold swing increases which is a major problem in scaling at nanometer. This affects the switching characteristics of the of device structure. However, as the radii silicon film thickness decreases, the subthreshold swing decreases. At 10 nm radii silicon film thickness, the subthreshold swing decreases below 80 mV/dec., enabling faster switching characteristics of the device structure. Hence, thin radii silicon film thickness helps in SCEs suppression at reduced channel length. The numerical simulation matches perfectly with the proposed device model.

6. Conclusions and Recommendations

In this research work, the close form expression for the threshold voltage, subthreshold current, and the subthreshold swing has been derived using evanescent-mode analysis to demonstrate the performance of the CSDG MOSFET. The behavior of the SCEs with various device parameters like radii silicon film thickness, gate-oxide thickness, and the channel length has been considered to predict the device performance. Results shows that the threshold voltage decreases with decrease in channel length. This results to threshold voltage roll-off which is due to 2D field effect that originated from the source and drain region because of their proximity to the channel at nanoscale length. However, this is optimized by decreasing the oxide thickness and radii silicon film difference of the CSDG MOSFET to increase the stability of the threshold voltage and better control of the turn-OFF current. This shows that the CSDG MOSFET improves immunity to SCEs, making it a promising device for the future nanometer MOSFET applications.

Although, the subthreshold swing increases above 60 mV/dec at room temperature as the channel length decreases. However, it decreases with proportional decrease in radii silicon film thickness or gate-oxide thickness which enhances the switching performance of the device for CMOS technology application. Additionally, it is observed that the decrease in the device channel length increases the subthreshold current leakage. However, the coupling of the internal and external gate control over the channel limits the leakage. Hence, making CSDG MOSFET, a suitable device for nanoscale switching operation.