Journal of Low Power Electronics and Applications

28 pages, 5178 KiB

Open AccessArticle

Multiple-Output DC-DC Converters with a Reduced Number of Active and Passive Components

by Mert Turhan, Juan C. Castellanos, Marcel A. M. Hendrix, Jorge L. Duarte and Elena A. Lomonova

J. Low Power Electron. Appl. 2019, 9(3), 28; https://0-doi-org.brum.beds.ac.uk/10.3390/jlpea9030028 - 18 Sep 2019

Cited by 6 | Viewed by 6474

Multiple-output converters have been widely used where individual outputs are required. Compared with conventional separate converters, the advantage of multiple outputs is to have a lower number of active and passive components. In this paper, first, a pulse-width-modulation (PWM)-pulse-frequency-modulation (PFM) method is used [...] Read more.

Multiple-output converters have been widely used where individual outputs are required. Compared with conventional separate converters, the advantage of multiple outputs is to have a lower number of active and passive components. In this paper, first, a pulse-width-modulation (PWM)-pulse-frequency-modulation (PFM) method is used for two-output converters that have only one coil and one active switch. Secondly, three-output converter topologies are proposed where the third output is controlled by phase delay (PD). These converters need only two coils and two active switches to regulate three outputs. How to obtain PD at different switching frequencies is discussed next, and a PWM-PFM-PD controlled five-output buck converter is presented. The proposed solution uses only two active switches and two magnetic cores to adjust five-output voltages independently. A modeling and digital control method are proposed in order to regulate the five output voltages. A prototype circuit with independent 15 V/1.5 A, 12 V/1.5 A, 5 V/0.8 A, −5 V/0.6 A and 3.3 V/0.45 A outputs is assembled to validate the analysis, and it was proved that it regulates the output voltages at different loads. Full article

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13 pages, 6089 KiB

Open AccessArticle

Synchronous Counter Design Using Novel Level Sensitive T-FF in QCA Technology

by Ali H. Majeed, Esam Alkaldy, Mohd Shamian bin Zainal and Danial Bin MD Nor

J. Low Power Electron. Appl. 2019, 9(3), 27; https://0-doi-org.brum.beds.ac.uk/10.3390/jlpea9030027 - 05 Sep 2019

Cited by 34 | Viewed by 7195

Abstract

The quantum-dot cellular automata (QCA) nano-technique has attracted computer scientists due to its noticeable features such as low power consumption and small size. Many papers have been published in the literature about the utilization of this technology for de-signing many QCA circuits and [...] Read more.

The quantum-dot cellular automata (QCA) nano-technique has attracted computer scientists due to its noticeable features such as low power consumption and small size. Many papers have been published in the literature about the utilization of this technology for de-signing many QCA circuits and for presenting logic gates in an optimal structure. The T flip-flop, which is an essential part of digital designs, can be used to design synchronous and asynchronous counters. This paper presents a novel T flip-flop structure in an optimal form. The presented novel gate was used to design an N-bit binary synchronous counter. The QCADesigner software was used to verify the designed circuits and to present the simulation results, while the QCAPro tool was used for the power analysis. The proposed design required minimal power and showed good improvements over previous designs. Full article

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15 pages, 3310 KiB

Open AccessReview

CMOS Inverter as Analog Circuit: An Overview

by Woorham Bae

J. Low Power Electron. Appl. 2019, 9(3), 26; https://0-doi-org.brum.beds.ac.uk/10.3390/jlpea9030026 - 20 Aug 2019

Cited by 28 | Viewed by 26225

Abstract

Since the CMOS technology scaling has focused on improving digital circuit, the design of conventional analog circuits has become more and more difficult. To overcome this challenge, there have been a lot of efforts to replace conventional analog circuits with digital implementations. Among [...] Read more.

Since the CMOS technology scaling has focused on improving digital circuit, the design of conventional analog circuits has become more and more difficult. To overcome this challenge, there have been a lot of efforts to replace conventional analog circuits with digital implementations. Among those approaches, this paper gives an overview of the latest achievement on utilizing a CMOS inverter as an analog circuit. Analog designers have found that a simple resistive feedback pulls a CMOS inverter into an optimum biasing for analog operation. Recently developed applications of the resistive-feedback inverter, including CMOS inverter as amplifier, high-speed buffer, and output driver for high-speed link, are introduced and discussed in this paper. Full article

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18 pages, 868 KiB

Open AccessArticle

Reconfigurable Analog Preprocessing for Efficient Asynchronous Analog-to-Digital Conversion

by Brandon M. Kelly, Alexander T. DiLello and David W. Graham

J. Low Power Electron. Appl. 2019, 9(3), 25; https://0-doi-org.brum.beds.ac.uk/10.3390/jlpea9030025 - 12 Aug 2019

Cited by 8 | Viewed by 6336

Abstract

Wearable medical devices, wireless sensor networks, and other energy-constrained sensing devices are often concerned with finding specific data within more-complex signals while maintaining low power consumption. Traditional analog-to-digital converters (ADCs) can capture the sensor information at a high resolution to enable a subsequent [...] Read more.

Wearable medical devices, wireless sensor networks, and other energy-constrained sensing devices are often concerned with finding specific data within more-complex signals while maintaining low power consumption. Traditional analog-to-digital converters (ADCs) can capture the sensor information at a high resolution to enable a subsequent digital system to process for the desired data. However, traditional ADCs can be inefficient for applications that only require specific points of data. This work offers an alternative path to lower the energy expenditure in the quantization stage—asynchronous content-dependent sampling. This asynchronous sampling scheme is achieved by pairing a flexible analog front-end with an asynchronous successive-approximation ADC and a time-to-digital converter. The versatility and reprogrammability of this system allows a multitude of event-driven, asynchronous, or even purely data-driven quantization methods to be implemented for a variety of different applications. The system, fabricated in standard 0.5

μ

m and 0.35

μ

m processes, is demonstrated along with example applications with voice, EMG, and ECG signals. Full article

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13 pages, 4215 KiB

Open AccessArticle

Memristor-Based Loop Filter Design for Phase Locked Loop

by Naheem Olakunle Adesina and Ashok Srivastava

J. Low Power Electron. Appl. 2019, 9(3), 24; https://0-doi-org.brum.beds.ac.uk/10.3390/jlpea9030024 - 29 Jul 2019

Cited by 16 | Viewed by 7370

Abstract

The main challenge in designing a loop filter for a phase locked loop (PLL) is the physical dimensions of the passive elements used in the circuit that occupy large silicon area. In this paper, the basic features of a charge-controlled memristor are studied [...] Read more.

The main challenge in designing a loop filter for a phase locked loop (PLL) is the physical dimensions of the passive elements used in the circuit that occupy large silicon area. In this paper, the basic features of a charge-controlled memristor are studied and the design procedures for various components of a PLL are examined. Following this, we propose a memristor-based filter design which has its resistance being replaced by a memristor in order to reduce the die area and achieve a low power consumption. We obtained a tuning range of 741–994 MHz, a stable output frequency of 1 GHz from the transfer characteristics of voltage-controlled oscillator (VCO), and an improved settling time. In addition to reduced power consumption and area occupied on the chip, our design shows a high reliability over wider range of temperature variations. Full article

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25 pages, 6268 KiB

Open AccessArticle

A New Approach for Optimizing Management of a Real Time Solar Charger Using the Firebase Platform Under Android

by Mohamed Redha Rezoug, Rachid Chenni and Djamel Taibi

J. Low Power Electron. Appl. 2019, 9(3), 23; https://0-doi-org.brum.beds.ac.uk/10.3390/jlpea9030023 - 16 Jul 2019

Cited by 5 | Viewed by 7443

Abstract

With the continuous growth of energy consumption, the rationalization of energy has become a priority. The photovoltaic energy sector remains a major occupation for researchers in the field of production optimization or storage methods. The concept developed in this work is a mixed [...] Read more.

With the continuous growth of energy consumption, the rationalization of energy has become a priority. The photovoltaic energy sector remains a major occupation for researchers in the field of production optimization or storage methods. The concept developed in this work is a mixed optimization approach for energy management during battery charging with a duty cycle. A selective collaborative algorithm intervenes to choose and use the appropriate results of the few techniques to optimize the charging time of a battery and estimate its state of charge by using the minimum possible tools. This is done using a collective database that is accessible in real time. It also effectively allows the synchronization of information between several customers. This approach is performed on a mobile application on android, through a Google Firebase platform that allows us to secure collaborative access between multiple customers and use the results of the calculations of some algorithms. It gives us the values obtained by the various sensors in real time to accelerate the charging speed of the battery. The validation of this approach led us to practice a few scenarios using an Arduino board to show that this approach has a better performance. Full article

(This article belongs to the Special Issue Electronic System-Level HW/SW Co-Design of Power-Aware Embedded Systems)

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19 pages, 6563 KiB

Open AccessArticle

FFC NMR Relaxometer with Magnetic Flux Density Control

by António Roque, Duarte M. Sousa, Pedro Sebastião, Elmano Margato and Gil Marques

J. Low Power Electron. Appl. 2019, 9(3), 22; https://0-doi-org.brum.beds.ac.uk/10.3390/jlpea9030022 - 13 Jul 2019

Cited by 2 | Viewed by 5361

Abstract

This paper describes an innovative solution for the power supply of a fast field cycling (FFC) nuclear magnetic resonance (NMR) spectrometer considering its low power consumption, portability and low cost. In FFC cores, the magnetic flux density must be controlled in order to [...] Read more.

This paper describes an innovative solution for the power supply of a fast field cycling (FFC) nuclear magnetic resonance (NMR) spectrometer considering its low power consumption, portability and low cost. In FFC cores, the magnetic flux density must be controlled in order to perform magnetic flux density cycles with short transients, while maintaining the magnetic flux density levels with high accuracy and homogeneity. Typical solutions in the FFC NMR literature use current control to get the required magnetic flux density cycles, which correspond to an indirect magnetic flux density control. The main feature of this new relaxometer is the direct control of the magnetic flux density instead of the magnet current, in contrast with other equipment available in the market. This feature is a great progress because it improves the performance. With this solution it is possible to compensate magnetic field disturbances and parasitic magnetic fields guaranteeing, among other possibilities, a field control below the earth magnetic field. Experimental results validating the developed solution and illustrating the real operation of this type of equipment are shown. Full article

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11 pages, 10852 KiB

Open AccessArticle

Design and Analysis of SEU Hardened Latch for Low Power and High Speed Applications

by Satheesh Kumar S and Kumaravel S

J. Low Power Electron. Appl. 2019, 9(3), 21; https://0-doi-org.brum.beds.ac.uk/10.3390/jlpea9030021 - 02 Jul 2019

Cited by 6 | Viewed by 6000

Abstract

Due to the reduction in technology scaling, gate capacitance and charge storage in sensitive nodes are rapidly decreasing, making Complementary Metal Oxide Semiconductor (CMOS) circuits more sensitive to soft errors caused by radiation. In this paper, a low-power and high-speed single event upset [...] Read more.

Due to the reduction in technology scaling, gate capacitance and charge storage in sensitive nodes are rapidly decreasing, making Complementary Metal Oxide Semiconductor (CMOS) circuits more sensitive to soft errors caused by radiation. In this paper, a low-power and high-speed single event upset radiation hardened latch is proposed. The proposed latch can withstand single event upsets completely when the high energy particle hit on any one of its intermediate nodes. The proposed latch structure comprises of four CMOS feedback schemes and a Muller C-element with clock gating technique. For the sake of comparison, the proposed and the existing latches in the literature are implemented in 45nm CMOS technology. From the post layout simulation results, it may be noted that the proposed latch achieves 8% low power consumption, 95% less delay, and a 94% reduction in power-delay-product compared to the existing single event upset resilient and single event tolerant latches. Monte Carlo simulations show that the proposed latch is less sensitive to process, voltage, and temperature variations in comparison with the existing hardened latches in the literature. Full article

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15 pages, 6915 KiB

Open AccessArticle

Ultrasound Sensor-Based Wireless Power Transfer for Low-Power Medical Devices

by Mustafa F. Mahmood, Saleem Latteef Mohammed and Sadik Kamel Gharghan

J. Low Power Electron. Appl. 2019, 9(3), 20; https://0-doi-org.brum.beds.ac.uk/10.3390/jlpea9030020 - 02 Jul 2019

Cited by 14 | Viewed by 7281

Abstract

Ultrasonic power transfer (UPT) is a promising method for wireless power transfer technology for low-power medical applications. Most portable or wearable medical devices are battery-powered. Batteries cannot be used for a long time and require periodic charging or replacement. UPT is a candidate [...] Read more.

Ultrasonic power transfer (UPT) is a promising method for wireless power transfer technology for low-power medical applications. Most portable or wearable medical devices are battery-powered. Batteries cannot be used for a long time and require periodic charging or replacement. UPT is a candidate technology for solving this problem. In this work, a 40-KHz ultrasound transducer was used to design a new prototype for supplying power to a wearable heart rate sensor for medical application. The implemented system consists of a power unit and heart rate measurement unit. The power unit includes an ultrasonic transmitter and receiver, rectifier, boost converter and super-capacitors. The heart rate measurement unit comprises measurement and monitoring circuits. UPT-based transfer power and efficiency were achieved using 1-, 4- and 8-Farad (F) super-capacitors. At 4 F, the system achieved 69.4% transfer efficiency and 0.318 mW power at 4 cm. In addition, 97% heart rate measurement accuracy was achieved relative to the benchmark device. The heart rate measurements were validated with statistical analysis. Our results show that this work outperforms previous works in terms of transfer power and efficiency with a 4-cm gap between the ultrasound transmitter and receiver. Full article

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J. Low Power Electron. Appl., Volume 9, Issue 3 (September 2019) – 9 articles

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