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Optimized Memory Allocation and Power Minimization for FPGA-Based Image Processing

FPGA-Based Processor Acceleration for Image Processing Applications

School of Electronics, Electrical Engineering and Computer Science, Queen’s University Belfast, Belfast BT7 1NN, UK
School of Computing, Electronics and Maths, Coventry University, Coventry CV1 5FB, UK
Author to whom correspondence should be addressed.
These authors contributed equally to this work.
Received: 27 November 2018 / Revised: 23 December 2018 / Accepted: 7 January 2019 / Published: 13 January 2019
(This article belongs to the Special Issue Image Processing Using FPGAs)
FPGA-based embedded image processing systems offer considerable computing resources but present programming challenges when compared to software systems. The paper describes an approach based on an FPGA-based soft processor called Image Processing Processor (IPPro) which can operate up to 337 MHz on a high-end Xilinx FPGA family and gives details of the dataflow-based programming environment. The approach is demonstrated for a k-means clustering operation and a traffic sign recognition application, both of which have been prototyped on an Avnet Zedboard that has Xilinx Zynq-7000 system-on-chip (SoC). A number of parallel dataflow mapping options were explored giving a speed-up of 8 times for the k-means clustering using 16 IPPro cores, and a speed-up of 9.6 times for the morphology filter operation of the traffic sign recognition using 16 IPPro cores compared to their equivalent ARM-based software implementations. We show that for k-means clustering, the 16 IPPro cores implementation is 57, 28 and 1.7 times more power efficient (fps/W) than ARM Cortex-A7 CPU, nVIDIA GeForce GTX980 GPU and ARM Mali-T628 embedded GPU respectively. View Full-Text
Keywords: FPGA; hardware acceleration; processor architectures; image processing; heterogeneous computing FPGA; hardware acceleration; processor architectures; image processing; heterogeneous computing
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MDPI and ACS Style

Siddiqui, F.; Amiri, S.; Minhas, U.I.; Deng, T.; Woods, R.; Rafferty, K.; Crookes, D. FPGA-Based Processor Acceleration for Image Processing Applications. J. Imaging 2019, 5, 16.

AMA Style

Siddiqui F, Amiri S, Minhas UI, Deng T, Woods R, Rafferty K, Crookes D. FPGA-Based Processor Acceleration for Image Processing Applications. Journal of Imaging. 2019; 5(1):16.

Chicago/Turabian Style

Siddiqui, Fahad; Amiri, Sam; Minhas, Umar I.; Deng, Tiantai; Woods, Roger; Rafferty, Karen; Crookes, Daniel. 2019. "FPGA-Based Processor Acceleration for Image Processing Applications" J. Imaging 5, no. 1: 16.

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