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Article

Side-Channel Power Resistance for Encryption Algorithms Using Implementation Diversity

1
Department of Electrical and Computer Engineering, University of New Mexico, Albuquerque, NM 87131, USA
2
Department of Electrical and Computer Engineering, University of North Carolina, Charlotte, NC 27599, USA
3
Klipsch School of Electrical and Computer Engineering, New Mexico State University, Las Cruces, NM 88003, USA
4
Department of Electrical Engineering and Computer Science, University of Maryland, Baltimore County, MD 20742, USA
*
Author to whom correspondence should be addressed.
Received: 25 February 2020 / Revised: 4 April 2020 / Accepted: 7 April 2020 / Published: 10 April 2020
(This article belongs to the Special Issue Feature Papers in Hardware Security)
This paper investigates countermeasures to side-channel attacks. A dynamic partial reconfiguration (DPR) method is proposed for field programmable gate arrays (FPGAs)s to make techniques such as differential power analysis (DPA) and correlation power analysis (CPA) difficult and ineffective. We call the technique side-channel power resistance for encryption algorithms using DPR, or SPREAD. SPREAD is designed to reduce cryptographic key related signal correlations in power supply transients by changing components of the hardware implementation on-the-fly using DPR. Replicated primitives within the advanced encryption standard (AES) algorithm, in particular, the substitution-box (SBOX)s, are synthesized to multiple and distinct gate-level implementations. The different implementations change the delay characteristics of the SBOXs, reducing correlations in the power traces, which, in turn, increases the difficulty of side-channel attacks. The effectiveness of the proposed countermeasures depends greatly on this principle; therefore, the focus of this paper is on the evaluation of implementation diversity techniques. View Full-Text
Keywords: side-channel attack countermeasure; FPGA dynamic partial reconfiguration; implementation diversity; moving target architecture side-channel attack countermeasure; FPGA dynamic partial reconfiguration; implementation diversity; moving target architecture
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MDPI and ACS Style

Bow, I.; Bete, N.; Saqib, F.; Che, W.; Patel, C.; Robucci, R.; Chan, C.; Plusquellic, J. Side-Channel Power Resistance for Encryption Algorithms Using Implementation Diversity. Cryptography 2020, 4, 13. https://0-doi-org.brum.beds.ac.uk/10.3390/cryptography4020013

AMA Style

Bow I, Bete N, Saqib F, Che W, Patel C, Robucci R, Chan C, Plusquellic J. Side-Channel Power Resistance for Encryption Algorithms Using Implementation Diversity. Cryptography. 2020; 4(2):13. https://0-doi-org.brum.beds.ac.uk/10.3390/cryptography4020013

Chicago/Turabian Style

Bow, Ivan, Nahome Bete, Fareena Saqib, Wenjie Che, Chintan Patel, Ryan Robucci, Calvin Chan, and Jim Plusquellic. 2020. "Side-Channel Power Resistance for Encryption Algorithms Using Implementation Diversity" Cryptography 4, no. 2: 13. https://0-doi-org.brum.beds.ac.uk/10.3390/cryptography4020013

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