Ultra-Low Voltage CMOS Front-End Design

A special issue of Electronics (ISSN 2079-9292). This special issue belongs to the section "Circuit and Signal Processing".

Deadline for manuscript submissions: closed (31 December 2022) | Viewed by 6278

Special Issue Editors

Service d’Électronique et Microélectronique, Université de Mons, 7000 Mons, Belgium
Interests: design and applications of analog integrated circuits/systems
Instituto de Microelectrónica de Sevilla, University of Seville, 41092 Seville, Spain
Interests: CMOS integrated circuits; biomedical electronics; neurophysiology; analogue-digital conversion; bioelectric potentials; low-power electronics
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Department of Electrical, Electronic and Telecommunications Engineering, and Naval Architecture, University of Genova, Via Opera Pia 11A, I16145 Genova, Italy
Interests: biomedical circuits and systems; electronic/artificial sensitive skin; tactile sensing systems for prosthetics and robotics; neuromorphic touch sensors; electronic and microelectronic systems
Special Issues, Collections and Topics in MDPI journals

Special Issue Information

Dear Colleagues,

As the Internet of Things (IoT) evolves to become a ubiquitous and pervasive technology, the development of its enabling technologies presents several challenges to circuit designers. Among them is the proper design of ultra-low-voltage low-power front ends to supply and interface the IoT sensor nodes, which must normally remain operable for weeks, months or even years, supplied by a single battery or by means of energy harvesting (EH) techniques.

Nowadays, thanks to the incessant evolution of integrated circuit technologies, more and more functionalities can be integrated in a real mixed-signal System on Chip (SoC) that satisfies the ever-increasing stringent requirements for IoT sensor nodes. Among others, the use of ultra-low-voltage and ultra-low-power consumption is critically claimed by IoT designers, especially when energy autonomy becomes an unavoidable feature for several applications (e.g., Smart Buildings, Smart Cities, Body Sensor Networks, Agriculture Sensors Networks, etc.).

When implemented in nano technologies, the operation of circuits with ultra-low-supply voltages becomes mandatory due to the strong reduction in geometries. As is well known, the power and area of digital circuits can be easily scaled down. In contrast, analog circuits suffer from performance degradation because of the reduced voltage headroom, high process dispersion, increased noise sensitivity and limited analog behavior of devices.

In conclusion, the major challenge for nano-circuit designers consists of proposing innovative and efficient circuit structures that are able to maintain an acceptable performance when operating from ultra-low-voltage low-power supply.

This Special Issue will focus on the following main topics:

  • Device modeling and biasing techniques for ultra-low-voltage low-power circuits;
  • Ultra-low-voltage pico/femtoampere analog and digital circuit design;
  • Multi-source energy harvesting circuits and systems;
  • Energy harvesting-powered DCDC converters;
  • Ultra-low-voltage data converters;
  • Ultra-low-voltage sensor readout interfaces;
  • Implantable devices for biomedical applications;
  • Ultra-low-voltage wearable electronics for body sensor networks;
  • Biodegradable autonomous sensors;
  • Autonomous healthcare circuits and systems.

Prof. Dr. Fortunato Dualibe
Dr. Rafaella Fiorelli
Prof. Dr. Maurizio Valle
Guest Editors

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Published Papers (2 papers)

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18 pages, 14281 KiB  
Article
CMOS Front End for Interfacing Spin-Hall Nano-Oscillators for Neuromorphic Computing in the GHz Range
by Rafaella Fiorelli, Eduardo Peralías, Roberto Méndez-Romero, Mona Rajabali, Akash Kumar, Mohammad Zahedinejad, Johan Åkerman, Farshad Moradi, Teresa Serrano-Gotarredona and Bernabé Linares-Barranco
Electronics 2023, 12(1), 230; https://0-doi-org.brum.beds.ac.uk/10.3390/electronics12010230 - 03 Jan 2023
Viewed by 2807
Abstract
Spin-Hall-effect nano-oscillators are promising beyond the CMOS devices currently available, and can potentially be used to emulate the functioning of neurons in computational neuromorphic systems. As they oscillate in the 4–20 GHz range, they could potentially be used for building highly accelerated neural [...] Read more.
Spin-Hall-effect nano-oscillators are promising beyond the CMOS devices currently available, and can potentially be used to emulate the functioning of neurons in computational neuromorphic systems. As they oscillate in the 4–20 GHz range, they could potentially be used for building highly accelerated neural hardware platforms. However, due to their extremely low signal level and high impedance at their output, as well as their microwave-range operating frequency, discerning whether the SHNO is oscillating or not carries a great challenge when its state read-out circuit is implemented using CMOS technologies. This paper presents the first CMOS front-end read-out circuitry, implemented in 180 nm, working at a SHNO oscillation frequency up to 4.7 GHz, managing to discern SHNO amplitudes of 100 µV even for an impedance as large as 300 Ω and a noise figure of 5.3 dB300 Ω. A design flow of this front end is presented, as well as the architecture of each of its blocks. The study of the low-noise amplifier is deepened for its intrinsic difficulties in the design, satisfying the characteristics of SHNOs. Full article
(This article belongs to the Special Issue Ultra-Low Voltage CMOS Front-End Design)
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12 pages, 5375 KiB  
Article
A 1.2-µW 41-dB Ripple Attenuation Chopper Amplifier Using Auto-Zero Offset Cancelation Loop for Area-Efficient Biopotential Sensing
by Xuan Thanh Pham, Trung Kien Vu, Tien Dzung Nguyen and Loan Pham-Nguyen
Electronics 2022, 11(7), 1149; https://0-doi-org.brum.beds.ac.uk/10.3390/electronics11071149 - 06 Apr 2022
Cited by 6 | Viewed by 2271
Abstract
In this paper, a low-power and low-noise capacitive-coupled chopper instrumentation amplifier (CCIA) is proposed for biopotential sensing applications. A chopping technique is applied to mitigate the domination of flicker noise at low frequency. A new offset cancellation loop is also used to deal [...] Read more.
In this paper, a low-power and low-noise capacitive-coupled chopper instrumentation amplifier (CCIA) is proposed for biopotential sensing applications. A chopping technique is applied to mitigate the domination of flicker noise at low frequency. A new offset cancellation loop is also used to deal with the intrinsic offset, originating from process variation, to reduce ripple noise at the output of CCIA. Moreover, the optimization of the chip area was resolved by adding a T-network capacitor in the negative feedback loop. The CCIA is designed on 0.18 µm process CMOS technology with a total chip area of 0.09 mm2. The post-simulation results show that the proposed architecture can attenuate the output ripple up to 41 dB with a closed-loop gain of 40 dB and up to 800 Hz of bandwidth. The integrated input referred noise (IRN) of the CCIA is 1.8 µVrms over a bandwidth of 200 Hz. A noise efficiency factor (NEF) of 5.4 is obtained with a total power dissipation of 1.2 µW and a supply voltage of 1 V, corresponding to a power efficiency factor of 9.7 that is comparable with that of state-of-the-art studies. Full article
(This article belongs to the Special Issue Ultra-Low Voltage CMOS Front-End Design)
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