Fault-Tolerant Design and Applications of Electronic Circuits and Systems

A special issue of Electronics (ISSN 2079-9292). This special issue belongs to the section "Circuit and Signal Processing".

Deadline for manuscript submissions: closed (31 March 2022) | Viewed by 6190

Special Issue Editor

School of Computer Science and Engineering, Nanyang Technological University, 50 Nanyang Avenue, Singapore 639798, Singapore
Interests: approximate computing; asynchronous circuits; computer arithmetic; digital integrated circuits; fault-tolerant design; reliability; logic synthesis
Special Issues, Collections and Topics in MDPI journals

Special Issue Information

Dear Colleagues,

Electronic circuits and systems used in many real-world safety-critical applications such as space, aerospace, defense, nuclear power plants, electric power transmission and distribution, industrial control and automation, and banking and finance etc. usually involve fault-tolerant design at the hardware and/or software level for enhanced reliability. Fault-tolerant design is essential to cope with the faults or failures of circuits and systems. Fault-tolerant design involves some form of redundancy which may be static or dynamic or a mix of both. This special issue aims to deal with recent advances in fault-tolerant design at the hardware and software levels. Given this, we invite high quality academic and industrial research work on all aspects of fault-tolerant design and reliability. The topics of interest include but are not limited to:

  • Methods for assessing reliability of devices, circuits and systems
  • Fault tolerance in low power electronics: microelectronics, nanoelectronics and optoelectronics
  • Fault tolerance in memories
  • Fault tolerance in communication systems
  • Fault tolerance in high power electronics
  • Fault tolerance in renewable energy systems including solar, wind, wave, geothermal etc.
  • Fault tolerance in emerging technologies
  • Software fault tolerance
  • Impact of radiation on reliability of devices, circuits and systems
  • Reliability assessment and prediction in space, aerospace and automotive systems
  • Modeling reliability versus ageing in low power and high power electronics
  • Reliability assessment of battery technologies

Dr. Padmanabhan Balasubramanian
Guest Editor

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Keywords

  • fault tolerance
  • redundancy
  • reliability
  • digital circuits
  • digital systems
  • logic design
  • low power
  • VLSI
  • power electronics
  • renewables
  • batteries

Published Papers (3 papers)

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Research

16 pages, 856 KiB  
Article
Communication-Induced Checkpointing with Message Logging beyond the Piecewise Deterministic (PWD) Model for Distributed Systems
by Jinho Ahn
Electronics 2021, 10(12), 1428; https://0-doi-org.brum.beds.ac.uk/10.3390/electronics10121428 - 14 Jun 2021
Cited by 2 | Viewed by 2166
Abstract
This paper introduces an effective communication-induced checkpointing protocol using message logging to enable the number of extra checkpoints to be far lower than the previous number. Even if a situation occurs in which it is decided that a process receiving a message has [...] Read more.
This paper introduces an effective communication-induced checkpointing protocol using message logging to enable the number of extra checkpoints to be far lower than the previous number. Even if a situation occurs in which it is decided that a process receiving a message has to perform forced checkpointing, our protocol allows the process to skip the forced checkpointing action if it recognizes that the state of its sender right before the receipt of the message is recoverable. Additionally, the communication-induced checkpointing protocol is thus not required to assume the piecewise deterministic model, despite being combined with message logging. This protocol can maintain these features by piggybacking a one-bit variable and an n-size vector on each message sent. Our simulation results verify our claim that the presented protocol performs much better than the representative optimized protocol with respect to the forced checkpointing frequency, regardless of the communication pattern. Full article
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12 pages, 3366 KiB  
Article
Area, Power and Speed Optimized Early Output Majority Voter for Asynchronous TMR Implementation
by Padmanabhan Balasubramanian and Nikos E. Mastorakis
Electronics 2021, 10(12), 1425; https://0-doi-org.brum.beds.ac.uk/10.3390/electronics10121425 - 14 Jun 2021
Viewed by 1582
Abstract
This paper presents a new, efficient asynchronous early output majority voter that can be used to effectively realize an asynchronous triple modular redundancy (TMR) implementation. For the input-output mode asynchronous realization, the dual-rail code was used for data encoding and four phase return-to-zero [...] Read more.
This paper presents a new, efficient asynchronous early output majority voter that can be used to effectively realize an asynchronous triple modular redundancy (TMR) implementation. For the input-output mode asynchronous realization, the dual-rail code was used for data encoding and four phase return-to-zero and return-to-one handshake schemes were separately used for data communication. The proposed majority voter requires 62.8% less area and dissipates 37% less power on average compared to the best of the existing asynchronous majority voters while considering both handshake schemes. Importantly, the reductions in area and power are achieved without sacrificing the speed. Example TMR implementations show that the proposed majority voter leads to simultaneous reductions in cycle time, silicon area, and power dissipation. As a result, the proposed majority voter enables improved optimization in figure-of-merits such as area–cycle time product, power–cycle time product, and area–cycle time–power product for TMR implementations utilizing it compared to TMR implementations incorporating other majority voters. The circuits were implemented using a 32/28-nm CMOS technology. Full article
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18 pages, 4040 KiB  
Article
A Self-Test, Self-Calibration and Self-Repair Methodology of Thermopile Infrared Detector
by Kaiyue Zhou, Jia Li, Weibing Wang and Dapeng Chen
Electronics 2021, 10(10), 1167; https://0-doi-org.brum.beds.ac.uk/10.3390/electronics10101167 - 13 May 2021
Viewed by 1297
Abstract
To improve the reliability and yield of thermopile infrared detectors, a self-test, self-calibration and self-repair methodology is proposed in this paper. A novel micro-electro-mechanical system (MEMS) infrared thermopile detector structure is designed in this method with a heating resistor building on the center [...] Read more.
To improve the reliability and yield of thermopile infrared detectors, a self-test, self-calibration and self-repair methodology is proposed in this paper. A novel micro-electro-mechanical system (MEMS) infrared thermopile detector structure is designed in this method with a heating resistor building on the center of the membrane. The heating resistor is used as the stimuli of the sensing element on chip to achieve a self-test, and the responsivity related with ambient temperature can be calibrated by the equivalent model between electrical stimuli and physical stimuli. Furthermore, a fault tolerance mechanism is also proposed to localize the fault and repair the detector if the detector fails the test. The simulation results with faults simulated by the Monte Carlo stochastic model show that the proposed scheme is an effective solution to improve the yield of the MEMS thermopile infrared detector. Full article
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