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A special issue of Electronics (ISSN 2079-9292). This special issue belongs to the section "Computer Science & Engineering".

Deadline for manuscript submissions: closed (30 September 2018) | Viewed by 61271

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Prof. Dr. Michael Hüebner

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Computer Engineering, Brandenburg University of Technology Cottbus-Senftenberg, Universitätsplatz 1, 01968 Senftenberg, Germany
Interests: reconfigurable computing; system on chip; embedded systems
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Special Issue Information

Dear Colleagues,

Novel trends in Cyber physical Systems, the Internet of things, and also neuronal networks and machine learning, need new hardware and architecture. The goal is to reduce energy consumption more, and to simultaneously increase performance. This Special Issue will cover novel trends, research, and the development of hardware and architecture, and contributes to the community with different views and solutions.

Prof. Dr. Michael Huebner
Guest Editor

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Manuscripts should be submitted online at www.mdpi.com by registering and logging in to this website. Once you are registered, click here to go to the submission form. Manuscripts can be submitted until the deadline. All submissions that pass pre-check are peer-reviewed. Accepted papers will be published continuously in the journal (as soon as accepted) and will be listed together on the special issue website. Research articles, review articles as well as short communications are invited. For planned papers, a title and short abstract (about 100 words) can be sent to the Editorial Office for announcement on this website.

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Keywords

Embedded system
Low power
Reconfigurable computing

Published Papers (10 papers)

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Research

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20 pages, 1376 KiB

Open AccessArticle

AnScalable Matrix Computing Unit Architecture for FPGA, and SCUMO User Design Interface

by Asgar Abbaszadeh, Taras Iakymchuk, Manuel Bataller-Mompeán, Jose V. Francés-Villora and Alfredo Rosado-Muñoz

Electronics 2019, 8(1), 94; https://0-doi-org.brum.beds.ac.uk/10.3390/electronics8010094 - 15 Jan 2019

Cited by 8 | Viewed by 5350

Abstract

High dimensional matrix algebra is essential in numerous signal processing and machine learning algorithms. This work describes a scalable square matrix-computing unit designed on the basis of circulant matrices. It optimizes data flow for the computation of any sequence of matrix operations removing the need for data movement for intermediate results, together with the individual matrix operations’ performance in direct or transposed form (the transpose matrix operation only requires a data addressing modification). The allowed matrix operations are: matrix-by-matrix addition, subtraction, dot product and multiplication, matrix-by-vector multiplication, and matrix by scalar multiplication. The proposed architecture is fully scalable with the maximum matrix dimension limited by the available resources. In addition, a design environment is also developed, permitting assistance, through a friendly interface, from the customization of the hardware computing unit to the generation of the final synthesizable IP core. For

N \times N

matrices, the architecture requires N ALU-RAM blocks and performs

O (N^{2})

, requiring

N^{2} + 7

and

N + 7

clock cycles for matrix-matrix and matrix-vector operations, respectively. For the tested Virtex7 FPGA device, the computation for

500 \times 500

matrices allows a maximum clock frequency of 346 MHz, achieving an overall performance of 173 GOPS. This architecture shows higher performance than other state-of-the-art matrix computing units. Full article

(This article belongs to the Special Issue Hardware and Architecture)

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13 pages, 1236 KiB

Open AccessArticle

Design and Optimization of Supercapacitor Hybrid Architecture for Power Supply-Connected Batteries Lifetime Enhancement

by Jaemin Kim, Donghwa Shin, Donkyu Baek and Jaehyun Park

Electronics 2019, 8(1), 41; https://0-doi-org.brum.beds.ac.uk/10.3390/electronics8010041 - 01 Jan 2019

Cited by 3 | Viewed by 3342

Abstract

AC power adapters for battery-operated systems, such as smartphones and notebook computers, not only supply run-time power to operate the devices but also charge the built-in batteries. The capacity of the adapter is optimized for the average power demand rather than the maximum power demand to reduce the size and weight of the adapter. Such a reduced capacity adapter may cause the battery to age even when the device is operated with the power adapter while under higher power demand, which is different from the expectation of most users. A recent study proposed a supercapacitor assist architecture to reduce the battery aging when the battery is powered by the adapter. However, the previous work only shows the potential of the architecture. In this work, we propose a design methodology to find the optimal setup for the supercapacitor hybrid architecture considering supercapacitor array structure and power conversion efficiency. The results show that a supercapacitor having 17.5 mF capacity and 20 V withstand voltage is enough to supply the deficient energy of a reduced capacity power adapter. Full article

(This article belongs to the Special Issue Hardware and Architecture)

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19 pages, 812 KiB

Open AccessFeature PaperArticle

An FPGA-Oriented Baseband Modulator Architecture for 4G/5G Communication Scenarios

by Mário Lopes Ferreira and João Canas Ferreira

Electronics 2019, 8(1), 2; https://0-doi-org.brum.beds.ac.uk/10.3390/electronics8010002 - 20 Dec 2018

Cited by 9 | Viewed by 4928

Abstract

The next evolution in cellular communications will not only improve upon the performance of previous generations, but also represent an unparalleled expansion in the number of services and use cases. One of the foundations for this evolution is the design of highly flexible, versatile, and resource-/power-efficient hardware components. This paper proposes and evaluates an FPGA-oriented baseband processing architecture suitable for communication scenarios such as non-contiguous carrier aggregation, centralized Cloud Radio Access Network (C-RAN) processing, and 4G/5G waveform coexistence. Our system is upgradeable, resource-efficient, cost-effective, and provides support for three 5G waveform candidates. Exploring Dynamic Partial Reconfiguration (DPR), the proposed architecture expands the design space exploration beyond the available hardware resources on the Zynq xc7z020 through hardware virtualization. Additionally, Dynamic Frequency Scaling (DFS) allows for run-time adjustment of processing throughput and reduces power consumption up to 88%. The resource overhead for DPR and DFS is residual, and the reconfiguration latency is two orders of magnitude below the control plane latency requirements proposed for 5G communications. Full article

(This article belongs to the Special Issue Hardware and Architecture)

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21 pages, 1147 KiB

Open AccessArticle

Module Based Floorplanning Methodology to Satisfy Voltage Island and Fixed Outline Constraints

by Srinath Balasubramanian, Arunapriya Panchanathan, Bharatiraja Chokkalingam, Sanjeevikumar Padmanaban and Zbigniew Leonowicz

Electronics 2018, 7(11), 325; https://0-doi-org.brum.beds.ac.uk/10.3390/electronics7110325 - 15 Nov 2018

Cited by 16 | Viewed by 3608

Abstract

Multiple supply voltage is the most prevalent method for low power reduction in the design of modern Integrated circuits. Floorplanning process in this design performs positioning of functional blocks in the layout satisfying both fixed outline and voltage island constraints. The floorplans while satisfying these two significant constraints causes significant rise in wirelength and congestion. In this paper, a congestion and wirelength aware floorplanning algorithm is proposed which allows effective placement of functional blocks in the layout to satisfying fixed outline and voltage island constraints simultaneously. To perform voltage island floorplanning, the proposed algorithm uses Skewed binary tree representation scheme to operate the functional blocks in its predefined voltage level. The proposed methodology determines the feasible dimensions of the functional blocks in the representation which aids the placement process for the reduction of congestion and wirelength. With these optimal dimensions of the functional blocks, floorplanning is also performed for the layouts of aspect 1:1, 2:1, and 3:1, to evaluate the ability of proposed algorithm for satisfying the fixed outline constraint. The proposed methodology is implemented in the layout of InternationalWorkshop on Logic and Synthesis (IWLS) benchmarks circuits for experimental purpose. The resulting floorplans were iteratively optimized for optimal reduction of wirelength and congestion. Experimental results show that the proposed methodology outperforms existing state-of-the-art approaches in wirelength reduction by about 18.65% and in congestion reduction by around 63%, while delivering the 30.35% power consumption. Full article

(This article belongs to the Special Issue Hardware and Architecture)

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18 pages, 3946 KiB

Open AccessArticle

A Pipelined FFT Processor Using an Optimal Hybrid Rotation Scheme for Complex Multiplication: Design, FPGA Implementation and Analysis

by Hung Ngoc Nguyen, Sheraz Ali Khan, Cheol-Hong Kim and Jong-Myon Kim

Electronics 2018, 7(8), 137; https://0-doi-org.brum.beds.ac.uk/10.3390/electronics7080137 - 02 Aug 2018

Cited by 10 | Viewed by 5666

Abstract

The fast Fourier transform (FFT) is the most prevalent algorithm for the spectral analysis of acoustic emission signals acquired at ultra-high sampling rates to monitor the condition of rotary machines. The complexity and cost of the associated hardware limit the use of FFT in real-time applications. In this paper, an efficient hardware architecture for FFT implementation is proposed based on the radix-2 decimation in frequency algorithm (R2DIF) and a feedback pipelined technique (FB) that allows effective sharing of storage between the input and output data at each stage of the FFT process via shift registers. The proposed design uses an optimal hybrid rotation scheme by combining the modified coordinate rotation digital computer (m-CORDIC) algorithm and a binary encoding technique based on canonical signed digit (CSD) for replacing the complex multipliers in FFT. The m-CORDIC algorithm, with an adaptive iterative monitoring process, improves the convergence of computation, whereas the CSD algorithm optimizes the multiplication of constants using a simple shift-add method. Therefore, the proposed design does not require the large memory typically entailed by existing designs to carry out twiddle factor multiplication in large-point FFT implementations, thereby reducing its area on the chip. Moreover, the proposed pipelined FFT processor uses only distributed logic resources and does not require expensive dedicated functional blocks. Experimental results show that the proposed design outperforms existing state-of-the-art approaches in speed by about 49% and in resource utilization by around 51%, while delivering the same accuracy and utilizing less chip area. Full article

(This article belongs to the Special Issue Hardware and Architecture)

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19 pages, 5971 KiB

Open AccessArticle

A Novel Supercapacitor/Lithium-Ion Hybrid Energy System with a Fuzzy Logic-Controlled Fast Charging and Intelligent Energy Management System

by Muhammad Adil Khan, Kamran Zeb, P. Sathishkumar, Muhammad Umair Ali, Waqar Uddin, S. Hussain, M. Ishfaq, Imran Khan, Hwan-Gue Cho and Hee-Je Kim

Electronics 2018, 7(5), 63; https://0-doi-org.brum.beds.ac.uk/10.3390/electronics7050063 - 04 May 2018

Cited by 42 | Viewed by 9554

Abstract

The electric powered wheelchair (EPW) is an essential assistive tool for people with serious injuries or disability. This manuscript describes the validation of applied research for reducing the charging time of an electric wheelchair using a hybrid electric system (HES) composed of a supercapacitor (SC) bank and a lithium-ion battery with a fuzzy logic controller (FLC)-based fast charging system for Li-ion batteries and a fuzzy logic-based intelligent energy management system (FLIEMS) for controlling the power flow within the HES. The fast charging FLC was designed to drive the voltage difference (V_d) among the different cells of a multi-cell battery and the cell voltage (V_c) of an individual cell. These parameters (voltage difference and cell voltage) were used as input voltages to reduce the charge time and activate a bypass equalization (BPE) scheme. BPE was introduced in this paper so that the battery operates within the safe voltage range. For SC/Li-ion HES, the FLIEMS presented in this paper controls the bi-directional power flow to smooth the power extracted from Li-ion batteries. Moreover, a dual active bridge isolated bidirectional DC converter (DAB-IBDC) was used for power conversion. The DAB-IBDC presented in this paper has the characteristics of galvanic isolation, and high power conversion efficiency compared to the conventional converter circuits due to the reduced reverse power flow and current stresses. Full article

(This article belongs to the Special Issue Hardware and Architecture)

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2761 KiB

Open AccessArticle

Integrated Circuit Conception: A Wire Optimization Technic Reducing Interconnection Delay in Advanced Technology Nodes

by Mohammed Darmi, Lekbir Cherif, Jalal Benallal, Rachid Elgouri and Nabil Hmina

Electronics 2017, 6(4), 78; https://0-doi-org.brum.beds.ac.uk/10.3390/electronics6040078 - 04 Oct 2017

Cited by 5 | Viewed by 6270

Abstract

As we increasingly use advanced technology nodes to design integrated circuits (ICs), physical designers and electronic design automation (EDA) providers are facing multiple challenges, firstly, to honor all physical constraints coming with cutting-edge technologies and, secondly, to achieve expected quality of results (QoR). An advanced technology should be able to bring better performances with minimum cost whatever the complexity. A high effort to develop out-of-the-box optimization techniques is more than needed. In this paper, we will introduce a new routing technique, with the objective to optimize timing, by only acting on routing topology, and without impacting the IC Area. In fact, the self-aligned double patterning (SADP) technology offers an important difference on layer resistance between SADP and No-SADP layers; this property will be taken as an advantage to drive the global router to use No-SADP less resistive layers for critical nets. To prove the benefit on real test cases, we will use Mentor Graphics’ physical design EDA tool Nitro-SoC™ and several 7 nm technology node designs. The experiments show that worst negative slack (WNS) and total negative slack (TNS) improved up to 13% and 56%, respectively, compared to the baseline flow. Full article

(This article belongs to the Special Issue Hardware and Architecture)

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2333 KiB

Open AccessArticle

Remote System Update for System on Programmable Chip Based on Controller Area Network

by Lei Zhou, Qingxiang Liu, Bangji Wang, Peixin Yang, Xiangqiang Li and Jianqiong Zhang

Electronics 2017, 6(2), 45; https://0-doi-org.brum.beds.ac.uk/10.3390/electronics6020045 - 13 Jun 2017

Cited by 4 | Viewed by 6237

Abstract

In some application domains, using a download cable to update the system on a programmable chip (SoPC) is infeasible, which reduces the maintainability and flexibility of the system. Hence the remote system update (RSU) scheme is being studied. In this scheme, the serial configuration (EPCS) device involves a factory mode configuration image, which acts as the baseline, and an application mode configuration image, which is used for some specific functions. Specifically, a new application mode image is delivered through the controller area network (CAN) with the improved application layer protocol. Besides, the data flow and data check for transmitting a new image are constructed to combine the transmission reliability with efficiency. The boot sequence copying hardware configuration code and software configuration code is analyzed, and the advanced boot loader is carried out to specify boot address of the application mode image manually. Experiments have demonstrated the feasibility of updating and running a new application mode image, as well as rolling back into the factory mode image when no application mode image is available. This scheme applies a single CAN bus, which makes the system easy to construct and suitable for the field distributed control system. Full article

(This article belongs to the Special Issue Hardware and Architecture)

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2236 KiB

Open AccessArticle

Fully-Integrated Converter for Low-Cost and Low-Size Power Supply in Internet-of-Things Applications

by Fernando Gutierrez

Electronics 2017, 6(2), 38; https://0-doi-org.brum.beds.ac.uk/10.3390/electronics6020038 - 17 May 2017

Cited by 10 | Viewed by 6556

Abstract

The paper presents a fully-integrated and universal DC/DC converter to minimize cost and size of power supply systems in wireless nodes for Internet-of-Things (IoT) applications. The proposed converter avoids the use of inductors and is made by a cascade of switching capacitor stages, implementing both step-down and step-up converting ratios, which regulate input sources from 1 V to 60 V to a voltage of about 4 V. Multiple linear regulators are placed at the end of the cascade to provide multiple and stable output voltages for loads such as memories, sensors, processors, wireless transceivers. The multi-output power converter has been integrated in a Bipolar-CMOS-DMOS (BCD) 180 nm technology. As case study, the generation of 3 output voltages has been considered (3 V, 2.7 V, and 1.65 V with load current requirements of 0.3 A, 0.3 A, and 0.12 A, respectively). Thanks to the adoption of a high switching frequency, up to 5 MHz, the only needed passive components are flying capacitors, whose size is below 10 nF, and buffer capacitors, whose size is below 100 nF. These capacitors can be integrated on top of the chip die, creating a 3D structure. This way, the size of the power management unit for IoT and CPS nodes is limited at 18 mm². The proposed converter can also be used with changing input power sources, like power harvesting systems and/or very disturbed power supplies. Full article

(This article belongs to the Special Issue Hardware and Architecture)

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Review

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27 pages, 2776 KiB

Open AccessReview

A Survey on Formal Verification Techniques for Safety-Critical Systems-on-Chip

by Tomás Grimm, Djones Lettnin and Michael Hübner

Electronics 2018, 7(6), 81; https://0-doi-org.brum.beds.ac.uk/10.3390/electronics7060081 - 26 May 2018

Cited by 29 | Viewed by 8609

Abstract

The high degree of miniaturization in the electronics industry has been, for several years, a driver to push embedded systems to different fields and applications. One example is safety-critical systems, where the compactness in the form factor helps to reduce the costs and allows for the implementation of new techniques. The automotive industry is a great example of a safety-critical area with a great rise in the adoption of microelectronics. With it came the creation of the ISO 26262 standard with the goal of guaranteeing a high level of dependability in the designs. Other areas in the safety-critical applications domain have similar standards. However, these standards are mostly guidelines to make sure that designs reach the desired dependability level without explicit instructions. In the end, the success of the design to fulfill the standard is the result of a thorough verification process. Naturally, the goal of any verification team dealing with such important designs is complete coverage as well as standards conformity, but as these are complex hardware, complete functional verification is a difficult task. From the several techniques that exist to verify hardware, where each has its pros and cons, we studied six well-established in academia and in industry. We can divide them into two categories: simulation, which needs extremely large amounts of time, and formal verification, which needs unrealistic amounts of resources. Therefore, we conclude that a hybrid approach offers the best balance between simulation (time) and formal verification (resources). Full article

(This article belongs to the Special Issue Hardware and Architecture)

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