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Millimeter-Wave Integrated Circuits and Systems for 5G Applications
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Millimeter-Wave Integrated Circuits and Systems for 5G Applications

A special issue of Electronics (ISSN 2079-9292). This special issue belongs to the section "Circuit and Signal Processing".

Deadline for manuscript submissions: closed (31 December 2021) | Viewed by 34370

Special Issue Editor

Prof. Dr. Kiat Seng Yeo

E-Mail Website
Guest Editor
1. Engineering Product Development (EPD), Singapore University of Technology and Design, Singapore 487372, Singapore
2. School of Microelectronics, Tianjin University, Tianjin 300072, China
Interests: circuits and systems; low-power integrated circuit design; visible light communications; CMOS technology; RF/mm-wave integrated circuit design; VLSI/ULSI design; memory
Special Issues, Collections and Topics in MDPI journals

Special Issue Information

Dear Colleagues,

Due to the explosive growth of mobile devices and 5G connectivity, wireless transmission at a greater than one gigabit-per-second (Gbps) data rate is becoming essential. As a result, the network infrastructure will be endowed with an unprecedented degree of intelligence, integrating with the environment and offering fast, secure, and reliable communications. Objects like lamp posts, road signs, buildings, vehicles, drones, robots, trains, and watercrafts will be equipped with intelligent devices able to detect electromagnetic signals, perform computations, and store data.

It is extremely challenging to achieve Gbps data rate applications below a 6 GHz band due to spectrum scarcity. Therefore, the millimeter-wave (MMW) band has drawn increasing interest over recent years for enabling ultrahigh-speed wireless transmission. Combining cutting-edge network technology and MMW integrated circuit design, 5G technology offers connections that are multitudes faster than current connections with low latency (1 ms or less) and high speed (>1 Gbps) for massive Internet of Things (IoT), tactile internet, drones, and robotics. It will transform the way we live, play, work, and travel while delivering more performance, efficiency, and comfort. New products, systems, services, business models, and entire industries will be born as 5G technology provides a huge leap forward in speed, capacity, and connectivity. 

The main aim of this Special Issue is to disseminate latest findings, new research developments, and future trends and innovations in MMW integrated circuits and systems for 5G applications. Both theoretical and experimental studies for MMW IC design, architectures, technologies, devices, circuits, and systems are encouraged. Furthermore, high-quality review and survey papers are welcomed.

The papers considered for possible publication may focus on but not necessarily be limited to the following areas:

  • MMW circuits, such as low noise amplifiers, mixers, voltage-controlled oscillators, power amplifiers, variable gain amplifiers, etc.;
  • MMW architectures, systems and subsystems, such as receivers, transmitters, transceivers, phase-locked loops, frequency synthesizers, multistandard transceivers, digital radio, etc.;
  • MMW passive structures such as transformers, hybrid couplers, filters, baluns, switches, antennae, etc.;
  • MMW digital baseband; MMW data converters; wireless communication systems; wideband integrated circuits and systems; low-power and energy-efficient MMW digital systems;
  • Advanced MMW IC; emerging MMW nanoscale CMOS IC; MMW 3D integrations; MMW SiP and SOC.

Prof. Dr. Yeo Kiat Seng
Guest Editor

Manuscript Submission Information

Manuscripts should be submitted online at www.mdpi.com by registering and logging in to this website. Once you are registered, click here to go to the submission form. Manuscripts can be submitted until the deadline. All submissions that pass pre-check are peer-reviewed. Accepted papers will be published continuously in the journal (as soon as accepted) and will be listed together on the special issue website. Research articles, review articles as well as short communications are invited. For planned papers, a title and short abstract (about 100 words) can be sent to the Editorial Office for announcement on this website.

Submitted manuscripts should not have been published previously, nor be under consideration for publication elsewhere (except conference proceedings papers). All manuscripts are thoroughly refereed through a single-blind peer-review process. A guide for authors and other relevant information for submission of manuscripts is available on the Instructions for Authors page. Electronics is an international peer-reviewed open access semimonthly journal published by MDPI.

Please visit the Instructions for Authors page before submitting a manuscript. The Article Processing Charge (APC) for publication in this open access journal is 2400 CHF (Swiss Francs). Submitted papers should be well formatted and use good English. Authors may use MDPI's English editing service prior to publication or during author revisions.

Keywords

  • Millimeter-wave circuits and systems
  • Transceivers
  • Low-power, energy-efficient MMW IC design
  • Wireless communication systems
  • Millimeter-wave digital baseband
  • Advanced MMW IC technologies, SiP and SOC

Published Papers (11 papers)

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Research

15 pages, 4830 KiB  
Article
A Wideband Reconfigurable CMOS VGA Based on an Asymmetric Capacitor Technique with a Low Phase Variation
by Qingfeng Zhang, Chenxi Zhao and Kai Kang
Electronics 2022, 11(5), 751; https://0-doi-org.brum.beds.ac.uk/10.3390/electronics11050751 - 28 Feb 2022
Cited by 1 | Viewed by 2334
Abstract
This paper presents a wideband digitally controlled variable gain amplifier (VGA) with a reconfigurable gain tuning range and gain step in a 65 nm CMOS process. A unique asymmetric capacitor-based reconfigurable technique is proposed to extend the gain tuning range and realize gain [...] Read more.
This paper presents a wideband digitally controlled variable gain amplifier (VGA) with a reconfigurable gain tuning range and gain step in a 65 nm CMOS process. A unique asymmetric capacitor-based reconfigurable technique is proposed to extend the gain tuning range and realize gain step reconfiguration. An active neutralization topology based on a stackless transistor is utilized to compensate for the additional phase shift introduced by the gain tuning. Moreover, a current-type digital-to-analog converter (DAC) is also integrated for easier precise gain control. With the asymmetric capacitor varying from 1000 fF to 200 fF with a step of 400 fF, the proposed VGA achieves a 12.2/9.2/6.1 dB gain tuning range with a 0.4/0.3/0.2 dB gain resolution, respectively. At the maximum gain tuning range mode, the measured minimum root-mean-square (RMS) phase error is 1.7° at 23.4 GHz. At the finest gain step control mode, the RMS phase error measured across 20–30 GHz is lower than 1.9°. The tested result also shows the proposed VGA achieves a peak gain of 13 dB with a 3 dB bandwidth of 21.4–29 GHz, and the output 1 dB compression point (OP1dB) is up to 8.6 dBm at 25 GHz. Full article
(This article belongs to the Special Issue Millimeter-Wave Integrated Circuits and Systems for 5G Applications)
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11 pages, 14271 KiB  
Article
A Wide-Band Divide-by-2 Injection-Locked Frequency Divider Based on Distributed Dual-Resonance Tank
by Zhao Xing, Yiming Yu and Kai Kang
Electronics 2022, 11(4), 506; https://0-doi-org.brum.beds.ac.uk/10.3390/electronics11040506 - 09 Feb 2022
Viewed by 1160
Abstract
A wide-band divide-by-2 injection-locked frequency divider (ILFD) based on a distributed dual-resonance high-order tank is presented. The ILFD employs a distributed LC network as the dual resonance tank and achieves an ultra-wide locking range. Fabricated in a 65 nm 1P7M LP-CMOS process, the [...] Read more.
A wide-band divide-by-2 injection-locked frequency divider (ILFD) based on a distributed dual-resonance high-order tank is presented. The ILFD employs a distributed LC network as the dual resonance tank and achieves an ultra-wide locking range. Fabricated in a 65 nm 1P7M LP-CMOS process, the divide-by-2 ILFD consumes 7 mW from a 0.7 V power supply and realizes a locking range of 87.0%, from 13 GHz to 33 GHz. The core circuit occupies an area of 0.22 mm × 0.5 mm. Full article
(This article belongs to the Special Issue Millimeter-Wave Integrated Circuits and Systems for 5G Applications)
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17 pages, 5210 KiB  
Article
A 48 GHz Fundamental Frequency PLL with Quadrature Clock Generation for 60 GHz Transceiver
by Xiaokang Niu, Xu Wu, Lianming Li, Long He, Depeng Cheng and Dongming Wang
Electronics 2022, 11(3), 415; https://0-doi-org.brum.beds.ac.uk/10.3390/electronics11030415 - 29 Jan 2022
Cited by 4 | Viewed by 2581
Abstract
This paper presents a design of a 48 GHz CMOS phase-locked loop (PLL) for 60 GHz millimeter-wave (mmWave) communication systems. For the sliding intermediate frequency (sliding-IF) transceiver applications, a fundamental frequency PLL with quadrature clock generation scheme is proposed. Specifically, with an implicit [...] Read more.
This paper presents a design of a 48 GHz CMOS phase-locked loop (PLL) for 60 GHz millimeter-wave (mmWave) communication systems. For the sliding intermediate frequency (sliding-IF) transceiver applications, a fundamental frequency PLL with quadrature clock generation scheme is proposed. Specifically, with an implicit capacitive-bridged shunt peaking network, a second order harmonic filtering technique is realized in the voltage control oscillator (VCO) to broaden the bandpass response, thereby avoiding the complex common-mode resonant tank calibration and improving the phase noise performance. A robust current mode logic (CML) static frequency divider topology is adopted to realize the prescaler and to generate the quadrature clock. With the capacitive-bridged shunt peaking load and robust biasing circuit, the static frequency divider locking range and high frequency performance is improved and its reliability is enhanced over the PVT corners. To improve the image suppression ratio of the transceiver, a quadrature clock phase calibration scheme is proposed and verified. Fabricated in a 65 nm CMOS process, the PLL occupies a core area of 800 μm × 950 μm. Over the frequency range of 45.2 to 52.6 GHz, the measured PLL in-band phase noise PLL is better than −90 dBc/Hz@100 KHz offset, and its jitter is less than 155 fs. Moreover, the reference spur is less than −60 dBc/Hz. Full article
(This article belongs to the Special Issue Millimeter-Wave Integrated Circuits and Systems for 5G Applications)
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15 pages, 6565 KiB  
Article
A 17.8–34.8 GHz (64.6%) Locking Range Current-Reuse Injection-Locked Frequency Multiplier with Dual Injection Technique
by Kwang-Il Oh, Goo-Han Ko, Gwang-Sub Kim, Jeong-Geun Kim and Donghyun Baek
Electronics 2021, 10(9), 1122; https://0-doi-org.brum.beds.ac.uk/10.3390/electronics10091122 - 10 May 2021
Cited by 2 | Viewed by 2923
Abstract
A 17.8–34.8 GHz (64.6%) locking range current-reuse injection-locked frequency multiplier (CR-ILFM) with dual injection technique is presented in this paper. A dual injection technique is applied to generate differential signal and increase the power of the second-order harmonic component. The CR core is [...] Read more.
A 17.8–34.8 GHz (64.6%) locking range current-reuse injection-locked frequency multiplier (CR-ILFM) with dual injection technique is presented in this paper. A dual injection technique is applied to generate differential signal and increase the power of the second-order harmonic component. The CR core is proposed to reduce the power consumption and compatibility with NMOS and PMOS injectors. The inductor-capacitor (LC) tank of the proposed CR-ILFM is designed with a fourth-order resonator using a transformer with distributed inductor to extend the locking range. The self-oscillated frequency of the proposed CR-ILFM is 23.82 GHz. The output frequency locking range is 17.8–34.8 GHz (64.6%) at a 0-dBm injection power without any additional control including supply voltage, varactor, and capacitor bank. The power consumption of the proposed CR-ILFM is 7.48 mW from a 1-V supply voltage and the die size is 0.75 mm × 0.45 mm. The CR-ILFM is implemented in a 65-nm CMOS technology. Full article
(This article belongs to the Special Issue Millimeter-Wave Integrated Circuits and Systems for 5G Applications)
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10 pages, 4012 KiB  
Article
Design and Verification of a Charge Pump in Local Oscillator for 5G Applications
by Rui Guo, Zhenghao Lu, Shaogang Hu, Qi Yu, Limei Rong and Yang Liu
Electronics 2021, 10(9), 1009; https://0-doi-org.brum.beds.ac.uk/10.3390/electronics10091009 - 23 Apr 2021
Cited by 3 | Viewed by 2813
Abstract
A charge pump (CP) that has low current mismatch to reduce the locking time of the Phase-Locked Loop (PLL) is proposed. The design is promising in 5G applications with the capabilities of fast settling and low power consumption. In this design, a charge [...] Read more.
A charge pump (CP) that has low current mismatch to reduce the locking time of the Phase-Locked Loop (PLL) is proposed. The design is promising in 5G applications with the capabilities of fast settling and low power consumption. In this design, a charge pump architecture consists of an operational power amplifier (OPA), switches, three D flip-flops (DFFs) and passive devices. A phase error compensation technique is introduced in the charge pump to reduce the locking time. The current mismatch, which is mainly due to the leakage current, is below 1% for a large output voltage headroom of 84% of the supply voltage. An 18.4% reduction in the settling time is realized by the proposed design. Full article
(This article belongs to the Special Issue Millimeter-Wave Integrated Circuits and Systems for 5G Applications)
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7 pages, 1986 KiB  
Article
A Millimeter-Wave CMOS Injection-Locked BPSK Transmitter in 65-nm CMOS
by Jiafu Lin, He Peng, Qichao Yang, Roc Berenguer and Gui Liu
Electronics 2021, 10(5), 598; https://0-doi-org.brum.beds.ac.uk/10.3390/electronics10050598 - 04 Mar 2021
Cited by 1 | Viewed by 1864
Abstract
In order to provide gigabit per second wireless communication, various standards have been proposed and implemented in recent years. Since the millimeter-wave (mm-wave) communication enables uncompressed high-speed data transfer with a minimum delay, it is considered to be the most promising technology to [...] Read more.
In order to provide gigabit per second wireless communication, various standards have been proposed and implemented in recent years. Since the millimeter-wave (mm-wave) communication enables uncompressed high-speed data transfer with a minimum delay, it is considered to be the most promising technology to alleviate the pressure of the increasing demand of the spectrum resource. In this paper, a compact and highly efficient mm-wave transmitter is presented. The proposed injection-locked binary phase-shift keying (BPSK) transmitter can deliver a 10.2 dBm output with an efficiency over 10%. The proposed transmitter occupies 0.105 mm2 chip area in 65 nm CMOS process. Full article
(This article belongs to the Special Issue Millimeter-Wave Integrated Circuits and Systems for 5G Applications)
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12 pages, 30534 KiB  
Article
A Two-Stage X-Band 20.7-dBm Power Amplifier in 40-nm CMOS Technology
by Zhichao Li, Shiheng Yang, Samuel B. S. Lee and Kiat Seng Yeo
Electronics 2020, 9(12), 2198; https://0-doi-org.brum.beds.ac.uk/10.3390/electronics9122198 - 20 Dec 2020
Cited by 3 | Viewed by 3493
Abstract
For higher integration density, X-band power amplifiers (PAs) with CMOS technology have been widely discussed in recent publications. However, with reduced power supply voltage and device size, it is a great challenge to design a compact PA with high output power and power-added [...] Read more.
For higher integration density, X-band power amplifiers (PAs) with CMOS technology have been widely discussed in recent publications. However, with reduced power supply voltage and device size, it is a great challenge to design a compact PA with high output power and power-added efficiency (PAE). In the proposed design, a 40-nm standard CMOS process is used for higher integration with other RF building blocks, compared with other CMOS PA designs with larger process node. Transistor cells are designed with neutralization capacitors to increase stability and gain performance of the PA. As a trade-off among gain, output power, and PAE, the transistor cells in driving stage and power stage are biased for class A and class AB operation, respectively. Both transistor cells consist of two transistors working in differential mode. Furthermore, transformer-based matching networks (TMNs) are used to realize a two-stage X-band CMOS PA with compact size. The PA achieves an effective conductivity (EC) of 117.5, which is among the highest in recently reported X-band PAs in CMOS technology. The PA also attains a saturated output power (Psat) of 20.7 dBm, a peak PAE of 22.4%, and a gain of 25.6 dB at the center frequency of 10 GHz under a 1 V supply in 40-nm CMOS. Full article
(This article belongs to the Special Issue Millimeter-Wave Integrated Circuits and Systems for 5G Applications)
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11 pages, 5184 KiB  
Article
Design of a Ka-Band U-Shaped Bandpass Filter with 20-GHz Bandwidth in 0.13-μm BiCMOS Technology
by Kai Men, Hang Liu and Kiat Seng Yeo
Electronics 2020, 9(10), 1608; https://0-doi-org.brum.beds.ac.uk/10.3390/electronics9101608 - 01 Oct 2020
Cited by 3 | Viewed by 2387
Abstract
In this work, the design of a novel Ka-band miniaturized bandpass filter with broad bandwidth is demonstrated by using inversely coupled U-shaped transmission lines. In the proposed filter, two transmission zeros can be generated within a cascaded U-shaped structure and it can also [...] Read more.
In this work, the design of a novel Ka-band miniaturized bandpass filter with broad bandwidth is demonstrated by using inversely coupled U-shaped transmission lines. In the proposed filter, two transmission zeros can be generated within a cascaded U-shaped structure and it can also be proven that, by inversely coupling two stacked U-shaped transmission lines, the notch frequency at the upper stopband can be shifted to a lower frequency, which results in a smaller chip size. The key parameters affecting the performance of the proposed filter are investigated in detail with the effective lumped-element circuit illustrated. Fabricated in a 0.13-μm SiGe BiCMOS process, the proposed filter achieves an insertion loss of 3.6 dB at a frequency of 28.75 GHz and the measured bandwidth is from 20.75 GHz to 41 GHz. The return loss is better than −10 dB from 20.5 GHz to 39 GHz. The lower transmission zero is located at 11.75 GHz with a suppression of 54 dB while the upper transmission zero is around 67 GHz with an attenuation of 34.6 dB. The measurement agrees very well with the simulation results and the overall chip size of the proposed filter is 176 × 269 μm2. Full article
(This article belongs to the Special Issue Millimeter-Wave Integrated Circuits and Systems for 5G Applications)
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9 pages, 3050 KiB  
Article
Ka-Band Marchand Balun with Edge- and Broadside-Coupled Hybrid Configuration
by Jinna Yan, Hang Liu, Xi Zhu, Kai Men and Kiat Seng Yeo
Electronics 2020, 9(7), 1116; https://0-doi-org.brum.beds.ac.uk/10.3390/electronics9071116 - 09 Jul 2020
Cited by 5 | Viewed by 6312
Abstract
This article presents a novel Ka-band Marchand balun implemented in 0.13-μm SiGe bipolar complementary metal–oxide–semiconductor (BiCMOS) process. By combining both edge- and broadside-coupled structures, the new hybrid balun is able to increase the coupling and minimize the balun insertion loss. As compared with [...] Read more.
This article presents a novel Ka-band Marchand balun implemented in 0.13-μm SiGe bipolar complementary metal–oxide–semiconductor (BiCMOS) process. By combining both edge- and broadside-coupled structures, the new hybrid balun is able to increase the coupling and minimize the balun insertion loss. As compared with conventional edge-coupled or broadside-coupled structures, the proposed balun achieves the lowest insertion loss of 1.02 dB across a wide 1-dB bandwidth from 29.0 GHz to 46.0 GHz, with a core size of 270 μm × 280 μm. Full article
(This article belongs to the Special Issue Millimeter-Wave Integrated Circuits and Systems for 5G Applications)
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16 pages, 6647 KiB  
Article
Design of Differential Variable-Gain Transimpedance Amplifier in 0.18 µm SiGe BiCMOS
by Samuel B.S. Lee, Hang Liu, Kiat Seng Yeo, Jer-Ming Chen and Xiaopeng Yu
Electronics 2020, 9(7), 1058; https://0-doi-org.brum.beds.ac.uk/10.3390/electronics9071058 - 27 Jun 2020
Cited by 5 | Viewed by 3309
Abstract
This paper presents two new inductorless differential variable-gain transimpedance amplifiers (DVGTIA) with voltage bias controlled variable gain designed in TowerJazz’s 0.18 µm SiGe BiCMOS technology (using CMOS transistors only). Both consist of a modified differential cross-coupled regulated cascode preamplifier stage and a cascaded [...] Read more.
This paper presents two new inductorless differential variable-gain transimpedance amplifiers (DVGTIA) with voltage bias controlled variable gain designed in TowerJazz’s 0.18 µm SiGe BiCMOS technology (using CMOS transistors only). Both consist of a modified differential cross-coupled regulated cascode preamplifier stage and a cascaded amplifier stage with bias-controlled gain-variation and third-order interleaving feedback. The designs have wide measured transimpedance gain ranges of 24.5–60.6 dBΩ and 27.8–62.8 dBΩ with bandwidth above 6.42 GHz and 5.22 GHz for DVGTIA designs 1 and 2 respectively. The core power consumptions are 30.7 mW and 27.5 mW from a 1.8 V supply and the input referred noise currents are 10.3 pA/√Hz and 21.7 pA/√Hz. The DVGTIA designs 1 and 2 have a dynamic range of 40.4 µA to 3 mA and 76.8 µA to 2.7 mA making both suitable for real photodetectors with an on-chip photodetector capacitive load of 250 fF. Both designs are compact with a core area of 100 µm × 85 µm. Full article
(This article belongs to the Special Issue Millimeter-Wave Integrated Circuits and Systems for 5G Applications)
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13 pages, 2684 KiB  
Article
A Compact Broadband Monolithic Sub-Harmonic Mixer Using Multi-Line Coupler
by Jincai Wen, Shengzhou Zhang and Lingling Sun
Electronics 2020, 9(4), 694; https://0-doi-org.brum.beds.ac.uk/10.3390/electronics9040694 - 24 Apr 2020
Cited by 3 | Viewed by 3054
Abstract
A compact broadband monolithic sub-harmonic mixer is presented in a 70 nm GaAs Technology for millimeter wave wireless communication application. The proposed mixer adopts a novel multi-line coupler structure; where the two-sided coupling energy of radio frequency (RF) and local oscillation (LO) signals [...] Read more.
A compact broadband monolithic sub-harmonic mixer is presented in a 70 nm GaAs Technology for millimeter wave wireless communication application. The proposed mixer adopts a novel multi-line coupler structure; where the two-sided coupling energy of radio frequency (RF) and local oscillation (LO) signals are both collected and efficiently feed to anti-parallel diode pair (APDP) topology; resulting in broadband performance and compact chip size. As a comparison in the same circuit configuration; the five-line coupler can expand the bandwidth of the existing three-line coupler by 85% and reduce the area by 39.5% when the central frequency is 127 GHz. The measured conversion gain is −16.2 dB to −19.7 dB in a wide operation frequency band of 110–170 GHz. The whole chip size is 0.47 × 0.66 mm2 including test pads. The proposed mixer exhibits good figure-of-merits for D-band down-converter applications Full article
(This article belongs to the Special Issue Millimeter-Wave Integrated Circuits and Systems for 5G Applications)
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