VLSI Implementation of Neural Networks

A special issue of Electronics (ISSN 2079-9292). This special issue belongs to the section "Networks".

Deadline for manuscript submissions: closed (31 March 2022) | Viewed by 2889

Special Issue Editors


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Guest Editor
Department of Computer and Electrical Engineering and Computer Science, Florida Atlantic University, Boca Raton, FL 33431, USA
Interests: neural network algorithms; VLSI implementation of neural networks; low power CMOS circuit design; digital circuit design; layout and verification
ADT Security Services, Inc., Boca Raton, FL 33431, USA
Interests: VLSI implementation of neural networks; low power CMOS circuit design; digital circuit design; layout and verification; RF and microwave; EMI and EMC structure
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Special Issue Information

Dear Colleagues,

This Special Issue on neural networks provides a forum for developing and nurturing an international community of scholars and practitioners who are interested in all aspects of neural networks and related approaches to computational intelligence. This uniquely broad range facilitates the cross-fertilization of ideas between biological and technological studies, and helps to foster the development of the interdisciplinary community that is interested in biologically-inspired computational intelligence. Accordingly, the “VLSI Implementation of Neural Networks” Guest Editor board represents experts in fields including psychology, neurobiology, computer science, engineering, mathematics, and physics. 

The aim of this Special Issue of Electronics is to present state-of-the-art investigations in various VLSI Implementation of Neural Networks technologies for future applications. We invite researchers to contribute original and unique articles, as well as sophisticated review articles. Topics include, but not limited to, the following areas:

  • Cognitive Science
  • Micro Controllers Parallel Processing
  • Neuroscience
  • Learning Systems
  • Mathematical and Computational Analysis
  • Engineering and Applications
  • Algorithms for VLSI Design Automation
  • Advanced Computer Architecture
  • Advanced CPLD-Based Design
  • Advanced FPGA-Based Design
  • Analog VLSI Design
  • Analog& Digital IC Design
  • Asynchronous System Design
  • Advanced Digital Design
  • Analysis and Design of Digital Systems using VHDL
  • Advanced Computer Architecture
  • Advanced Computational Methods
  • Computational Methods for VLSI
  • CMOS RF Circuit Design
  • Computer-Aided VLSI Design
  • Cryptology and Crypto Chip Design
  • Digital System Design
  • Digital Signal Processing Structures for VLSI
  • Digital Image Processing for VLSI
  • Data Structure & Algorithm Analysis
  • Design of VLSI System
  • Digital Logic with Verilog
  • Embedded Systems: High-Level Synthesis for VLSI Systems
  • Electronic Design Automation Tools
  • Electronic Packaging
  • Functional and Formal Verification
  • HDL Modelling
  • Hardware-Software Co-design
  • HDL Languages used for VLSI: Verilog & VHDL
  • Low Power VLSI Design
  • Modelling and Synthesis with Verilog HDLMOS Circuit Design
  • Mixed-Signal Circuit Design
  • MEMS and IC Integration
  • Nano Technology
  • Process, Devices & Circuit Simulation
  • RF & Bio MEMS
  • Thermal Design of Electronic Equipment
  • Solid State Electronics Devices
  • System on Programmable Chip Design
  • Simulation, Synthesis & Verification of Integrated Circuits and Systems
  • VLSI System Testing
  • VLSI Process Technology
  • VLSI Test & Testability
  • VLSI Architectures, Algorithms, Methods & Tools for Modelling

Prof. Dr. Abhijit Pandya
Dr. Riki Patel
Guest Editors

Manuscript Submission Information

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Submitted manuscripts should not have been published previously, nor be under consideration for publication elsewhere (except conference proceedings papers). All manuscripts are thoroughly refereed through a single-blind peer-review process. A guide for authors and other relevant information for submission of manuscripts is available on the Instructions for Authors page. Electronics is an international peer-reviewed open access semimonthly journal published by MDPI.

Please visit the Instructions for Authors page before submitting a manuscript. The Article Processing Charge (APC) for publication in this open access journal is 2400 CHF (Swiss Francs). Submitted papers should be well formatted and use good English. Authors may use MDPI's English editing service prior to publication or during author revisions.

Keywords

  • Very large scale integration
  • Neural networks
  • Computer networks
  • Integrated circuit interconnections
  • Circuit testing
  • Optical computing
  • Optical interconnections
  • Optical network units Optical fiber networks Biological system modeling

Published Papers (1 paper)

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Research

18 pages, 921 KiB  
Article
A Multi-Cache System for On-Chip Memory Optimization in FPGA-Based CNN Accelerators
by Tommaso Pacini, Emilio Rapuano, Gianmarco Dinelli and Luca Fanucci
Electronics 2021, 10(20), 2514; https://0-doi-org.brum.beds.ac.uk/10.3390/electronics10202514 - 15 Oct 2021
Cited by 2 | Viewed by 2093
Abstract
In recent years, FPGAs have demonstrated remarkable performance and contained power consumption for the on-the-edge inference of Convolutional Neural Networks. One of the main challenges in implementing this class of algorithms on board an FPGA is resource management, especially with regard to memory. [...] Read more.
In recent years, FPGAs have demonstrated remarkable performance and contained power consumption for the on-the-edge inference of Convolutional Neural Networks. One of the main challenges in implementing this class of algorithms on board an FPGA is resource management, especially with regard to memory. This work presents a multi-cache system that allows for noticeably shrinking the required on-chip memory with a negligible variation of timing performance and power consumption. The presented methods have been applied to the CloudScout CNN, which was developed to perform cloud detection directly on board the satellite, thus representing a relevant case study for on the edge applications. The system was validated and characterized on a Xilinx ZCU106 Evaluation Board. The result is a 64.48% memory saving if compared to an alternative hardware accelerator developed for the same algorithm, with comparable performance in terms of inference time and power consumption. The paper also presents a detailed analysis of the hardware accelerator power consumption, focusing on the impact of data transfer between the accelerator and the external memory. Further investigation shows that the proposed strategies allow the implementation of the accelerator on FPGAs with a smaller size, guaranteeing benefits in terms of power consumption and hardware costs. A broader evaluation about the applicability of the presented methods to other models demonstrates valuable results in terms of memory saving with respect to other works reported in the literature. Full article
(This article belongs to the Special Issue VLSI Implementation of Neural Networks)
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