Research

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22 pages, 14923 KiB

Open AccessFeature PaperArticle

A Novel Automated Design Methodology for Power Electronics Converters

by André Andreta, Luiz Fernando Lavado Villa, Yves Lembeye and Jean Christophe Crebier

Electronics 2021, 10(3), 271; https://0-doi-org.brum.beds.ac.uk/10.3390/electronics10030271 - 23 Jan 2021

Cited by 10 | Viewed by 2299

This work proposes a methodology for designing power electronic converters called “Automatic Design for Manufacturing” (ADFM). This methodology proposes creating Power Converter Arrays (PCAs) using standardized converter cells. The approach is greatly inspired by the microelectronics integrated circuit design flow, power electronics building [...] Read more.

This work proposes a methodology for designing power electronic converters called “Automatic Design for Manufacturing” (ADFM). This methodology proposes creating Power Converter Arrays (PCAs) using standardized converter cells. The approach is greatly inspired by the microelectronics integrated circuit design flow, power electronics building blocks, and multicell converters. To achieve the desired voltage/current specifications, the PCA conversion stage is made from the assembly of several Conversion-Standard Cells (CSCs) in series and/or parallel. The ADFM uses data-based models to simulate the behavior of a PCA with very little computational effort. These models require a special characterization approach to maximize the amount of knowledge while minimizing the amount of data. This approach consists of establishing an experiment plan to select the relevant measurements that contain the most information about the PCA technology, building an experimental setup that is capable of acquiring data automatically and using statistical learning to train models that can yield precise predictions. This work performed over 210 h of tests in nine different PCAs in order to gather data to the statistical models. The models predict the efficiency and converter temperature of several PCAs, and the accuracy is compared with real measurements. Finally, the models are employed to compare the performance of PCAs in a specific battery charging application. Full article

(This article belongs to the Special Issue Multilevel Converters)

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19 pages, 2708 KiB

Open AccessArticle

Four-Level Quasi-Nested Inverter Topology for Single-Phase Applications

by Carlos A. Reusser and Hector Young

Electronics 2021, 10(3), 233; https://0-doi-org.brum.beds.ac.uk/10.3390/electronics10030233 - 20 Jan 2021

Cited by 2 | Viewed by 2614

Abstract

In this paper, a novel four-level single-phase multilevel converter is introduced, consisting of six active switches arranged in a quasi-nested configuration. The proposed topology synthesizes its output voltage levels with respect to a floating neutral point, using four cascaded capacitors with identical voltage [...] Read more.

In this paper, a novel four-level single-phase multilevel converter is introduced, consisting of six active switches arranged in a quasi-nested configuration. The proposed topology synthesizes its output voltage levels with respect to a floating neutral point, using four cascaded capacitors with identical voltage levels. The proposed converter contains a reduced number of components compared to the neutral point clamped (NPC) or active-NPC topologies (ANPC) for the same number of output voltage levels, since it does not require diode or active switch clamping to a neutral point. Moreover, no floating capacitors with asymmetric voltage levels are employed, thereby simplifying the capacitor voltage balancing. The switching operation principles, modulation technique and control scheme for supplying a single-phase resistive-inductive load are addressed in detail. The proposed four-level inverter allows generating an additional output voltage level with the same semiconductor count as conventional three-level inverters such as NPC and ANPC which allows a superior waveform quality, with a THD

_{v}

reduction of

32.69 %

in comparison the clamped inverters. Experimental tests carried out in a laboratory-scale setup verify the feasibility of the proposed topology. Full article

(This article belongs to the Special Issue Multilevel Converters)

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19 pages, 4289 KiB

Open AccessArticle

Analysis of Cross-Connected Half-Bridges Multilevel Inverter for STATCOM Application

by Yuan Li and Muhammad Humayun

Electronics 2020, 9(11), 1898; https://0-doi-org.brum.beds.ac.uk/10.3390/electronics9111898 - 12 Nov 2020

Cited by 6 | Viewed by 1848

Abstract

This paper suggested a single-phase cross-connected half-bridges multilevel inverter (cchb-mli) topology for static synchronous compensator (statcom) applications. The proposed mli structure consists of cross-connected multilevel cells connected in series with a more optimized number of devices to synthesize a [...] Read more.

This paper suggested a single-phase cross-connected half-bridges multilevel inverter (cchb-mli) topology for static synchronous compensator (statcom) applications. The proposed mli structure consists of cross-connected multilevel cells connected in series with a more optimized number of devices to synthesize a higher number of voltage steps. Each cell in the structure consists of a set of switches and a dc-capacitor. Typically, when several dc-capacitors are used in an inverter, the dc voltages fluctuation occurs due to tolerance between passive element and asymmetric switch losses. A dual-loop control technique has been proposed with level-shifted pulse width modulation pwm to overcome these issues. The proposed methodology balances the dc-voltages using a proportional-integral controller by adjusting the switch duty cycle. The control method helps offset the issue of aggravated fluctuation while preserving the delivered reactive power distributed equally among the dc-capacitors at the same time. A thorough comparison is made between the proposed inverter concerning the number of components and efficiency to demonstrate the effectiveness of previous topologies. Moreover, a simulation model built in simulink and experimental results take from laboratory prototype to confirm the effectiveness of proposed structure and its control technique. Full article

(This article belongs to the Special Issue Multilevel Converters)

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17 pages, 9047 KiB

Open AccessFeature PaperEditor’s ChoiceArticle

Analysis of the Multi-Steps Package (MSP) for Series-Connected SiC-MOSFETs

by Luciano F. S. Alves, Pierre Lefranc, Pierre-Olivier Jeannin, Benoit Sarrazin and Jean-Christophe Crebier

Electronics 2020, 9(9), 1341; https://0-doi-org.brum.beds.ac.uk/10.3390/electronics9091341 - 19 Aug 2020

Cited by 4 | Viewed by 2724

Abstract

In this paper, a multi-step packaging (MSP) concept for series-connected SiC-MOSFETs is analyzed. The parasitic capacitance generated by the dielectric isolation of each device in the stack has a significant impact on the dynamic behavior of SiC devices, which impacts the voltage-sharing performances. [...] Read more.

In this paper, a multi-step packaging (MSP) concept for series-connected SiC-MOSFETs is analyzed. The parasitic capacitance generated by the dielectric isolation of each device in the stack has a significant impact on the dynamic behavior of SiC devices, which impacts the voltage-sharing performances. The study performed in this work reveals that the parasitic capacitance network introduced by the classical planar packaging unbalances the voltage across the series-connected SiC-MOSFETs. Therefore, a new drain-source parasitic capacitance network configuration provided by the MSP is proposed in order to improve the voltage balancing across the series-connected devices. The concept is introduced and analyzed thanks to equivalent models and time domain simulations. To verify the analysis, the voltage sharing between four series-connected 1.2 kV SiC MOSFETs is tested in a double pulse test setup. The experimental results confirm that the MSP has a better performance than the classical one in terms of voltage sharing. Furthermore, the proposed investigation shows that the MSP increases the middle point dv/dt of the switching cell. Sensitive analysis and thermal management considerations are also discussed in order to clarify the MSP limitations and indicate the ways to optimize the MSP from a thermal point of view. Full article

(This article belongs to the Special Issue Multilevel Converters)

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10 pages, 3191 KiB

Open AccessArticle

Voltage Space Vector Equivalent Substitution Fault-Tolerance Control for Cascaded H-Bridge Multilevel Inverter with Current-Tracking

by Guohua Li, Chunwu Liu and Yufeng Wang

Electronics 2020, 9(1), 93; https://0-doi-org.brum.beds.ac.uk/10.3390/electronics9010093 - 02 Jan 2020

Cited by 7 | Viewed by 2977

Abstract

A novel fault-tolerant control method based on the equivalent substitution of voltage space vector for cascaded H-bridge multilevel inverter with current-tracking is proposed in this paper. With this method, the fault effects on the voltage vector of each sector of the cascaded inverter [...] Read more.

A novel fault-tolerant control method based on the equivalent substitution of voltage space vector for cascaded H-bridge multilevel inverter with current-tracking is proposed in this paper. With this method, the fault effects on the voltage vector of each sector of the cascaded inverter is analyzed first. Then, an algorithm to substitute the voltage vector in fault state is developed. In the fault state, if the voltage vector selected by the original algorithm cannot be used normally, the redundant voltage vector with the position coincidence is preferentially selected for equivalent substitution. If there is no redundant coincidence vector, select the other vector whose position and effect are closest to it. Compared with the commonly used N + 1 redundancy method, this method does not require the spare cascaded units and can be applied to any class cascaded H-bridge multilevel inverter with current-tracking to improve its reliability. Finally, the effectiveness of the proposed method is validated by simulation and experiment results. Full article

(This article belongs to the Special Issue Multilevel Converters)

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19 pages, 9486 KiB

Open AccessArticle

Pure Sinusoidal Output Single-Phase Current-Source Inverter with Minimized Switching Losses and Reduced Output Filter Size

by Eka Rakhman Priandana and Toshihiko Noguchi

Electronics 2019, 8(12), 1556; https://0-doi-org.brum.beds.ac.uk/10.3390/electronics8121556 - 17 Dec 2019

Cited by 5 | Viewed by 3736

Abstract

This paper proposes a novel single-phase current-source inverter that generates a pure sinusoidal waveform with minimized switching losses and using a small-size output filter capacitor. The proposed method is investigated by incorporating a conventional multilevel current-source inverter with a linear amplifier. The conventional [...] Read more.

This paper proposes a novel single-phase current-source inverter that generates a pure sinusoidal waveform with minimized switching losses and using a small-size output filter capacitor. The proposed method is investigated by incorporating a conventional multilevel current-source inverter with a linear amplifier. The conventional multilevel technique uses fundamental switching frequency instead of using high-switching frequency modulation for the H-bridge circuit. The linear amplifier such as class-A or class-D types has a function to reform the staircase waveform generated by the multilevel inverter into a pure sinusoidal by using superimposition technique. As a result, pure sinusoidal output current is generated with a small ripple and the system only requires a small output filter capacitor for smoothing the waveform. Based on the simulation and experimental results, the proposed system presents not only the optimal configuration, but also an option as to whether to obtain excellent power efficiency or very low output harmonic. Implications of the results and future research directions are also presented. Full article

(This article belongs to the Special Issue Multilevel Converters)

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13 pages, 7296 KiB

Open AccessArticle

Improved Synchronized Space Vector PWM Strategy for Three-Level Inverter at Low Modulation Index

by Xin Gu, Bingxu Wei, Guozheng Zhang, Zhiqiang Wang and Wei Chen

Electronics 2019, 8(12), 1400; https://0-doi-org.brum.beds.ac.uk/10.3390/electronics8121400 - 23 Nov 2019

Cited by 4 | Viewed by 3332

Abstract

Aimed at reducing the switching loss and common-mode voltage amplitude of high-power medium-voltage three-level inverter under low modulation index conditions, an improved synchronous space vector PWM strategy is proposed in this paper. The switching times in each fundamental period are reduced by the [...] Read more.

Aimed at reducing the switching loss and common-mode voltage amplitude of high-power medium-voltage three-level inverter under low modulation index conditions, an improved synchronous space vector PWM strategy is proposed in this paper. The switching times in each fundamental period are reduced by the re-division of small regions and the full use of the redundant switching state. The sum of switching algebra is introduced as an evaluation index and the switching state with the minimum value of the sum of switching algebra are adopted. Then, the common mode voltage amplitude is reduced. The theoretical analysis and experimental results show that the improved modulation strategy proposed in this paper can effectively reduce the switching loss and common-mode voltage amplitude of the inverter under the condition of the low modulation index. Moreover, the neutral-point voltage ripple is also reduced simultaneously. Full article

(This article belongs to the Special Issue Multilevel Converters)

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Review

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33 pages, 18710 KiB

Open AccessFeature PaperEditor’s ChoiceReview

An Extensive Review of Multilevel Inverters Based on Their Multifaceted Structural Configuration, Triggering Methods and Applications

by Suvetha Poyyamani Sunddararaj, Shriram Srinivasarangan Rangarajan and Subashini N

Electronics 2020, 9(3), 433; https://0-doi-org.brum.beds.ac.uk/10.3390/electronics9030433 - 05 Mar 2020

Cited by 43 | Viewed by 6774

Abstract

Power electronic converters are used to transform one form of energy to another. They are classified into four types depending upon the nature of the input and output voltages. The inverter is one among those types; it converts direct electrical current into alternating [...] Read more.

Power electronic converters are used to transform one form of energy to another. They are classified into four types depending upon the nature of the input and output voltages. The inverter is one among those types; it converts direct electrical current into alternating electrical current at desired frequency. Conventional types of inverters are capable of producing voltage at the output terminal that can only switch between two levels. The range of output voltage generated at the output is low when they are used for high power applications. To improve the voltage profile and efficiency of the overall system, multilevel inverters (MLIs) are introduced. In multilevel inverters the voltage at the output terminal is generated from several DC voltage levels fed at its input. The generated output is more appropriate to a sine wave and the dv/dt rating is also less leading to the reduction in EMI. Though they possess many advantages compared to the conventional inverters, the structural complexity and triggering techniques involved in designing multilevel inverters are high. Many studies are being carried out in defining new topologies of MLI with reduced switch as well as with the implementation of different PWM techniques. This paper will provide an extensive review on variety of MLI configurations based on the parameters such as the number of switches, switching techniques, symmetric, asymmetric, hybrid topologies, configurations based on applications, THD and power quality. Full article

(This article belongs to the Special Issue Multilevel Converters)

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