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Electronics
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Reliability Assessment and Modeling of Optical and Semiconductor Devices
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Reliability Assessment and Modeling of Optical and Semiconductor Devices

A special issue of Electronics (ISSN 2079-9292). This special issue belongs to the section "Semiconductor Devices".

Deadline for manuscript submissions: closed (1 March 2022) | Viewed by 26081

Special Issue Editors

Prof. Dr. Ilgu Yun

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Guest Editor
Department of Electrical and Electronic Engineering, Yonsei University, Shinchon Campus, Seoul 03722, Korea
Interests: reliability assessment and modeling of optical and semiconductor devices; modeling and simulation of semiconductor devices using TCAD; compact modeling for semiconductor devices for process development kit (PDK); semiconductor process/equipment diagnosis; monitoring and modeling of semiconductor processes and devices for intelligent manufacturing
Dr. Soon Il Jung

E-Mail Website
Guest Editor
Process Development Team, Mobile Display Business, Samsung Display Corporation, Yongin 17113, Korea
Interests: characterization and modeling of quantum dot (QD) LDs and LEDs; reliability assessment and modeling of optical devices; instrumentation and measurements of optical characteristics for QD devices
Dr. Chang Eun Kim

E-Mail Website
Guest Editor
Material Research Team 1, LG Display, Seoul 150-721, Korea
Interests: material design and characterization for electrical and optical devices; modeling and simulation of semiconductor devices using TCAD; device physics and process development for thin film transistors; material development using artificial intelligence
Dr. Edward Namkyu Cho

E-Mail Website
Guest Editor
Semiconductor R&D Center, Samsung Electronics, Hwaseong 445906, Korea
Interests: process and device engineering of semiconductor devices; physics on electronics and semiconductors; modeling and simulation of semiconductor devices

Special Issue Information

Dear Colleagues,

This Special Issue will focus on recent developments in research in optical and semiconductor device reliability, such as reliability assessment, testing, modeling, and failure analysis, for optical and semiconductor devices, including optical sources (LD, LED, VCSEL, etc.), optical detectors (PD, APD, etc.), thin-film transistors (TFT), memory devices (MOSFET, JFET, Flash devices, etc.), and power devices (IGBT, LDMOS, VMOS, etc.). These devices are the key components of either optoelectronic or electronic commercial products, which should exhibit high reliability (or quality) to meet the customer satisfaction. In addition, the goal of this Special Issue is to focus on cross-fertilized communication in the state of the art of reliability of optical and semiconductor devices and provide fundamental understanding of basic phenomena that affect reliability. 

Potential authors are welcome to submit their original research papers and review papers on, but not limited to, the following topics: 

Reliability assessment and testing of optoelectronic semiconductor devices (LD, LED, PD, etc.);

Reliability assessment and testing of electronic semiconductor devices (TFT, FET, IGBT, etc.);

Reliability modeling and simulation of optoelectronic semiconductor devices;

Reliability modeling and simulation of electronic semiconductor devices;

Reliability methodology and prediction of optoelectronic semiconductor devices;

Reliability methodology and prediction of electronic semiconductor devices;

Failure analysis of optoelectronic semiconductor devices;

Failure analysis of electronic semiconductor devices.

Prof. Dr. Ilgu Yun
Dr. Soon Il Jung
Dr. Chang Eun Kim
Dr. Edward Namkyu Cho
Guest Editors

Manuscript Submission Information

Manuscripts should be submitted online at www.mdpi.com by registering and logging in to this website. Once you are registered, click here to go to the submission form. Manuscripts can be submitted until the deadline. All submissions that pass pre-check are peer-reviewed. Accepted papers will be published continuously in the journal (as soon as accepted) and will be listed together on the special issue website. Research articles, review articles as well as short communications are invited. For planned papers, a title and short abstract (about 100 words) can be sent to the Editorial Office for announcement on this website.

Submitted manuscripts should not have been published previously, nor be under consideration for publication elsewhere (except conference proceedings papers). All manuscripts are thoroughly refereed through a single-blind peer-review process. A guide for authors and other relevant information for submission of manuscripts is available on the Instructions for Authors page. Electronics is an international peer-reviewed open access semimonthly journal published by MDPI.

Please visit the Instructions for Authors page before submitting a manuscript. The Article Processing Charge (APC) for publication in this open access journal is 2400 CHF (Swiss Francs). Submitted papers should be well formatted and use good English. Authors may use MDPI's English editing service prior to publication or during author revisions.

Keywords

  • Reliability assessment
  • Reliability testing
  • reliability modeling and simulation
  • Reliability methodology and prediction
  • Failure analysis
  • Optoelectronic semiconductor devices
  • Electronic semiconductor devices.

Published Papers (9 papers)

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12 pages, 5410 KiB  
Article
Evaluation of the Long-Term Reliability of Open-Tube Diffused Planar InGaAs/InP Avalanche Photodiodes under a Hybrid of Thermal and Electrical Stresses
by Hyejeong Choi, Chan-Yong Park, Soo-Hyun Baek, Gap Yeal Moon and Ilgu Yun
Electronics 2022, 11(5), 802; https://0-doi-org.brum.beds.ac.uk/10.3390/electronics11050802 - 04 Mar 2022
Cited by 3 | Viewed by 2602
Abstract
The long-term reliability of open-tube diffused planar InGaAs/InP APDs was investigated via accelerated life testing in this study. For the proposed life testing scheme, both thermal and electrical stresses were applied simultaneously to reduce the testing periods while maintaining statistical significance. Additionally, the [...] Read more.
The long-term reliability of open-tube diffused planar InGaAs/InP APDs was investigated via accelerated life testing in this study. For the proposed life testing scheme, both thermal and electrical stresses were applied simultaneously to reduce the testing periods while maintaining statistical significance. Additionally, the Eyring model was used to extrapolate the activation energy. To determine the optimum life testing conditions, high-temperature storage tests, preliminary accelerated life tests, and main accelerated life tests were conducted. From the test results, the mean-time-to-failure was utilized to verify the suitability of the Eyring model. The proposed testing scheme, which utilizes a hybrid of accelerated stress factors, allows us to estimate the device reliability within an acceptable testing period, minimizing the time to market. Full article
(This article belongs to the Special Issue Reliability Assessment and Modeling of Optical and Semiconductor Devices)
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16 pages, 5879 KiB  
Article
Failure Analysis of Some Commercial Spotlights Based on Light Emitting Diodes
by Wei Zhong and Thomas Walther
Electronics 2022, 11(1), 48; https://0-doi-org.brum.beds.ac.uk/10.3390/electronics11010048 - 24 Dec 2021
Cited by 1 | Viewed by 2508
Abstract
The failure mechanism of two commercial light-emitting diode (LED)-based spotlights with GU10 form factor is analyzed. Through component testing and comparison to nominal values as well as to simulations, it is found that the cause of both device failures is related to damaged [...] Read more.
The failure mechanism of two commercial light-emitting diode (LED)-based spotlights with GU10 form factor is analyzed. Through component testing and comparison to nominal values as well as to simulations, it is found that the cause of both device failures is related to damaged components within the drive circuits rather than the LEDs themselves. Both LED heads work as normal when connected to an external direct current (DC) source. The results show that the lack of light output of one spotlight is related to the open circuit caused by damaged resistors and inductors in its drive circuit, while the flickering of the other is related to the malfunction of the integrated circuit providing constant current output. Therefore, improving the quality of the LED drive circuits is considered the most effective way for manufacturers to reduce catastrophic failures of LED spotlights. Full article
(This article belongs to the Special Issue Reliability Assessment and Modeling of Optical and Semiconductor Devices)
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15 pages, 4975 KiB  
Article
Numerical Model of Current Flow and Thermal Phenomena in Lateral GaN/InGaN LEDs
by Zbigniew Lisik, Ewa Raj and Jacek Podgórski
Electronics 2021, 10(24), 3127; https://0-doi-org.brum.beds.ac.uk/10.3390/electronics10243127 - 16 Dec 2021
Cited by 2 | Viewed by 1999
Abstract
GaN-based light-emitting diodes (LEDs) became one of the most widely used light sources. One of their key factors is power conversion efficiency; hence, a lot of effort is placed on research to improve this parameter, either experimentally or numerically. Standard approaches involve device-oriented [...] Read more.
GaN-based light-emitting diodes (LEDs) became one of the most widely used light sources. One of their key factors is power conversion efficiency; hence, a lot of effort is placed on research to improve this parameter, either experimentally or numerically. Standard approaches involve device-oriented or system-oriented methods. Combining them is possible only with the aid of compact, lumped parameter models. In the paper, we present a new electro-thermal model that covers all the complex opto-electro-thermal phenomena occurring within the operating LED. It is a simple and low computational cost solution that can be integrated with package- or system-oriented numerical analysis. It allows a parametric analysis of the diode structure and properties under steady-state operating conditions. Its usefulness has been proved by conducting simulations of a sample lateral GaN/InGaN LED with the aid of ANSYS software. The results presented illustrate the current density and temperature fields. They allow the identification of ‘hot spots’ resulting from the current crowding effect and can be used to optimise the structure. Full article
(This article belongs to the Special Issue Reliability Assessment and Modeling of Optical and Semiconductor Devices)
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13 pages, 5841 KiB  
Article
An Anti-Interference Online Monitoring Method for IGBT Bond Wire Aging
by Chuankun Wang, Yigang He, Yunfeng Jiang and Lie Li
Electronics 2021, 10(12), 1449; https://0-doi-org.brum.beds.ac.uk/10.3390/electronics10121449 - 17 Jun 2021
Cited by 3 | Viewed by 2124
Abstract
Due to the constant changes of the environment and load, the insulated-gate bipolar transistor (IGBT) module is subjected to a large amount of junction temperature (Tj) fluctuations, which often leads to damage to the bond wires. The monitoring parameters of [...] Read more.
Due to the constant changes of the environment and load, the insulated-gate bipolar transistor (IGBT) module is subjected to a large amount of junction temperature (Tj) fluctuations, which often leads to damage to the bond wires. The monitoring parameters of IGBTs are often coupled with Tj, which increases the difficulty of monitoring IGBTs’ health status online. In this paper, based on the collector current (Ic) and collector-emitter on-state voltage (Vce_on) online monitoring circuit, an online monitoring method of IGBT bond wire aging against interference is proposed. First, the bond wire aging model is established, and the Vce_on is selected as the monitoring parameter. Secondly, taking a three-phase inverter circuit as an example, the Vce_on and Ic waveforms of the IGBT module are monitored in real time, and the process of online monitoring is introduced accordingly. Finally, the experimental results output by RT-LAB indicate that the method proposed in this paper can accurately identify the aging state of IGBT bond wires under different conditions. Full article
(This article belongs to the Special Issue Reliability Assessment and Modeling of Optical and Semiconductor Devices)
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13 pages, 6530 KiB  
Article
Analytical Current–Voltage Modeling and Analysis of the MFIS Gate-All-Around Transistor Featuring Negative-Capacitance
by Yeji Kim, Yoongeun Seon, Soowon Kim, Jongmin Kim, Saemin Bae, Inkyung Yang, Changhyun Yoo, Junghoon Ham, Jungmin Hong and Jongwook Jeon
Electronics 2021, 10(10), 1177; https://0-doi-org.brum.beds.ac.uk/10.3390/electronics10101177 - 14 May 2021
Cited by 6 | Viewed by 2917
Abstract
Recently, in accordance with the demand for development of low-power semiconductor devices, a negative capacitance field-effect-transistor (NC-FET) that integrates ferroelectric material into a gate stack and utilizes negative capacitive behavior has been widely investigated. Furthermore, gate-all-around (GAA) architecture to reduce short-channel effect is [...] Read more.
Recently, in accordance with the demand for development of low-power semiconductor devices, a negative capacitance field-effect-transistor (NC-FET) that integrates ferroelectric material into a gate stack and utilizes negative capacitive behavior has been widely investigated. Furthermore, gate-all-around (GAA) architecture to reduce short-channel effect is expected to be applied after Fin-FET technology. In this work, we proposed a compact model describing current–voltage (I–V) relationships of an NC GAA-FET with interface trap effects for the first time, which is a simplified model by taking proper approximation in each operating region. This is a surface potential-based compact model, which is suitable for evaluating the I–V characteristics for each operating region. It was validated that the proposed model shows good agreement with the results of implicit numerical calculations. In addition, by using the proposed model, we explored the electrical properties of the NC GAA-FET by varying the basic design parameters such as ferroelectric thickness (tfe), intermediate insulator thickness (tox), silicon channel radius (R), and interface trap densities (Net). Full article
(This article belongs to the Special Issue Reliability Assessment and Modeling of Optical and Semiconductor Devices)
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15 pages, 9566 KiB  
Article
A Study on the Effect of Bond Wires Lift-Off on IGBT Thermal Resistance Measurement
by Dan Luo, Minyou Chen, Wei Lai, Hongjian Xia, Xueni Ding and Zhenyu Deng
Electronics 2021, 10(2), 194; https://0-doi-org.brum.beds.ac.uk/10.3390/electronics10020194 - 15 Jan 2021
Cited by 6 | Viewed by 3283
Abstract
Bond wire lift-off will cause an increase of remaining wires’ power dissipation, which usually is ignored for healthy modules. However, only partial wires’ power dissipation transfers through thermal path from junction to case, which will lead to overestimate the whole power dissipation from [...] Read more.
Bond wire lift-off will cause an increase of remaining wires’ power dissipation, which usually is ignored for healthy modules. However, only partial wires’ power dissipation transfers through thermal path from junction to case, which will lead to overestimate the whole power dissipation from collector to emitter pole and underestimate the calculated thermal resistance using the proportion of temperature difference to power dissipation. A FEM model is established to show the change of heat flow after bond wires were removed, the temperature of bond wires increases, and the measured thermal resistance decrease after bond wires lift-off. It is validated by experimental results using open package Insulated Gate Bipolar Transistor (IGBT) modules under different current conditions. This conclusion might be helpful to indicate the bond wires lift-off and solder fatigue by comparing the change of measured thermal resistance. Using the Kelvin setup to measure thermal resistance will cause misjudgment of failure mode due to the ignoring of wires’ power dissipation. This paper proposed that the lift-off of bond wires will lead to underestimating the thermal resistance measurement, which will overestimate the lifetime of IGBT module and misjudge its state of health. Full article
(This article belongs to the Special Issue Reliability Assessment and Modeling of Optical and Semiconductor Devices)
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9 pages, 2763 KiB  
Article
LTPS TFTs with an Amorphous Silicon Buffer Layer and Source/Drain Extension
by Hye In Kim, Jung Min Sung, Hyung Uk Cho, Yong Jo Kim, Young Gwan Park and Woo Young Choi
Electronics 2021, 10(1), 29; https://0-doi-org.brum.beds.ac.uk/10.3390/electronics10010029 - 28 Dec 2020
Cited by 7 | Viewed by 5922
Abstract
A low leakage poly-Si thin film transistor (TFT) is proposed featuring hydrogenated amorphous silicon (a-Si:H) buffer layer and source/drain extension (SDE) by using technology computer aided design (TCAD) simulation. This architecture reduces off-current effectively by suppressing two leakage current generation mechanisms with little [...] Read more.
A low leakage poly-Si thin film transistor (TFT) is proposed featuring hydrogenated amorphous silicon (a-Si:H) buffer layer and source/drain extension (SDE) by using technology computer aided design (TCAD) simulation. This architecture reduces off-current effectively by suppressing two leakage current generation mechanisms with little on-current loss. The amorphous silicon buffer layer having large bandgap energy (Eg) suppresses both thermal generation and minimum leakage current, which leads to higher on/off current ratio. In addition, the formation of lightly doped region near the drain alleviates the field-enhanced generation in the off-state by reducing electric field. TCAD simulation results show that the proposed TFT shows more than three orders of magnitude lower off-current than low-temperature polycrystalline silicon (LTPS) TFTs, while maintaining on-current. Full article
(This article belongs to the Special Issue Reliability Assessment and Modeling of Optical and Semiconductor Devices)
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11 pages, 4262 KiB  
Article
Characterization of Single Event Cell Upsets in a Radiation Hardened SRAM in a 40 nm Bulk CMOS Technology
by Guoqing Yang, Junting Yu, Jincheng Zhang, Xiangyuan Liu and Qiang Chen
Electronics 2020, 9(6), 927; https://0-doi-org.brum.beds.ac.uk/10.3390/electronics9060927 - 02 Jun 2020
Cited by 2 | Viewed by 2357
Abstract
A large amount of data needs to be stored in integrated circuits when data are being processed. The integrated circuits contain a large amount of static random access memory (SRAM) due to its high level of integration and speed. SRAM units should be [...] Read more.
A large amount of data needs to be stored in integrated circuits when data are being processed. The integrated circuits contain a large amount of static random access memory (SRAM) due to its high level of integration and speed. SRAM units should be as small as possible to achieve higher storage density. In this work, the features of single cell upsets (SCUs) and multiple cell upsets (MCUs) in a full custom SRAM are tested for a 40 nm bulk CMOS technology node, and Ge (linear energy transfer (LET) = 37.3 MeV cm2/mg), Cl (LET = 13.1 MeV cm2/mg), Al (LET = 8.6 MeV cm2/mg), O (LET = 3.1 MeV cm2/mg), and Li (LET = 0.5 MeV cm2/mg) particles are used. The test results show that the total single cell upset events are 2,000,147, 1,124,269, 413,100, 311,311, and 47,815 under the irradiation of Ge, Cl, Al, O, and Li, respectively. Moreover, due to single event upset reversal mechanism, multiple cell upsets significantly decrease. The total multiple cell upset events are 10, 4, 0, 0, and 0 under the irradiation of Ge, Cl, Al, O, and Li, respectively. There are a lot of single cell upsets appearing under Ge, Cl, Al, O, and Li exposure. The number is increasing with increasing LET, which means that well contacts still need optimization in the full custom SRAM. Close spacing of well contacts or increasing contacts are the approaches used to drain the excess carriers quickly, and error detection and correction (EDAC) is used for SRAM technology. The features show that SCUs have become a major source of soft errors for the full custom SRAM. Combining close spacing of well contacts with error detection and correction (EDAC) and a well engineering scheme are used to reduce single cell upsets, although there are a few MCUs which are inevitable. Radiation hardened by design schemes needs to be further improved. Full article
(This article belongs to the Special Issue Reliability Assessment and Modeling of Optical and Semiconductor Devices)
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12 pages, 3635 KiB  
Study Protocol
A 1/f Noise Detection Method for IGBT Devices Based on PSO-VMD
by Jie Wu, Xiao-juan Chen and Mei-yue Zhu
Electronics 2022, 11(11), 1722; https://0-doi-org.brum.beds.ac.uk/10.3390/electronics11111722 - 28 May 2022
Cited by 1 | Viewed by 1430
Abstract
The generation of 1/f noise is closely related to the quality defects of IGBT devices. In the process of detecting single-tube noise of IGBT, thermal noise and shot noise show obvious white noise characteristics in the low-frequency range. This paper investigates how [...] Read more.
The generation of 1/f noise is closely related to the quality defects of IGBT devices. In the process of detecting single-tube noise of IGBT, thermal noise and shot noise show obvious white noise characteristics in the low-frequency range. This paper investigates how to accurately detect the 1/f noise under strong white noise, and thus proposes a particle swarm optimization method known as variational mode decomposition. First, the particle swarm optimization algorithm was used twice to search the optimal parameter combination between the penalty parameter and the decomposition modulus of the VMD model. Then, the parameters of the variational mode decomposition algorithm were set in optimal parameter combination. The frequency center and bandwidth of each IMF component were determined by continuous iteration in the variational framework. Finally, the 1/f noise signal was adaptively separated from background noise. Extensive experimental investigations carried out under different signal-to-noise ratios, compared with the optimal wavelet denoising algorithm, revealed that the PSO-VMD algorithm improved the signal-to-noise ratio by 6.6%, 16.82%, and 42.48%, whereas the mean square error is reduced by 7.12%, 19.80%, and 33.76%. Full article
(This article belongs to the Special Issue Reliability Assessment and Modeling of Optical and Semiconductor Devices)
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