Editorial

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4 pages, 192 KiB

Open AccessEditorial

Signal Processing and Analysis of Electrical Circuit

by Adam Glowacz and Jose Alfonso Antonino Daviu

Electronics 2020, 9(1), 17; https://0-doi-org.brum.beds.ac.uk/10.3390/electronics9010017 - 23 Dec 2019

Viewed by 2202

Abstract

The analysis of electrical circuits is an essential task in the evaluation of electrical systems [...] Full article

(This article belongs to the Special Issue Signal Processing and Analysis of Electrical Circuit)

Research

Jump to: Editorial

21 pages, 4980 KiB

Open AccessArticle

Numerical Laplace Inversion Method for Through-Silicon Via (TSV) Noise Coupling in 3D-IC Design

by Khaoula Ait Belaid, Hassan Belahrach and Hassan Ayad

Electronics 2019, 8(9), 1010; https://0-doi-org.brum.beds.ac.uk/10.3390/electronics8091010 - 10 Sep 2019

Cited by 11 | Viewed by 4209

Abstract

Typical 3D integrated circuit structures based on through-silicon vias (TSVs) are complicated to study and analyze. Therefore, it seems important to find some methods to investigate them. In this paper, a method is proposed to model and compute the time-domain coupling noise in [...] Read more.

Typical 3D integrated circuit structures based on through-silicon vias (TSVs) are complicated to study and analyze. Therefore, it seems important to find some methods to investigate them. In this paper, a method is proposed to model and compute the time-domain coupling noise in 3D Integrated Circuit (3D-IC) based on TSVs. It is based on the numerical inversion Laplace transform (NILT) method and the chain matrices. The method is validated using some experimental results and the Pspice and Matlab tools. The results confirm the effectiveness of the proposed technique and the noise is analyzed in several cases. It is found that TSV noise coupling is affected by different factors such as source characteristics, horizontal interconnections, and the type of Inputs and Outputs (I/O) drivers. Full article

(This article belongs to the Special Issue Signal Processing and Analysis of Electrical Circuit)

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24 pages, 12049 KiB

Open AccessArticle

Investigation of Induced Charge Mechanism on a Rod Electrode

by Jiming Li, Jingyu Li, Xuezhen Cheng and Guojin Feng

Electronics 2019, 8(9), 977; https://0-doi-org.brum.beds.ac.uk/10.3390/electronics8090977 - 01 Sep 2019

Cited by 18 | Viewed by 3568

Abstract

Rod electrodes based on an electrostatic induction mechanism are widely used in various industrial applications, but the analytic solution of an induced charge mechanism on a metal rod electrode has not yet been systematically established. In this paper, the theoretical model of the [...] Read more.

Rod electrodes based on an electrostatic induction mechanism are widely used in various industrial applications, but the analytic solution of an induced charge mechanism on a metal rod electrode has not yet been systematically established. In this paper, the theoretical model of the induced charge on a rod electrode is obtained through the method of images. Then, the properties of the rod electrode under the action of the point charge are studied, including the induced charge density distribution on the rod electrode, the amount of the induced charge with different diameters and lengths of the electrode, and the effective space region induced by the electrode. On this basis, a theoretical model of the induced current on a rod electrode is established, which is used to study the induced current properties by a moving point charge. It is found that both the magnitude and bandwidth of the induced current increase with the increased point charge velocity. Finally, three experimental studies are conducted, and the experimental results show good consistency with the analysis of the theoretical model, verifying the correctness, and accuracy of the model. In addition, the induced charge mechanism studied in this paper can act as an effective basis for the rod electrode sensor design in terms of the optimal radius and length. Full article

(This article belongs to the Special Issue Signal Processing and Analysis of Electrical Circuit)

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24 pages, 26743 KiB

Open AccessArticle

A Novel Image-Restoration Method Based on High-Order Total Variation Regularization Term

by Jianhong Xiang, Pengfei Ye, Linyu Wang and Mingqi He

Electronics 2019, 8(8), 867; https://0-doi-org.brum.beds.ac.uk/10.3390/electronics8080867 - 05 Aug 2019

Cited by 7 | Viewed by 3283

Abstract

This paper presents two new models for solving image the deblurring problem in the presence of impulse noise. One involves a high-order total variation (TV) regularizer term in the corrected total variation L1 (CTVL1) model and is named high-order corrected TVL1 (HOCTVL1). This [...] Read more.

This paper presents two new models for solving image the deblurring problem in the presence of impulse noise. One involves a high-order total variation (TV) regularizer term in the corrected total variation L1 (CTVL1) model and is named high-order corrected TVL1 (HOCTVL1). This new model can not only suppress the defects of the staircase effect, but also improve the quality of image restoration. In most cases, the regularization parameter in the model is a fixed value, which may influence processing results. Aiming at this problem, the spatially adapted regularization parameter selection scheme is involved in HOCTVL1 model, and spatially adapted HOCTVL1 (SAHOCTVL1) model is proposed. When dealing with corrupted images, the regularization parameter in SAHOCTVL1 model can be updated automatically. Many numerical experiments are conducted in this paper and the results show that the two models can significantly improve the effects both in visual quality and signal-to-noise ratio (SNR) at the expense of a small increase in computational time. Compared to HOCTVL1 model, SAHOCTVL1 model can restore more texture details, though it may take more time. Full article

(This article belongs to the Special Issue Signal Processing and Analysis of Electrical Circuit)

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22 pages, 3791 KiB

Open AccessArticle

A n-out-of-n Sharing Digital Image Scheme by Using Color Palette

by Ching-Nung Yang, Qin-Dong Sun, Yan-Xiao Liu and Ci-Ming Wu

Electronics 2019, 8(7), 802; https://0-doi-org.brum.beds.ac.uk/10.3390/electronics8070802 - 17 Jul 2019

Viewed by 2778

Abstract

A secret image sharing (SIS) scheme inserts a secret message into shadow images in a way that if shadow images are combined in a specific way, the secret image can be recovered. A 2-out-of-2 sharing digital image scheme (SDIS) adopts a color palette [...] Read more.

A secret image sharing (SIS) scheme inserts a secret message into shadow images in a way that if shadow images are combined in a specific way, the secret image can be recovered. A 2-out-of-2 sharing digital image scheme (SDIS) adopts a color palette to share a digital color secret image into two shadow images, and the secret image can be recovered from two shadow images, while any one shadow image has no information about the secret image. This 2-out-of-2 SDIS may keep the shadow size small because by using a color palette, and thus has advantage of reducing storage. However, the previous works on SDIS are just 2-out-of-2 scheme and have limited functions. In this paper, we take the lead to study a general n-out-of-n SDIS which can be applied on more than two shadow. The proposed SDIS is implemented on the basis of 2-out-of-2 SDIS. Our main contribution has the higher contrast of binary meaningful shadow and the larger region in color shadows revealing cover image when compared with previous 2-out-of-2 SDISs. Meanwhile, our SDIS is resistant to colluder attack. Full article

(This article belongs to the Special Issue Signal Processing and Analysis of Electrical Circuit)

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16 pages, 8545 KiB

Open AccessArticle

A Low-Cost, High-Precision Method for Ripple Voltage Measurement Using a DAC and Comparators

by Jincheng Liu, Jiguang Yue, Li Wang, Chenhao Wu and Feng Lyu

Electronics 2019, 8(5), 586; https://0-doi-org.brum.beds.ac.uk/10.3390/electronics8050586 - 27 May 2019

Cited by 2 | Viewed by 4090

Abstract

As the core of electronic system, the switched-mode power supply (SMPS) will lead to serious accidents and catastrophes if it suddenly fails. According to the related research, the monitoring of ripple can acquire the health degree of SMPS indirectly. To realize low-cost, high-precision, [...] Read more.

As the core of electronic system, the switched-mode power supply (SMPS) will lead to serious accidents and catastrophes if it suddenly fails. According to the related research, the monitoring of ripple can acquire the health degree of SMPS indirectly. To realize low-cost, high-precision, and automatic ripple measurement, this paper proposes a new ripple voltage (peak-to-peak value) measuring scheme, utilizing a DAC and two high-speed comparators. Within this scheme, the DC component of SMPS output is blocked by a high-pass filter (HPF). Then, the filtered signal and the reference voltage from a DAC together compose the input of a high-speed comparator. Finally, output pulses of the comparator are captured by a microcontroller unit (MCU), which readjusts the output of the DAC by calculation, and this process is repeated until the DAC output is exactly equal to the peak (or valley) value of ripple. Moreover, in order to accelerate the measurement process, a peak estimation method is specially designed to calculate the output ripple peak (or valley) value of buck topology through merely two measurements. Then the binary search method is utilized to obtain a more exact value on the basis of estimative results. Additionally, an analysis of the measurement error of this ripple measurement system is executed, which shows that the theoretical error is less than 0.5% where the ripple value is larger than 500 mV. Furthermore, appropriate components are selected, and a prototype is manufactured to verify the validity of the proposed theory. Full article

(This article belongs to the Special Issue Signal Processing and Analysis of Electrical Circuit)

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16 pages, 6202 KiB

Open AccessArticle

Noise Reduction for High-Accuracy Automatic Calibration of Resolver Signals via DWT-SVD Based Filter

by Meishan Guo and Zhong Wu

Electronics 2019, 8(5), 516; https://0-doi-org.brum.beds.ac.uk/10.3390/electronics8050516 - 09 May 2019

Cited by 7 | Viewed by 3412

Abstract

High-accuracy calibration of resolver signals is the key to improve its angular measurement accuracy. However, inductive harmonics, residual excitation components, and random noise in signals dramatically restrict the further improvement of calibration accuracy. Aiming to reduce these unexpected noises, a filter based on [...] Read more.

High-accuracy calibration of resolver signals is the key to improve its angular measurement accuracy. However, inductive harmonics, residual excitation components, and random noise in signals dramatically restrict the further improvement of calibration accuracy. Aiming to reduce these unexpected noises, a filter based on discrete wavelet transform (DWT) and singular value decomposition (SVD) is designed in this paper. Firstly, the signal was decomposed into a time-frequency domain by DWT and several groups of coefficients were obtained. Next, the SVD operation of a Hankel matrix created from the coefficients was made. Afterwards, the noises were attenuated by reconstructing the signal with a few selected singular values. Compared with a conventional low-pass filter, this method can almost only preserve the fundamental and DC components of the signal because of the multi-resolution characteristic of DWT and the good correspondence between the singular value and frequency. Therefore, the calibration accuracy of the imperfect characteristics could be improved effectively. Simulation and experimental results demonstrated the effectiveness of the proposed method. Full article

(This article belongs to the Special Issue Signal Processing and Analysis of Electrical Circuit)

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22 pages, 4490 KiB

Open AccessArticle

HPEFT for Hierarchical Heterogeneous Multi-DAG in a Multigroup Scan UPA System

by Yuzhong Li, Wenming Tang and Guixiong Liu

Electronics 2019, 8(5), 498; https://0-doi-org.brum.beds.ac.uk/10.3390/electronics8050498 - 05 May 2019

Cited by 1 | Viewed by 2662

Abstract

Multidirected acyclic graph (DAG) workflow scheduling is a key problem in the heterogeneous distributed environment in the distributed computing field. A hierarchical heterogeneous multi-DAG workflow problem (HHMDP) was proposed based on the different signal processing workflows produced by different grouping and scanning modes [...] Read more.

Multidirected acyclic graph (DAG) workflow scheduling is a key problem in the heterogeneous distributed environment in the distributed computing field. A hierarchical heterogeneous multi-DAG workflow problem (HHMDP) was proposed based on the different signal processing workflows produced by different grouping and scanning modes and their hierarchical processing in specific functional signal processing modules in a multigroup scan ultrasonic phased array (UPA) system. A heterogeneous predecessor earliest finish time (HPEFT) algorithm with predecessor pointer adjustment was proposed based on the improved heterogeneous earliest finish time (HEFT) algorithm. The experimental results denote that HPEFT reduces the makespan, ratio of the idle time slot (RITS), and missed deadline rate (MDR) by 3.87–57.68%, 0–6.53%, and 13–58%, respectively, and increases relative relaxation with respect to the deadline (RLD) by 2.27–8.58%, improving the frame rate and resource utilization and reducing the probability of exceeding the real-time period. The multigroup UPA instrument architecture in multi-DAG signal processing flow was also provided. By simulating and verifying the scheduling algorithm, the architecture and the HPEFT algorithm is proved to coordinate the order of each group of signal processing tasks for improving the instrument performance. Full article

(This article belongs to the Special Issue Signal Processing and Analysis of Electrical Circuit)

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18 pages, 16082 KiB

Open AccessArticle

Rolling 3D Laplacian Pyramid Video Fusion

by Rade Pavlović and Vladimir Petrović

Electronics 2019, 8(4), 447; https://0-doi-org.brum.beds.ac.uk/10.3390/electronics8040447 - 19 Apr 2019

Viewed by 3847

Abstract

In this paper, we present a novel algorithm for video fusion of multi-sensor sequences applicable to real-time night vision systems. We employ the Laplacian pyramid fusion of a block of successive frames to add temporal robustness to the fused result. For the fusion [...] Read more.

In this paper, we present a novel algorithm for video fusion of multi-sensor sequences applicable to real-time night vision systems. We employ the Laplacian pyramid fusion of a block of successive frames to add temporal robustness to the fused result. For the fusion rule, we first group high and low frequency levels of the decomposed frames in the block from both input sensor sequences. Then, we define local space-time energy measure to guide the selection based fusion process in a manner that achieves spatio-temporal stability. We demonstrate our approach on several well-known multi-sensor video fusion examples with varying contents and target appearance and show its advantage over conventional video fusion approaches. Computational complexity of the proposed methods is kept low by the use of simple linear filtering that can be easily parallelised for implementation on general-purpose graphics processing units (GPUs). Full article

(This article belongs to the Special Issue Signal Processing and Analysis of Electrical Circuit)

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9 pages, 4074 KiB

Open AccessArticle

A 2.5 Gbps, 10-Lane, Low-Power, LVDS Transceiver in 28 nm CMOS Technology

by Xu Bai, Jianzhong Zhao, Shi Zuo and Yumei Zhou

Electronics 2019, 8(3), 350; https://0-doi-org.brum.beds.ac.uk/10.3390/electronics8030350 - 22 Mar 2019

Cited by 6 | Viewed by 7343

Abstract

This paper presents a 2.5 Gbps 10-lane low-power low voltage differential signaling (LVDS) transceiver for a high-speed serial interface. In the transmitter, a complementary MOS H-bridge output driver with a common mode feedback (CMFB) circuit was used to achieve a stipulated common mode [...] Read more.

This paper presents a 2.5 Gbps 10-lane low-power low voltage differential signaling (LVDS) transceiver for a high-speed serial interface. In the transmitter, a complementary MOS H-bridge output driver with a common mode feedback (CMFB) circuit was used to achieve a stipulated common mode voltage over process, voltage and temperature (PVT) variations. The receiver was composed of a pre-stage common mode voltage shifter and a rail-to-rail comparator. The common mode voltage shifter with an error amplifier shifted the common mode voltage of the input signal to the required range, thereby the following rail-to-rail comparator obtained the maximum transconductance to recover the signal. The chip was fabricated using SMIC 28 nm CMOS technology, and had an area of 1.46 mm². The measured results showed that the output swing of the transmitter was around 350 mV, with a root-mean-square (RMS) jitter of 3.65 [email protected] Gbps, and the power consumption of each lane was 16.51 mW under a 1.8 V power supply. Full article

(This article belongs to the Special Issue Signal Processing and Analysis of Electrical Circuit)

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12 pages, 4398 KiB

Open AccessArticle

A 2.6 GS/s 8-Bit Time-Interleaved SAR ADC in 55 nm CMOS Technology

by Dong Wang, Xiaoge Zhu, Xuan Guo, Jian Luan, Lei Zhou, Danyu Wu, Huasen Liu, Jin Wu and Xinyu Liu

Electronics 2019, 8(3), 305; https://0-doi-org.brum.beds.ac.uk/10.3390/electronics8030305 - 08 Mar 2019

Cited by 12 | Viewed by 5611

Abstract

This paper presents an eight-channel time-interleaved (TI) 2.6 GS/s 8-bit successive approximation register (SAR) analog-to-digital converter (ADC) prototype in a 55-nm complementary metal-oxide-semiconductor (CMOS) process. The channel-selection-embedded bootstrap switch is adopted to perform sampling times synchronization using the full-speed master clock to suppress [...] Read more.

This paper presents an eight-channel time-interleaved (TI) 2.6 GS/s 8-bit successive approximation register (SAR) analog-to-digital converter (ADC) prototype in a 55-nm complementary metal-oxide-semiconductor (CMOS) process. The channel-selection-embedded bootstrap switch is adopted to perform sampling times synchronization using the full-speed master clock to suppress the time skew between channels. Based on the segmented pre-quantization and bypass switching scheme, double alternate comparators clocked asynchronously with background offset calibration are utilized in sub-channel SAR ADC to achieve high speed and low power. Measurement results show that the signal-to-noise-and-distortion ratio (SNDR) of the ADC is above 38.2 dB up to 500 MHz input frequency and above 31.8 dB across the entire first Nyquist zone. The differential non-linearity (DNL) and integral non-linearity (INL) are +0.93/−0.85 LSB and +0.71/−0.91 LSB, respectively. The ADC consumes 60 mW from a 1.2 V supply, occupies an area of 400 μm × 550 μm, and exhibits a figure-of-merit (FoM) of 348 fJ/conversion-step. Full article

(This article belongs to the Special Issue Signal Processing and Analysis of Electrical Circuit)

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17 pages, 9056 KiB

Open AccessArticle

A Multispectral Backscattered Light Recorder of Insects’ Wingbeats

by Iraklis Rigakis, Ilyas Potamitis, Nicolaos-Alexandros Tatlas, Ioannis Livadaras and Stavros Ntalampiras

Electronics 2019, 8(3), 277; https://0-doi-org.brum.beds.ac.uk/10.3390/electronics8030277 - 02 Mar 2019

Cited by 15 | Viewed by 4706

Abstract

Most reported optical recorders of the wingbeat of insects are based on the so-called extinction light, which is the variation of light in the receiver due to the cast shadow of the insect’s wings and main body. In this type of recording devices, [...] Read more.

Most reported optical recorders of the wingbeat of insects are based on the so-called extinction light, which is the variation of light in the receiver due to the cast shadow of the insect’s wings and main body. In this type of recording devices, the emitter uses light and is placed opposite to the receiver, which is usually a single (or multiple) photodiode. In this work, we present a different kind of wingbeat sensor and its associated recorder that aims to extract a deeper representational signal of the wingbeat event and color characterization of the main body of the insect, namely: a) we record the backscattered light that is richer in harmonics than the extinction light, b) we use three different spectral bands, i.e., a multispectral approach that aims to grasp the melanization and microstructural and color features of the wing and body of the insects, and c) we average at the receiver’s level the backscattered signal from many LEDs that illuminate the wingbeating insect from multiple orientations and thus offer a smoother and more complete signal than one based on a single snapshot. We present all the necessary details to reproduce the device and we analyze many insects of interest like the bee Apis mellifera, the wasp Polistes gallicus, and some insects whose wingbeating characteristics are pending in the current literature, like Drosophila suzukii and Zaprionus, another member of the drosophilidae family. Full article

(This article belongs to the Special Issue Signal Processing and Analysis of Electrical Circuit)

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12 pages, 1028 KiB

Open AccessArticle

A Highly Robust Interface Circuit for Resistive Sensors

by Emmanuel Gómez-Ramírez, L. A. Maeda-Nunez, Luis C. Álvarez-Simón and F. G. Flores-García

Electronics 2019, 8(3), 263; https://0-doi-org.brum.beds.ac.uk/10.3390/electronics8030263 - 28 Feb 2019

Cited by 9 | Viewed by 3871

Abstract

The signal from a resistive sensor must be converted into a digital signal to be compatible with a computer through an interface circuit. Resistance-to-Period converter, used as interface, is preferred if the resistance variations are very large. This paper presents the structure of [...] Read more.

The signal from a resistive sensor must be converted into a digital signal to be compatible with a computer through an interface circuit. Resistance-to-Period converter, used as interface, is preferred if the resistance variations are very large. This paper presents the structure of an interface circuit for resistive sensors that is highly robust to component and power supply variations. Robustness is achieved by using the ratiometric approach, thus complex circuits or highly accurate voltage references are not necessary. To validate the proposed approach, a prototype was implemented using discrete components. Measurements were carried out considering a variation of ±35% in the single supply voltage and a range from 1 k

Ω

to 1 M

Ω

. Full article

(This article belongs to the Special Issue Signal Processing and Analysis of Electrical Circuit)

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10 pages, 3602 KiB

Open AccessArticle

A 13-bit 3-MS/s Asynchronous SAR ADC with a Passive Resistor Based Loop Delay Circuit

by Hyungyu Ju and Minjae Lee

Electronics 2019, 8(3), 262; https://0-doi-org.brum.beds.ac.uk/10.3390/electronics8030262 - 27 Feb 2019

Cited by 8 | Viewed by 4703

Abstract

An asynchronous successive approximation register (SAR) ADC incorporates a passive resistor based delay cell to reduce power consumption and accommodate the SAR ADC with a reconfigurable sampling frequency or tapered bit period without repeated delay calibration. The ADC aims to have a sampling [...] Read more.

An asynchronous successive approximation register (SAR) ADC incorporates a passive resistor based delay cell to reduce power consumption and accommodate the SAR ADC with a reconfigurable sampling frequency or tapered bit period without repeated delay calibration. The ADC aims to have a sampling frequency of several MS/s. The proposed delay cell adopts resistance controlled delay architecture to generate a delay of nanoseconds with high linearity. The resistance controlled delay cell is based on a passive resistor instead of a MOS transistor using a triode region to avoid the nonlinear delay characteristic of active devices. From the analysis of the linearity of delay cell, the passive resistor based delay cell achieves a delay error of about 5 percent. The prototype ADC to validate the proposed passive resistor based delay cell is fabricated in 40

n m

CMOS. The ADC occupies 0.054

m m^{2}

and achieves an SNDR of 57.4 dB under 67

μ W

power dissipation at a 1.1 V supply with a 3 MHz sampling frequency. Full article

(This article belongs to the Special Issue Signal Processing and Analysis of Electrical Circuit)

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11 pages, 334 KiB

Open AccessArticle

A Study of Movement Classification of the Lower Limb Based on up to 4-EMG Channels

by Diana C. Toledo-Pérez, Miguel A. Martínez-Prado, Roberto A. Gómez-Loenzo, Wilfrido J. Paredes-García and Juvenal Rodríguez-Reséndiz

Electronics 2019, 8(3), 259; https://0-doi-org.brum.beds.ac.uk/10.3390/electronics8030259 - 27 Feb 2019

Cited by 53 | Viewed by 3864

Abstract

The number and position of sEMG electrodes have been studied extensively due to the need to improve the accuracy of the classification they carry out of the intention of movement. Nevertheless, increasing the number of channels used for this classification often increases their [...] Read more.

The number and position of sEMG electrodes have been studied extensively due to the need to improve the accuracy of the classification they carry out of the intention of movement. Nevertheless, increasing the number of channels used for this classification often increases their processing time as well. This research work contributes with a comparison of the classification accuracy based on the different number of sEMG signal channels (one to four) placed in the right lower limb of healthy subjects. The analysis is performed using Mean Absolute Values, Zero Crossings, Waveform Length, and Slope Sign Changes; these characteristics comprise the feature vector. The algorithm used for the classification is the Support Vector Machine after applying a Principal Component Analysis to the features. The results show that it is possible to reach more than 90% of classification accuracy by using 4 or 3 channels. Moreover, the difference obtained with 500 and 1000 samples, with 2, 3 and 4 channels, is not higher than 5%, which means that increasing the number of channels does not guarantee 100% precision in the classification. Full article

(This article belongs to the Special Issue Signal Processing and Analysis of Electrical Circuit)

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15 pages, 8784 KiB

Open AccessArticle

A Countermeasure against DPA on SIMON with an Area-Efficient Structure

by Yuanyuan Zhang, Ning Wu, Fang Zhou, Jinbao Zhang and Muhammad Rehan Yahya

Electronics 2019, 8(2), 240; https://0-doi-org.brum.beds.ac.uk/10.3390/electronics8020240 - 20 Feb 2019

Cited by 3 | Viewed by 3245

Abstract

Differential power analysis (DPA) is an effective side channel attack method, which poses a critical threat to cryptographic algorithms, especially lightweight ciphers such as SIMON. In this paper, we propose an area-efficient countermeasure against DPA on SIMON based on the power randomization. Firstly, [...] Read more.

Differential power analysis (DPA) is an effective side channel attack method, which poses a critical threat to cryptographic algorithms, especially lightweight ciphers such as SIMON. In this paper, we propose an area-efficient countermeasure against DPA on SIMON based on the power randomization. Firstly, we review and analyze the architecture of SIMON algorithm. Secondly, we prove the threat of DPA attack to SIMON by launching actual DPA attack on SIMON 32/64 circuit. Thirdly, a low-cost power randomization scheme is proposed by combining fault injection with double rate technology, and the corresponding circuit design is implemented. To the best of our knowledge, this is the first scheme that applies the combination of fault injection and double rate technology to the DPA-resistance. Finally, the t-test is used to evaluate the security mechanism of the proposed designs with leakage quantification. Our experimental results show that the proposed design implements DPA-resistance of SIMON algorithm at certain overhead the cost of 47.7% LUTs utilization and 39.6% registers consumption. As compared to threshold implementation and bool mask, the proposed scheme has greater advantages in resource consumption. Full article

(This article belongs to the Special Issue Signal Processing and Analysis of Electrical Circuit)

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25 pages, 2061 KiB

Open AccessArticle

Performance Analysis of Single-Step Localization Method Based on Matrix Eigen-Perturbation Theory with System Errors

by Tianzhu Qin, Bin Ba and Daming Wang

Electronics 2019, 8(2), 235; https://0-doi-org.brum.beds.ac.uk/10.3390/electronics8020235 - 19 Feb 2019

Cited by 1 | Viewed by 2525

Abstract

Direct position determination (DPD) is a novel technique in passive localization field recently, receiving superior localization performance compared with the conventional two-step method. The DPD estimator using Doppler shifts is first proposed by Weiss, but it is not suitable for antenna arrays. Additionally, [...] Read more.

Direct position determination (DPD) is a novel technique in passive localization field recently, receiving superior localization performance compared with the conventional two-step method. The DPD estimator using Doppler shifts is first proposed by Weiss, but it is not suitable for antenna arrays. Additionally, the performance analysis of this method with system errors is absent. This study discusses the single-step localization problem based on moving arrays and exhibits the performance analysis via matrix eigen-perturbation theory with system errors. First, the DPD method using angle of arrival and Doppler shifts is introduced. Then, by adding the eigenvalue perturbations to the estimated Hermitian matrix, the asymptotic linear formulation of localization errors is derived. Consequently, the mean square error of the DPD method is available. Finally, Cramér–Rao bound without system errors is presented, providing a benchmark for the best localization precision and revealing the influence of system errors on the localization precision. Simulation results demonstrate the theoretical analysis in this study. Full article

(This article belongs to the Special Issue Signal Processing and Analysis of Electrical Circuit)

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21 pages, 6862 KiB

Open AccessArticle

Stochastic Gradient Matching Pursuit Algorithm Based on Sparse Estimation

by Liquan Zhao, Yunfeng Hu and Yulong Liu

Electronics 2019, 8(2), 165; https://0-doi-org.brum.beds.ac.uk/10.3390/electronics8020165 - 01 Feb 2019

Cited by 3 | Viewed by 2746

Abstract

The stochastic gradient matching pursuit algorithm requires the sparsity of the signal as prior information. However, this prior information is unknown in practical applications, which restricts the practical applications of the algorithm to some extent. An improved method was proposed to overcome this [...] Read more.

The stochastic gradient matching pursuit algorithm requires the sparsity of the signal as prior information. However, this prior information is unknown in practical applications, which restricts the practical applications of the algorithm to some extent. An improved method was proposed to overcome this problem. First, a pre-evaluation strategy was used to evaluate the sparsity of the signal and the estimated sparsity was used as the initial sparsity. Second, if the number of columns of the candidate atomic matrix was smaller than that of the rows, the least square solution of the signal was calculated, otherwise, the least square solution of the signal was set as zero. Finally, if the current residual was greater than the previous residual, the estimated sparsity was adjusted by the fixed step-size and stage index, otherwise we did not need to adjust the estimated sparsity. The simulation results showed that the proposed method was better than other methods in terms of the aspect of reconstruction percentage in the larger sparsity environment. Full article

(This article belongs to the Special Issue Signal Processing and Analysis of Electrical Circuit)

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15 pages, 4242 KiB

Open AccessArticle

Development of a Miniaturized Frequency Standard Comparator Based on FPGA

by Sheng Tang, Jing Ke, Tianxiang Wang and Zhouhu Deng

Electronics 2019, 8(2), 123; https://0-doi-org.brum.beds.ac.uk/10.3390/electronics8020123 - 23 Jan 2019

Cited by 1 | Viewed by 3902

Abstract

Frequency standard comparison measurement has important practical significance for the rational use of frequency standard in engineering. This paper was devoted to the study of frequency standard comparison measurement based on classical dual mixing time difference method. However, in the actual system design [...] Read more.

Frequency standard comparison measurement has important practical significance for the rational use of frequency standard in engineering. This paper was devoted to the study of frequency standard comparison measurement based on classical dual mixing time difference method. However, in the actual system design and implementation, the commonly used counter was discarded and the phase difference was measured by a digital signal processing method based on Field Programmable Gate Array (FPGA). A miniaturized 10 MHz frequency standard comparator with good noise floor was successfully developed. The size of the prototype circuit board is only about 292.1 cm². The experimental results showed that the noise floor of the frequency standard comparator was typically better than 7.50 × 10⁻¹²/s, and its relative error of phase difference measurement was less than 1.70 × 10⁻⁵. Full article

(This article belongs to the Special Issue Signal Processing and Analysis of Electrical Circuit)

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16 pages, 7272 KiB

Open AccessArticle

Fully Integrated Low-Ripple Switched-Capacitor DC–DC Converter with Parallel Low-Dropout Regulator

by Jeong-Yun Lee, Gwang-Sub Kim, Kwang-Il Oh and Donghyun Baek

Electronics 2019, 8(1), 98; https://0-doi-org.brum.beds.ac.uk/10.3390/electronics8010098 - 16 Jan 2019

Cited by 11 | Viewed by 6036

Abstract

In this paper, we propose a fully integrated switched-capacitor DC–DC converter with low ripple and fast transient response for portable low-power electronic devices. The proposed converter reduces the output ripple by filtering the control ripple via combining a low-dropout regulator with a main [...] Read more.

In this paper, we propose a fully integrated switched-capacitor DC–DC converter with low ripple and fast transient response for portable low-power electronic devices. The proposed converter reduces the output ripple by filtering the control ripple via combining a low-dropout regulator with a main switched-capacitor DC–DC converter with a four-bit digital capacitance modulation control. In addition, the four-phase interleaved technique applied to the main converter reduces the switching ripple. The proposed converter provides an output voltage ranging from 1.2 to 1.5 V from a 3.3 V supply. Its peak efficiency reaches 73% with ripple voltages below 55 mV over the entire output power range. The transient response time for a load current variation from 100 μA to 50 mA is measured to be 800 ns. Importantly, the converter chip, which is fabricated using 0.13 μm complementary metal–oxide–semiconductor (CMOS) technology, has a size of 2.04 mm². We believe that our approach can contribute to advancements in power sources for applications such as wearable electronics and the Internet of Things. Full article

(This article belongs to the Special Issue Signal Processing and Analysis of Electrical Circuit)

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19 pages, 2394 KiB

Open AccessArticle

Design of Voltage Mode Electronically Tunable First Order All Pass Filter in ±0.7 V 16 nm CNFET Technology

by Muhammad Masud, Abu A’ain, Iqbal Khan and Nasir Husin

Electronics 2019, 8(1), 95; https://0-doi-org.brum.beds.ac.uk/10.3390/electronics8010095 - 15 Jan 2019

Cited by 15 | Viewed by 4386

Abstract

A novel voltage mode first order active only tuneable all pass filter (AOTAPF) circuit configuration is presented. The AOTAPF has been designed using ±0.7 V, 16 nm carbon nanotube field effect transistor (CNFET) Technology. The circuit uses CNFET based varactor and unity gain [...] Read more.

A novel voltage mode first order active only tuneable all pass filter (AOTAPF) circuit configuration is presented. The AOTAPF has been designed using ±0.7 V, 16 nm carbon nanotube field effect transistor (CNFET) Technology. The circuit uses CNFET based varactor and unity gain inverting amplifier (UGIA). The presented AOTAPF is realized with three N-type CNFETs and without any external passive components. It is to be noted that the realized circuit uses only two CNFETs between its supply-rails and thus, suitable for low-voltage operation. The electronic tunability is achieved by varying the voltage controlled capacitance of the employed CNFET varactor. By altering the varactor tuning voltage, a wide tunable range of pole frequency between 34.2 GHz to 56.9 GHz is achieved. The proposed circuit does not need any matching constraint and is suitable for multi-GHz frequency applications. The presented AOTAPF performance is substantiated with HSPICE simulation program for 16 nm technology-node, using the well-known Stanford CNFET model. AOTAPF simulation results verify the theory for a wide frequency-range. Full article

(This article belongs to the Special Issue Signal Processing and Analysis of Electrical Circuit)

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15 pages, 8250 KiB

Open AccessArticle

Shannon Entropy Index and a Fuzzy Logic System for the Assessment of Stator Winding Short-Circuit Faults in Induction Motors

by Arturo Mejia-Barron, J. Jesus de Santiago-Perez, David Granados-Lieberman, Juan P. Amezquita-Sanchez and Martin Valtierra-Rodriguez

Electronics 2019, 8(1), 90; https://0-doi-org.brum.beds.ac.uk/10.3390/electronics8010090 - 15 Jan 2019

Cited by 11 | Viewed by 3395

Abstract

The induction motor (IM) is one of the most important elements in industry. Although IMs are robust machines, they are susceptible to faults, where the stator winding short-circuit fault is one of the most common ones. In this work, the Shannon entropy (SE) [...] Read more.

The induction motor (IM) is one of the most important elements in industry. Although IMs are robust machines, they are susceptible to faults, where the stator winding short-circuit fault is one of the most common ones. In this work, the Shannon entropy (SE) index and a fuzzy logic (FL) system are proposed to diagnose short-circuit faults, considering both different severity levels and different load conditions. In the proposed methodology, a filtering stage based on brick-wall band-pass filters is firstly carried out. After this stage, the SE index is computed to quantify the fault severity and a FL system is applied to diagnose the IM condition in an automatic way. Unlike other works that propose some types of space transformations, the proposal is only based on a filtering stage and a time domain index, requiring low computational resources. The obtained results demonstrate the effectiveness of the proposal, i.e., the SE index quantifies the fault severity, regardless of the mechanical load, and the proposed FL system achieves a positive classification rate of 98%. Full article

(This article belongs to the Special Issue Signal Processing and Analysis of Electrical Circuit)

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14 pages, 2613 KiB

Open AccessFeature PaperArticle

A Capacitance-to-Time Converter-Based Electronic Interface for Differential Capacitive Sensors

by Andrea De Marcellis, Càndid Reig and María-Dolores Cubells-Beltrán

Electronics 2019, 8(1), 80; https://0-doi-org.brum.beds.ac.uk/10.3390/electronics8010080 - 10 Jan 2019

Cited by 21 | Viewed by 4835

Abstract

In this paper we present an oscillating conditioning circuit, operating a capacitance-to-time conversion, which is suitable for the readout of differential capacitive sensors. The simple architecture, based on a multiple-feedbacks structure that avoids ground noise disturbs and system calibrations, employs only three Operational [...] Read more.

In this paper we present an oscillating conditioning circuit, operating a capacitance-to-time conversion, which is suitable for the readout of differential capacitive sensors. The simple architecture, based on a multiple-feedbacks structure that avoids ground noise disturbs and system calibrations, employs only three Operational Amplifiers (OAs) and a mixer implementing a square wave oscillator that provides an AC sensor excitation voltage. It performs a Period Modulation (PM) and a Pulse Width Modulation (PWM) of the output signal proportionally to the sensor differential capacitance values. The sensor variation range and the detection sensitivity can be easily set through the additional resistors. Preliminary PSpice simulation results have shown a good agreement with theoretical calculations as well as a linear response with a high detection sensitivity of differential capacitive sensors having a baseline in the range [2.2 ÷ 180 pF]. Moreover, different experimental measurements have been also performed by implementing the circuit on a laboratory breadboard using commercial discrete components so validating the idea and providing the circuit performances with different kind of differential capacitive sensors achieving detection resolutions of about 0.1 fF in an overall differential capacitive variation range that is equal to ±15.8 pF. The achieved results demonstrate that the proposed interface solution is suitable for on-chip integration with different kinds of differential capacitive sensing devices, such as Micro-Electro-Mechanical-System (MEMS), force/position, and humidity sensors in biomedical and robotics applications. Full article

(This article belongs to the Special Issue Signal Processing and Analysis of Electrical Circuit)

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16 pages, 3992 KiB

Open AccessArticle

A Fusion Frequency Feature Extraction Method for Underwater Acoustic Signal Based on Variational Mode Decomposition, Duffing Chaotic Oscillator and a Kind of Permutation Entropy

by Yuxing Li, Xiao Chen, Jing Yu and Xiaohui Yang

Electronics 2019, 8(1), 61; https://0-doi-org.brum.beds.ac.uk/10.3390/electronics8010061 - 05 Jan 2019

Cited by 44 | Viewed by 4917

Abstract

In order to effectively extract the frequency characteristics of an underwater acoustic signal under sensor measurement, a fusion frequency feature extraction method for an underwater acoustic signal is presented based on variational mode decomposition (VMD), duffing chaotic oscillator (DCO) and a kind of [...] Read more.

In order to effectively extract the frequency characteristics of an underwater acoustic signal under sensor measurement, a fusion frequency feature extraction method for an underwater acoustic signal is presented based on variational mode decomposition (VMD), duffing chaotic oscillator (DCO) and a kind of permutation entropy (PE). Firstly, VMD decomposes the complex multi-component underwater acoustic signal into a set of intrinsic mode functions (IMFs), so as to extract the estimated center frequency of each IMF. Secondly, the frequency of the line spectrum can be obtained by using DCO and a kind of PE (KPE). DCO is used to detect the actual frequency of the line spectrum for each IMF and KPE can determine the accurate frequency when the phase space track is in the great periodic state. Finally, the frequency characteristic parameters acted as the input of the support vector machine (SVM) to distinguish different types of underwater acoustic signals. By comparing with the other three traditional methods for simulation signal and different kinds of underwater acoustic signals, the results show that the proposed method can accurately extract the frequency characteristics and effectively realize the classification and recognition for the underwater acoustic signal. Full article

(This article belongs to the Special Issue Signal Processing and Analysis of Electrical Circuit)

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14 pages, 4412 KiB

Open AccessFeature PaperArticle

A Tilt Sensor Node Embedding a Data-Fusion Algorithm for Vibration-Based SHM

by Nicola Testoni, Federica Zonzini, Alessandro Marzani, Valentina Scarponi and Luca De Marchi

Electronics 2019, 8(1), 45; https://0-doi-org.brum.beds.ac.uk/10.3390/electronics8010045 - 01 Jan 2019

Cited by 12 | Viewed by 4191

Abstract

This work describes a miniaturized sensor network based on low-power, light-weight and small footprint microelectromechanical (MEMS) sensor nodes capable to simultaneously measure tri-axial accelerations and tri-axial angular velocities. A real-time data fusion algorithm based on complementary filters is applied to extract tilt angles. [...] Read more.

This work describes a miniaturized sensor network based on low-power, light-weight and small footprint microelectromechanical (MEMS) sensor nodes capable to simultaneously measure tri-axial accelerations and tri-axial angular velocities. A real-time data fusion algorithm based on complementary filters is applied to extract tilt angles. The resulting device is designed to show competitive performance over the whole frequency range of the inertial units. Besides the capability to provide accurate measurements both in static and dynamic conditions, an optimization process has been designed to efficiently make the fusion procedure running on-sensor. An experimental campaign conducted on a pinned-pinned steel beam equipped with a network comprising several sensor nodes was used to evaluate the reliability of the developed architecture. Performance metrics revealed a satisfactory agreement to the physical model, thus making the network suitable for real-time tilt monitoring scenarios. Full article

(This article belongs to the Special Issue Signal Processing and Analysis of Electrical Circuit)

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21 pages, 6303 KiB

Open AccessArticle

A Robust Registration Method for Autonomous Driving Pose Estimation in Urban Dynamic Environment Using LiDAR

by Rendong Wang, Youchun Xu, Miguel Angel Sotelo, Yulin Ma, Thompson Sarkodie-Gyan, Zhixiong Li and Weihua Li

Electronics 2019, 8(1), 43; https://0-doi-org.brum.beds.ac.uk/10.3390/electronics8010043 - 01 Jan 2019

Cited by 29 | Viewed by 4283

Abstract

The registration of point clouds in urban environments faces problems such as dynamic vehicles and pedestrians, changeable road environments, and GPS inaccuracies. The state-of-the-art methodologies have usually combined the dynamic object tracking and/or static feature extraction data into a point cloud towards the [...] Read more.

The registration of point clouds in urban environments faces problems such as dynamic vehicles and pedestrians, changeable road environments, and GPS inaccuracies. The state-of-the-art methodologies have usually combined the dynamic object tracking and/or static feature extraction data into a point cloud towards the solution of these problems. However, there is the occurrence of minor initial position errors due to these methodologies. In this paper, the authors propose a fast and robust registration method that exhibits no need for the detection of any dynamic and/or static objects. This proposed methodology may be able to adapt to higher initial errors. The initial steps of this methodology involved the optimization of the object segmentation under the application of a series of constraints. Based on this algorithm, a novel multi-layer nested RANSAC algorithmic framework is proposed to iteratively update the registration results. The robustness and efficiency of this algorithm is demonstrated on several high dynamic scenes of both short and long time intervals with varying initial offsets. A LiDAR odometry experiment was performed on the KITTI data set and our extracted urban data-set with a high dynamic urban road, and the average of the horizontal position errors was compared to the distance traveled that resulted in 0.45% and 0.55% respectively. Full article

(This article belongs to the Special Issue Signal Processing and Analysis of Electrical Circuit)

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23 pages, 8500 KiB

Open AccessFeature PaperArticle

A Multichannel FRA-Based Impedance Spectrometry Analyzer Based on a Low-Cost Multicore Microcontroller

by Arturo Sanchez-Gonzalez, Nicolas Medrano, Belen Calvo and Pedro A. Martinez

Electronics 2019, 8(1), 38; https://0-doi-org.brum.beds.ac.uk/10.3390/electronics8010038 - 01 Jan 2019

Cited by 8 | Viewed by 4611

Abstract

Impedance spectrometry (IS) is a characterization technique in which a voltage or current signal is applied to a sample under test to measure its electrical behavior over a determined frequency range, obtaining its complex characteristic impedance. Frequency Response Analyzer (FRA) is an IS [...] Read more.

Impedance spectrometry (IS) is a characterization technique in which a voltage or current signal is applied to a sample under test to measure its electrical behavior over a determined frequency range, obtaining its complex characteristic impedance. Frequency Response Analyzer (FRA) is an IS technique based on Phase Sensitive Detection (PSD) to extract the real and imaginary response of the sample at each input signal, which presents advantages compared to FFT-based (Fast Fourier Transform) algorithms in terms of complexity and speed. Parallelization of this technique has proven pivotal in multi-sample characterization, reducing the instrumentation size and speeding up analysis processes in, e.g., biotechnological or chemical applications. This work presents a multichannel FRA-based IS system developed on a low-cost multicore microcontroller platform which both generates the required excitation signals and acquires and processes the output sensor data with a minimum number of external passive components, providing accurate impedance measurements. With a suitable configuration, the use of this multicore solution allows characterizing several impedance samples in parallel, reducing the measurement time. In addition, the proposed architecture is easily scalable. Full article

(This article belongs to the Special Issue Signal Processing and Analysis of Electrical Circuit)

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10 pages, 2749 KiB

Open AccessFeature PaperArticle

5GHz CMOS All-Pass Filter-Based True Time Delay Cell

by Seyed Rasoul Aghazadeh, Herminio Martinez and Alireza Saberkari

Electronics 2019, 8(1), 16; https://0-doi-org.brum.beds.ac.uk/10.3390/electronics8010016 - 22 Dec 2018

Cited by 12 | Viewed by 5584

Abstract

Analog CMOS time-delay cells realized by passive components, e.g., lumped LC delay lines, are inefficient in terms of area for multi-GHz frequencies. All-pass filters considered as active circuits can, therefore, be the best candidates to approximate time delays. This paper proposes a broadband [...] Read more.

Analog CMOS time-delay cells realized by passive components, e.g., lumped LC delay lines, are inefficient in terms of area for multi-GHz frequencies. All-pass filters considered as active circuits can, therefore, be the best candidates to approximate time delays. This paper proposes a broadband first-order voltage-mode all-pass filter as a true-time-delay cell. The proposed true-time-delay cell is capable of tuning delay, demonstrating its potential capability to be used in different systems, e.g., RF beam-formers. The proposed filter achieves a flat group delay of over 60 ps with a pole/zero pair located at 5 GHz. This proposed circuit consumes only 10 mW power from a 1.8-V supply. To demonstrate the performance of the proposed all-pass filter, simulation results are conducted by using Virtuoso Cadence in a standard TSMC 180-nm CMOS process. Full article

(This article belongs to the Special Issue Signal Processing and Analysis of Electrical Circuit)

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12 pages, 1495 KiB

Open AccessFeature PaperArticle

An 11 GHz Dual-Sided Self-Calibrating Dynamic Comparator in 28 nm CMOS

by Athanasios Ramkaj, Maarten Strackx, Michiel Steyaert and Filip Tavernier

Electronics 2019, 8(1), 13; https://0-doi-org.brum.beds.ac.uk/10.3390/electronics8010013 - 21 Dec 2018

Cited by 7 | Viewed by 5085

Abstract

This paper demonstrates a high-speed, low-noise dynamic comparator, employing self-calibration. The proposed dual-sided, fully-dynamic offset calibration is able to reduce the input-referred offset voltage by a factor of ten compared to the uncalibrated value without any speed or noise penalty and with less [...] Read more.

This paper demonstrates a high-speed, low-noise dynamic comparator, employing self-calibration. The proposed dual-sided, fully-dynamic offset calibration is able to reduce the input-referred offset voltage by a factor of ten compared to the uncalibrated value without any speed or noise penalty and with less than 5% power overhead. Moreover, the implemented multi-stage topology significantly advances the state-of-the-art comparator performance, achieving the highest reported operating frequency, as well as the lowest delay slope and sensitivity to supply and common mode variations compared to existing works, with similar energy/comparison. This makes the proposed self-calibrating comparator an ideal candidate for high resolution (>10 b) multi-GHz Analog-to-Digital Converters (ADCs). The 28 nm bulk CMOS prototype measures an input-referred noise and calibrated offset of

0.82

mV and

0.99

mV, respectively clocked at 11 GHz, consuming only

0.89

mW from a 1 V supply, for an area of 0.00054 mm², including calibration. Full article

(This article belongs to the Special Issue Signal Processing and Analysis of Electrical Circuit)

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18 pages, 4437 KiB

Open AccessArticle

High-Linearity Self-Biased CMOS Current Buffer

by Javier Alejandro Martínez-Nieto, María Teresa Sanz-Pascual, Nicolás Medrano-Marqués, Belén Calvo-López and Arturo Sarmiento-Reyes

Electronics 2018, 7(12), 423; https://0-doi-org.brum.beds.ac.uk/10.3390/electronics7120423 - 11 Dec 2018

Cited by 2 | Viewed by 4749

Abstract

A highly linear fully self-biased class AB current buffer designed in a standard 0.18

μ

m CMOS process with 1.8 V power supply is presented in this paper. It is a simple structure that, with a static power consumption of 48

μ

W, [...] Read more.

A highly linear fully self-biased class AB current buffer designed in a standard 0.18

μ

m CMOS process with 1.8 V power supply is presented in this paper. It is a simple structure that, with a static power consumption of 48

μ

W, features an input resistance as low as

89 Ω

, high accuracy in the input–output current ratio and total harmonic distortion (THD) figures lower than −60 dB at 30

μ

A amplitude signal and 1 kHz frequency. Robustness was proved through Monte Carlo and corner simulations, and finally validated through experimental measurements, showing that the proposed configuration is a suitable choice for high performance low voltage low power applications. Full article

(This article belongs to the Special Issue Signal Processing and Analysis of Electrical Circuit)

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13 pages, 4456 KiB

Open AccessArticle

Demodulation of Angular Position and Velocity from Resolver Signals via Chebyshev Filter-Based Type III Phase Locked Loop

by Huan Liu and Zhong Wu

Electronics 2018, 7(12), 354; https://0-doi-org.brum.beds.ac.uk/10.3390/electronics7120354 - 25 Nov 2018

Cited by 10 | Viewed by 7045

Abstract

A high-accuracy demodulation algorithm is required to estimate angular position and angular velocity from resolver signals. In order to improve the estimation accuracy of conventional phase-locked loop (PLL) based demodulation method, a Chebyshev filter-based type III PLL method is proposed in this paper. [...] Read more.

A high-accuracy demodulation algorithm is required to estimate angular position and angular velocity from resolver signals. In order to improve the estimation accuracy of conventional phase-locked loop (PLL) based demodulation method, a Chebyshev filter-based type III PLL method is proposed in this paper. The proposed method makes PLL become a system of type III tracking loop, which could greatly reduce the theoretical constant deviation in the estimation results of conventional type II PLL in case of variable speed. Meanwhile, the eigenvalues of type III PLL are placed to be the same position as those of a Chebyshev low-pass filter. In this way, demodulation parameters with stronger filter properties can be obtained to effectively suppress the high-frequency measurement noise in resolver signals. Thus, the proposed method can achieve higher demodulation precision compared with the conventional ones. Simulations and experiments are performed to validate the proposed demodulation method. Full article

(This article belongs to the Special Issue Signal Processing and Analysis of Electrical Circuit)

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14 pages, 10042 KiB

Open AccessArticle

An Accurate DDS Method Using Compound Frequency Tuning Word and Its FPGA Implementation

by Yuqing Hou, Changlong Li and Sheng Tang

Electronics 2018, 7(11), 330; https://0-doi-org.brum.beds.ac.uk/10.3390/electronics7110330 - 16 Nov 2018

Cited by 4 | Viewed by 5243

Abstract

Because of its high resolution, low cost, small volume, low power dissipation and less conversion time consumption, the direct digital synthesizer (DDS) method has been applied more and more in the fields of frequency synthesis and signal generation. However, only a limited number [...] Read more.

Because of its high resolution, low cost, small volume, low power dissipation and less conversion time consumption, the direct digital synthesizer (DDS) method has been applied more and more in the fields of frequency synthesis and signal generation. However, only a limited number of precise frequency signals can be synthesized by the traditional DDS, for the reason that its accumulator modulus is fixed, and its frequency tuning word must be integer. In this paper, a precise DDS method using compound frequency tuning word is proposed, which improves the accuracy of synthesized signals at any frequency points on the premise of guaranteeing the stability of synthesized signals. In order to verify the effectiveness of the new method, a DDS frequency synthesizer based on FPGA is designed and implemented. Taking the rubidium atomic clock PRS10 as standard frequency source, the experiments shows that the frequency stability of the synthesized signal is better than 8.0 × 10⁻¹²/s, the relative frequency error is less than 4.8 × 10⁻¹², and that the frequency accuracy is improved by three orders of magnitude compared with the traditional DDS method. Full article

(This article belongs to the Special Issue Signal Processing and Analysis of Electrical Circuit)

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24 pages, 3929 KiB

Open AccessFeature PaperArticle

Hardware Considerations for Tensor Implementation and Analysis Using the Field Programmable Gate Array

by Ian Grout and Lenore Mullin

Electronics 2018, 7(11), 320; https://0-doi-org.brum.beds.ac.uk/10.3390/electronics7110320 - 13 Nov 2018

Cited by 7 | Viewed by 4376

Abstract

In today’s complex embedded systems targeting internet of things (IoT) applications, there is a greater need for embedded digital signal processing algorithms that can effectively and efficiently process complex data sets. A typical application considered is for use in supervised and unsupervised machine [...] Read more.

In today’s complex embedded systems targeting internet of things (IoT) applications, there is a greater need for embedded digital signal processing algorithms that can effectively and efficiently process complex data sets. A typical application considered is for use in supervised and unsupervised machine learning systems. With the move towards lower power, portable, and embedded hardware-software platforms that meet the current and future needs for such applications, there is a requirement on the design and development communities to consider different approaches to design realization and implementation. Typical approaches are based on software programmed processors that run the required algorithms on a software operating system. Whilst such approaches are well supported, they can lead to solutions that are not necessarily optimized for a particular problem. A consideration of different approaches to realize a working system is therefore required, and hardware based designs rather than software based designs can provide performance benefits in terms of power consumption and processing speed. In this paper, consideration is given to utilizing the field programmable gate array (FPGA) to implement a combined inner and outer product algorithm in hardware that utilizes the available hardware resources within the FPGA. These products form the basis of tensor analysis operations that underlie the data processing algorithms in many machine learning systems. Full article

(This article belongs to the Special Issue Signal Processing and Analysis of Electrical Circuit)

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21 pages, 9147 KiB

Open AccessArticle

Acoustic-Based Fault Diagnosis of Commutator Motor

by Adam Glowacz

Electronics 2018, 7(11), 299; https://0-doi-org.brum.beds.ac.uk/10.3390/electronics7110299 - 05 Nov 2018

Cited by 66 | Viewed by 4849

Abstract

In the paper, the author presents acoustic-based fault diagnosis of a commutator motor (CM). Five states of the commutator motor were considered: healthy commutator motor, commutator motor with broken rotor coil, commutator motor with shorted stator coils, commutator motor with broken tooth on [...] Read more.

In the paper, the author presents acoustic-based fault diagnosis of a commutator motor (CM). Five states of the commutator motor were considered: healthy commutator motor, commutator motor with broken rotor coil, commutator motor with shorted stator coils, commutator motor with broken tooth on sprocket, commutator motor with damaged gear train. A method of feature extraction MSAF-15-MULTIEXPANDED-8-GROUPS (Method of Selection of Amplitudes of Frequency Multiexpanded 8 Groups) was described and implemented. Classification methods, such as nearest neighbour (NN), nearest mean (NM), self-organizing map (SOM), backpropagation neural network (BNN) were used for acoustic analysis of the commutator motor. The paper provides results of acoustic analysis of the commutator motor. The results had a good recognition rate. The results of acoustic analysis were in the range of 88.4–94.6%. The NM classifier and the MSAF-15-MULTIEXPANDED-8-GROUPS provided TE_RCM = 94.6%. Full article

(This article belongs to the Special Issue Signal Processing and Analysis of Electrical Circuit)

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13 pages, 10099 KiB

Open AccessArticle

Seismic Random Noise Attenuation Method Based on Variational Mode Decomposition and Correlation Coefficients

by Yaping Huang, Hanyong Bao and Xuemei Qi

Electronics 2018, 7(11), 280; https://0-doi-org.brum.beds.ac.uk/10.3390/electronics7110280 - 28 Oct 2018

Cited by 15 | Viewed by 3710

Abstract

Seismic data is easily affected by random noise during field data acquisition. Therefore, random noise attenuation plays an important role in seismic data processing and interpretation. According to decomposition characteristics of seismic signals by using variational mode decomposition (VMD) and the constraint conditions [...] Read more.

Seismic data is easily affected by random noise during field data acquisition. Therefore, random noise attenuation plays an important role in seismic data processing and interpretation. According to decomposition characteristics of seismic signals by using variational mode decomposition (VMD) and the constraint conditions of correlation coefficients, this paper puts forward a method for random noise attenuation in seismic data, which is called variational mode decomposition correlation coefficients VMDC. Firstly, the original signals were decomposed into intrinsic mode functions (IMFs) with different characteristics by VMD. Then, the correlation coefficients between each IMF and the original signal were calculated. Next, based on the differences among correlation coefficients of effective signals and random noise as well as the original signals, the corresponding treatment was carried out, and the effective signals were reconstructed. Finally, the random noise attenuation was realized. After adding random noise to simple sine signals and the synthetic seismic record, the improved complementary ensemble empirical mode decomposition (ICEEMD) and VMDC were used for testing. The testing results indicate that the proposed VMDC has better random noise attenuation effects. It was also used in real-world seismic data noise attenuation. The results also show that it could effectively improve the signal-to-noise ratio (SNR) of seismic data and could provide high-quality basic data for further interpretation of seismic data. Full article

(This article belongs to the Special Issue Signal Processing and Analysis of Electrical Circuit)

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