Special Issue "Low Power Memory/Memristor Devices and Systems"

Special Issue Editors

Dr. Alex Serb
E-Mail Website
Guest Editor
Department of Electronics and Computer Science (ECS), University of Southampton, Southampton SO17 1BJ, UK
Interests: electronic circuits; neuromorphic engineering; computational neuroscience
Dr. Adnan Mehonic
E-Mail Website
Guest Editor
Department of Electronic & Electrical Engineering, University College London, London WC1E 7JE, UK
Interests: functional materials; nanoelectronics; memristors; energy-efficient novel computing paradigms

Special Issue Information

Dear Colleagues,

The continuing proliferation of AI is underpinning an intense interest in hardware development targeting the specific needs of AI computation. Part of the problem lies in the large memory requirements of systems employing millions of weights that are constantly being used to compute outputs. This places an enormous strain on both memory technology, which has to provide cheaper-better-faster memory, and on the Von Neumann architecture, which attempts to solve the problem by squeezing ever more data through an ever tighter pipeline.

The solution to this problem is not simple and encompasses many fields. Over the last few years, it has become clear that one such field is that of emerging memory technologies. By enlisting the help of nanotechnology, engineers are pushing the boundaries of the energy efficiency of memories in a race to the next generation of memory. Much like FLASH memory once upset a world dominated by magnetic memory, these days a multitude of emerging technologies (often collectively referred to as “memristors”) are vying to earn a place in the mainstream memory landscape, promising ultra-low power and area footprints.

This Special Issue will bring together excellent and inspiring work currently being undertaken in the area of low power memory including the following:

  • Demonstrations of novel memory devices exhibiting exemplary performance (especially low power operation).
  • Novel memory circuits and systems (specifically designed to efficiently incorporate/leverage the benefits of novel nanotechnology).
  • Other circuits and systems demonstrating the use of ultra-efficient memory (especially describing what was required in order to successfully implement or incorporate such memory into the system).

Naturally, this list is not exhaustive or exclusive and any contributions that pave the way towards the future of efficient memory are welcome.

We hope that you will contribute your work to this issue and help map the recent progress of memory technology and techniques.

Dr. Alex Serb
Dr. Adnan Mehonic
Guest Editor

Manuscript Submission Information

Manuscripts should be submitted online at www.mdpi.com by registering and logging in to this website. Once you are registered, click here to go to the submission form. Manuscripts can be submitted until the deadline. All papers will be peer-reviewed. Accepted papers will be published continuously in the journal (as soon as accepted) and will be listed together on the special issue website. Research articles, review articles as well as short communications are invited. For planned papers, a title and short abstract (about 100 words) can be sent to the Editorial Office for announcement on this website.

Submitted manuscripts should not have been published previously, nor be under consideration for publication elsewhere (except conference proceedings papers). All manuscripts are thoroughly refereed through a single-blind peer-review process. A guide for authors and other relevant information for submission of manuscripts is available on the Instructions for Authors page. Journal of Low Power Electronics and Applications is an international peer-reviewed open access quarterly journal published by MDPI.

Please visit the Instructions for Authors page before submitting a manuscript. The Article Processing Charge (APC) for publication in this open access journal is 1400 CHF (Swiss Francs). Submitted papers should be well formatted and use good English. Authors may use MDPI's English editing service prior to publication or during author revisions.

Keywords

  • Low power memory
  • Memory circuits
  • Memristors
  • AI hardware

Published Papers (7 papers)

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Research

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Article
A New Physical Design Flow for a Selective State Retention Based Approach
J. Low Power Electron. Appl. 2021, 11(3), 35; https://0-doi-org.brum.beds.ac.uk/10.3390/jlpea11030035 - 13 Sep 2021
Viewed by 433
Abstract
This research presents a novel approach for physical design implementation aimed for a System on Chip (SoC) based on Selective State Retention techniques. Leakage current has become a dominant factor in Very Large Scale Integration (VLSI) design. Power Gating (PG) techniques were first [...] Read more.
This research presents a novel approach for physical design implementation aimed for a System on Chip (SoC) based on Selective State Retention techniques. Leakage current has become a dominant factor in Very Large Scale Integration (VLSI) design. Power Gating (PG) techniques were first developed to mitigate these leakage currents, but they result in longer SoC wake-up periods due to loss of state. The common State Retention Power Gating (SRPG) approach was developed to overcome the PG technique’s loss of state drawback. However, SRPG resulted in a costly expense of die area overhead due to the additional state retention logic required to keep the design state when power is gated. Moreover, the physical design implementation of SRPG presents additional wiring due to the extra power supply network and power-gating controls for the state retention logic. This results in increased implementation complexity for the physical design tools, and therefore increases runtime and limits the ability to handle large designs. Recently published works on Selective State Retention Power Gating (SSRPG) techniques allow reducing the total amount of retention logic and their leakage currents. Although the SSRPG approach mitigates the overhead area and power limitations of the conventional SRPG technique, still both SRPG and SSRPG approaches require a similar extra power grid network for the retention cells, and the effect of the selective approach on the complexity of the physical design has not been yet investigated. Therefore, this paper introduces further analysis of the physical design flow for the SSRPG design, which is required for optimal cell placement and power grid allocation. This significantly increases the potential routing area, which directly improves the convergence time of the Place and Route tools. Full article
(This article belongs to the Special Issue Low Power Memory/Memristor Devices and Systems)
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Article
Energy-Efficient Non-Von Neumann Computing Architecture Supporting Multiple Computing Paradigms for Logic and Binarized Neural Networks
J. Low Power Electron. Appl. 2021, 11(3), 29; https://0-doi-org.brum.beds.ac.uk/10.3390/jlpea11030029 - 06 Jul 2021
Viewed by 875
Abstract
Different in-memory computing paradigms enabled by emerging non-volatile memory technologies are promising solutions for the development of ultra-low-power hardware for edge computing. Among these, SIMPLY, a smart logic-in-memory architecture, provides high reconfigurability and enables the in-memory computation of both logic operations and binarized [...] Read more.
Different in-memory computing paradigms enabled by emerging non-volatile memory technologies are promising solutions for the development of ultra-low-power hardware for edge computing. Among these, SIMPLY, a smart logic-in-memory architecture, provides high reconfigurability and enables the in-memory computation of both logic operations and binarized neural networks (BNNs) inference. However, operation-specific hardware accelerators can result in better performance for a particular task, such as the analog computation of the multiply and accumulate operation for BNN inference, but lack reconfigurability. Nonetheless, a solution providing the flexibility of SIMPLY while also achieving the high performance of BNN-specific analog hardware accelerators is missing. In this work, we propose a novel in-memory architecture based on 1T1R crossbar arrays, which enables the coexistence on the same crossbar array of both SIMPLY computing paradigm and the analog acceleration of the multiply and accumulate operation for BNN inference. We also highlight the main design tradeoffs and opportunities enabled by different emerging non-volatile memory technologies. Finally, by using a physics-based Resistive Random Access Memory (RRAM) compact model calibrated on data from the literature, we show that the proposed architecture improves the energy delay product by >103 times when performing a BNN inference task with respect to a SIMPLY implementation. Full article
(This article belongs to the Special Issue Low Power Memory/Memristor Devices and Systems)
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Article
Minimization of the Line Resistance Impact on Memdiode-Based Simulations of Multilayer Perceptron Arrays Applied to Pattern Recognition
J. Low Power Electron. Appl. 2021, 11(1), 9; https://0-doi-org.brum.beds.ac.uk/10.3390/jlpea11010009 - 05 Feb 2021
Cited by 2 | Viewed by 1018
Abstract
In this paper, we extend the application of the Quasi-Static Memdiode model to the realistic SPICE simulation of memristor-based single (SLPs) and multilayer perceptrons (MLPs) intended for large dataset pattern recognition. By considering ex-situ training and the classification of the hand-written characters of [...] Read more.
In this paper, we extend the application of the Quasi-Static Memdiode model to the realistic SPICE simulation of memristor-based single (SLPs) and multilayer perceptrons (MLPs) intended for large dataset pattern recognition. By considering ex-situ training and the classification of the hand-written characters of the MNIST database, we evaluate the degradation of the inference accuracy due to the interconnection resistances for MLPs involving up to three hidden neural layers. Two approaches to reduce the impact of the line resistance are considered and implemented in our simulations, they are the inclusion of an iterative calibration algorithm and the partitioning of the synaptic layers into smaller blocks. The obtained results indicate that MLPs are more sensitive to the line resistance effect than SLPs and that partitioning is the most effective way to minimize the impact of high line resistance values. Full article
(This article belongs to the Special Issue Low Power Memory/Memristor Devices and Systems)
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Article
A Morphable Physically Unclonable Function and True Random Number Generator Using a Commercial Magnetic Memory
J. Low Power Electron. Appl. 2021, 11(1), 5; https://0-doi-org.brum.beds.ac.uk/10.3390/jlpea11010005 - 14 Jan 2021
Cited by 1 | Viewed by 908
Abstract
We use commercial magnetic memory to realize morphable security primitives, a Physically Unclonable Function (PUF) and a True Random Number Generator (TRNG). The PUF realized by manipulating the write time and the TRNG is realized by tweaking the number of write pulses. Our [...] Read more.
We use commercial magnetic memory to realize morphable security primitives, a Physically Unclonable Function (PUF) and a True Random Number Generator (TRNG). The PUF realized by manipulating the write time and the TRNG is realized by tweaking the number of write pulses. Our analysis indicates that more than 75% bits in the PUF are unusable without any correction due to their inability to exhibit any randomness. We exploit temporal randomness of working columns to fix the unusable columns and write latency to fix the unusable rows during the enrollment. The intra-HD, inter-HD, energy, bandwidth and area of the proposed PUF are found to be 0, 46.25%, 0.14 pJ/bit, 0.34 Gbit/s and 0.385 μm2/bit (including peripherals) respectively. The proposed TRNG provides all possible outcomes with a standard deviation of 0.0062, correlation coefficient of 0.05 and an entropy of 0.95. The energy, bandwidth and area of the proposed TRNG is found to be 0.41 pJ/bit, 0.12 Gbit/s and 0.769 μm2/bit (including peripherals). The performance of the proposed TRNG has also been tested with NIST test suite. The proposed designs are compared with other magnetic PUFs and TRNGs from other literature. Full article
(This article belongs to the Special Issue Low Power Memory/Memristor Devices and Systems)
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Article
Continuous-Time Programming of Floating-Gate Transistors for Nonvolatile Analog Memory Arrays
J. Low Power Electron. Appl. 2021, 11(1), 4; https://0-doi-org.brum.beds.ac.uk/10.3390/jlpea11010004 - 13 Jan 2021
Cited by 1 | Viewed by 899
Abstract
Floating-gate (FG) transistors are a primary means of providing nonvolatile digital memory in standard CMOS processes, but they are also key enablers for large-scale programmable analog systems, as well. Such programmable analog systems are often designed for battery-powered and resource-constrained applications, which require [...] Read more.
Floating-gate (FG) transistors are a primary means of providing nonvolatile digital memory in standard CMOS processes, but they are also key enablers for large-scale programmable analog systems, as well. Such programmable analog systems are often designed for battery-powered and resource-constrained applications, which require the memory cells to program quickly and with low infrastructural overhead. To meet these needs, we present a four-transistor analog floating-gate memory cell that offers both voltage and current outputs and has linear programming characteristics. Furthermore, we present a simple programming circuit that forces the memory cell to converge to targets with 13.0 bit resolution. Finally, we demonstrate how to use the FG memory cell and the programmer circuit in array configurations. We show how to program an array in either a serial or parallel fashion and demonstrate the effectiveness of the array programming with an application of a bandpass filter array. Full article
(This article belongs to the Special Issue Low Power Memory/Memristor Devices and Systems)
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Article
Logic-in-Memory Computation: Is It Worth It? A Binary Neural Network Case Study
J. Low Power Electron. Appl. 2020, 10(1), 7; https://0-doi-org.brum.beds.ac.uk/10.3390/jlpea10010007 - 22 Feb 2020
Cited by 2 | Viewed by 3343
Abstract
Recently, the Logic-in-Memory (LiM) concept has been widely studied in the literature. This paradigm represents one of the most efficient ways to solve the limitations of a Von Neumann’s architecture: by placing simple logic circuits inside or near a memory element, it is [...] Read more.
Recently, the Logic-in-Memory (LiM) concept has been widely studied in the literature. This paradigm represents one of the most efficient ways to solve the limitations of a Von Neumann’s architecture: by placing simple logic circuits inside or near a memory element, it is possible to obtain a local computation without the need to fetch data from the main memory. Although this concept introduces a lot of advantages from a theoretical point of view, its implementation could introduce an increasing complexity overhead of the memory itself, leading to a more sophisticated design flow. As a case study, Binary Neural Networks (BNNs) have been chosen. BNNs binarize both weights and inputs, transforming multiply-and-accumulate into a simpler bitwise logical operation while maintaining high accuracy, making them well-suited for a LiM implementation. In this paper, we present two circuits implementing a BNN model in CMOS technology. The first one, called Out-Of-Memory (OOM) architecture, is implemented following a standard Von Neumann structure. The same architecture was redesigned to adapt the critical part of the algorithm for a modified memory, which is also capable of executing logic calculations. By comparing both OOM and LiM architectures we aim to evaluate if Logic-in-Memory paradigm is worth it. The results highlight that LiM architectures have a clear advantage over Von Neumann architectures, allowing a reduction in energy consumption while increasing the overall speed of the circuit. Full article
(This article belongs to the Special Issue Low Power Memory/Memristor Devices and Systems)
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Review

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Review
Rediscovering Majority Logic in the Post-CMOS Era: A Perspective from In-Memory Computing
J. Low Power Electron. Appl. 2020, 10(3), 28; https://0-doi-org.brum.beds.ac.uk/10.3390/jlpea10030028 - 04 Sep 2020
Cited by 4 | Viewed by 2097
Abstract
As we approach the end of Moore’s law, many alternative devices are being explored to satisfy the performance requirements of modern integrated circuits. At the same time, the movement of data between processing and memory units in contemporary computing systems (‘von Neumann bottleneck’ [...] Read more.
As we approach the end of Moore’s law, many alternative devices are being explored to satisfy the performance requirements of modern integrated circuits. At the same time, the movement of data between processing and memory units in contemporary computing systems (‘von Neumann bottleneck’ or ‘memory wall’) necessitates a paradigm shift in the way data is processed. Emerging resistance switching memories (memristors) show promising signs to overcome the ‘memory wall’ by enabling computation in the memory array. Majority logic is a type of Boolean logic which has been found to be an efficient logic primitive due to its expressive power. In this review, the efficiency of majority logic is analyzed from the perspective of in-memory computing. Recently reported methods to implement majority gate in Resistive RAM array are reviewed and compared. Conventional CMOS implementation accommodated heterogeneity of logic gates (NAND, NOR, XOR) while in-memory implementation usually accommodates homogeneity of gates (only IMPLY or only NAND or only MAJORITY). In view of this, memristive logic families which can implement MAJORITY gate and NOT (to make it functionally complete) are to be favored for in-memory computing. One-bit full adders implemented in memory array using different logic primitives are compared and the efficiency of majority-based implementation is underscored. To investigate if the efficiency of majority-based implementation extends to n-bit adders, eight-bit adders implemented in memory array using different logic primitives are compared. Parallel-prefix adders implemented in majority logic can reduce latency of in-memory adders by 50–70% when compared to IMPLY, NAND, NOR and other similar logic primitives. Full article
(This article belongs to the Special Issue Low Power Memory/Memristor Devices and Systems)
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Planned Papers

The below list represents only planned manuscripts. Some of these manuscripts have not been received by the Editorial Office yet. Papers submitted to MDPI journals are subject to peer-review.

Review on the basic circuit elements and memristor interpretation: Analysis, Technology and Applications

Authors: Aliyu Isah, Aurélien Serge Tchakoutio Nguetcho, Stéphane Binczak and Jean-Marie Bilbault

Abstract: Circuit elements or electronic components are useful elements allowing us to realize different circuit functionalities. Resistor, capacitor and inductor are the three commonly known passive circuit elements owing to their fundamental nature that relate them to the four circuit variables, namely voltage, magnetic flux, current and electric charge. The memory resistor (or memristor) was claimed to be the fourth basic passive circuit element, complementing resistor, capacitor and inductor. This paper presents a review on the four basic passive circuit elements. We present briefly the first three known basic passive circuit elements and then follow by thorough description of memristor. Memristor sparks interest in the scientific community due to its some interesting features, for example nano-scalability, memory capability, conductance modulation, connection flexibility and compatibility with CMOS technology, etc... These features among many others are highly demanded in the present industrial scale. For this reason, thousands of memristor-based applications are reported. Hence, we present the philosophical argumentations of memristor, technologies and applications.

Keywords: Circuit elements, circuit variables, memristor, argumentation, analysis, technology, modeling, applications

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