Research

12 pages, 3929 KiB

Open AccessArticle

The Influence of Special Environments on SiC MOSFETs

by Zhigang Li, Jie Jiang, Zhiyuan He, Shengdong Hu, Yijun Shi, Zhenbo Zhao, Yigang He, Yiqiang Chen and Guoguang Lu

Materials 2023, 16(18), 6193; https://0-doi-org.brum.beds.ac.uk/10.3390/ma16186193 - 13 Sep 2023

Viewed by 806

Abstract

In this work, the influences of special environments (hydrogen gas and high temperature, high humidity environments) on the performance of three types of SiC MOSFETs are investigated. The results reveal several noteworthy observations. Firstly, after 500 h in a hydrogen gas environment, all [...] Read more.

In this work, the influences of special environments (hydrogen gas and high temperature, high humidity environments) on the performance of three types of SiC MOSFETs are investigated. The results reveal several noteworthy observations. Firstly, after 500 h in a hydrogen gas environment, all the SiC MOSFETs exhibited a negative drift in threshold voltage, accompanied by an increase in maximum transconductance and drain current (@ V_GS/V_DS = 13 V/3 V). This phenomenon can be attributed to that the hydrogen atoms can increase the positive fixed charges in the oxide and increase the electron mobility in the channel. In addition, high temperature did not intensify the impact of hydrogen on the devices and electron mobility. Instead, prolonged exposure to high temperatures may induce stress on the SiO₂/SiC interface, leading to a decrease in electron mobility, subsequently reducing the transconductance and drain current (@ V_GS/V_DS = 13 V/3 V). The high temperature, high humidity environment can cause a certain negative drift in the devices’ threshold voltage. With the increasing duration of the experiment, the maximum transconductance and drain current (@ V_GS/V_DS = 18V (20 V)/3 V) gradually decreased. This may be because the presence of moisture can lead to corrosion of the devices’ metal contacts and interconnects, which can increase the devices’ resistance and lead to a decrease in the devices’ maximum transconductance and drain current. Full article

(This article belongs to the Special Issue Wide Bandgap Semiconductor Materials and Devices)

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11 pages, 1383 KiB

Open AccessEditor’s ChoiceArticle

Examining the Effect of Cu and Mn Dopants on the Structure of Zinc Blende ZnS Nanopowders

by Alexei Kuzmin, Inga Pudza, Milena Dile, Katrina Laganovska and Aleksejs Zolotarjovs

Materials 2023, 16(17), 5825; https://0-doi-org.brum.beds.ac.uk/10.3390/ma16175825 - 25 Aug 2023

Cited by 1 | Viewed by 973

Abstract

It is known that doping zinc sulfide (ZnS) nanoparticles with Mn or Cu ions significantly affects their luminescent properties. Herein, we investigated how dopant atoms are incorporated into the structure of ZnS using X-ray diffraction and multi-edge X-ray absorption spectroscopy. The observed broadening [...] Read more.

It is known that doping zinc sulfide (ZnS) nanoparticles with Mn or Cu ions significantly affects their luminescent properties. Herein, we investigated how dopant atoms are incorporated into the structure of ZnS using X-ray diffraction and multi-edge X-ray absorption spectroscopy. The observed broadening of the X-ray diffraction patterns indicates an average crystallite size of about 6 nm. By analyzing the Zn, Mn, and Cu K-edge extended X-ray absorption fine structure (EXAFS) spectra using the reverse Monte Carlo method, we were able to determine the relaxations of the local environments around the dopants. Our findings suggested that upon the substitution of Zn by Mn or Cu ions, there is a shortening of the Cu–S bonds by 0.08 Å, whereas the Mn–S bonds exhibited lengthening by 0.07 Å. These experimental results were further confirmed by first-principles density functional theory calculations, which explained the increase in the Mn–S bond lengths due to the high-spin state of Mn

^{2 +}

ions. Full article

(This article belongs to the Special Issue Wide Bandgap Semiconductor Materials and Devices)

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14 pages, 6823 KiB

Open AccessArticle

Analysis for DC and RF Characteristics Recessed-Gate GaN MOSFET Using Stacked TiO₂/Si₃N₄ Dual-Layer Insulator

by So-Ra Min, Min-Su Cho, Sang-Ho Lee, Jin Park, Hee-Dae An, Geon-Uk Kim, Young-Jun Yoon, Jae-Hwa Seo, Jae-Won Jang, Jin-Hyuk Bae, Sin-Hyung Lee and In-Man Kang

Materials 2022, 15(3), 819; https://0-doi-org.brum.beds.ac.uk/10.3390/ma15030819 - 21 Jan 2022

Cited by 3 | Viewed by 2477

Abstract

The self-heating effects (SHEs) on the electrical characteristics of the GaN MOSFETs with a stacked TiO₂/Si₃N₄ dual-layer insulator are investigated by using rigorous TCAD simulations. To accurately analyze them, the GaN MOSFETs with Si₃N₄ single-layer [...] Read more.

The self-heating effects (SHEs) on the electrical characteristics of the GaN MOSFETs with a stacked TiO₂/Si₃N₄ dual-layer insulator are investigated by using rigorous TCAD simulations. To accurately analyze them, the GaN MOSFETs with Si₃N₄ single-layer insulator are conducted to the simulation works together. The stacked TiO₂/Si₃N₄ GaN MOSFET has a maximum on-state current of 743.8 mA/mm, which is the improved value due to the larger oxide capacitance of TiO₂/Si₃N₄ than that of a Si₃N₄ single-layer insulator. However, the electrical field and current density increased by the stacked TiO₂/Si₃N₄ layers make the device’s temperature higher. That results in the degradation of the device’s performance. We simulated and analyzed the operation mechanisms of the GaN MOSFETs modulated by the SHEs in view of high-power and high-frequency characteristics. The maximum temperature inside the device was increased to 409.89 K by the SHEs. In this case, the stacked TiO₂/Si₃N₄-based GaN MOSFETs had 25%-lower values for both the maximum on-state current and the maximum transconductance compared with the device where SHEs did not occur; R_on increased from 1.41 mΩ·cm² to 2.56 mΩ·cm², and the cut-off frequency was reduced by 26% from 5.45 GHz. Although the performance of the stacked TiO₂/Si₃N₄-based GaN MOSFET is degraded by SHEs, it shows superior electrical performance than GaN MOSFETs with Si₃N₄ single-layer insulator. Full article

(This article belongs to the Special Issue Wide Bandgap Semiconductor Materials and Devices)

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10 pages, 3289 KiB

Open AccessFeature PaperArticle

Simulation Study of the Use of AlGaN/GaN Ultra-Thin-Barrier HEMTs with Hybrid Gates for Achieving a Wide Threshold Voltage Modulation Range

by Shouyi Wang, Qi Zhou, Kuangli Chen, Pengxiang Bai, Jinghai Wang, Liyang Zhu, Chunhua Zhou, Wei Gao and Bo Zhang

Materials 2022, 15(2), 654; https://0-doi-org.brum.beds.ac.uk/10.3390/ma15020654 - 15 Jan 2022

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Abstract

In this work, novel hybrid gate Ultra-Thin-Barrier HEMTs (HG-UTB HEMTs) featuring a wide modulation range of threshold voltages (V_TH) are proposed. The hybrid gate structure consists of a p-GaN gate part and a MIS-gate part. Due to the depletion effect [...] Read more.

In this work, novel hybrid gate Ultra-Thin-Barrier HEMTs (HG-UTB HEMTs) featuring a wide modulation range of threshold voltages (V_TH) are proposed. The hybrid gate structure consists of a p-GaN gate part and a MIS-gate part. Due to the depletion effect assisted by the p-GaN gate part, the V_TH of HG-UTB HEMTs can be significantly increased. By tailoring the hole concentration of the p-GaN gate, the V_TH can be flexibly modulated from 1.63 V to 3.84 V. Moreover, the MIS-gate part enables the effective reduction in the electric field (E-field) peak at the drain-side edge of the p-GaN gate, which reduces the potential gate degradation originating from the high E-field in the p-GaN gate. Meanwhile, the HG-UTB HEMTs exhibit a maximum drain current as high as 701 mA/mm and correspond to an on-resistance of 10.1 Ω mm and a breakdown voltage of 610 V. The proposed HG-UTB HEMTs are a potential means to achieve normally off GaN HEMTs with a promising device performance and featuring a flexible V_TH modulation range, which is of great interest for versatile power applications. Full article

(This article belongs to the Special Issue Wide Bandgap Semiconductor Materials and Devices)

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15 pages, 258109 KiB

Open AccessArticle

Investigation of SiC Trench MOSFETs’ Reliability under Short-Circuit Conditions

by Yuan Zou, Jue Wang, Hongyi Xu and Hengyu Wang

Materials 2022, 15(2), 598; https://0-doi-org.brum.beds.ac.uk/10.3390/ma15020598 - 13 Jan 2022

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Abstract

In this paper, the short-circuit robustness of 1200 V silicon carbide (SiC) trench MOSFETs with different gate structures has been investigated. The MOSFETs exhibited different failure modes under different DC bus voltages. For double trench SiC MOSFETs, failure modes are gate failure at [...] Read more.

In this paper, the short-circuit robustness of 1200 V silicon carbide (SiC) trench MOSFETs with different gate structures has been investigated. The MOSFETs exhibited different failure modes under different DC bus voltages. For double trench SiC MOSFETs, failure modes are gate failure at lower dc bus voltages and thermal runaway at higher dc bus voltages, while failure modes for asymmetric trench SiC MOSFETs are soft failure and thermal runaway, respectively. The shortcircuit withstanding time (SCWT) of the asymmetric trench MOSFET is higher than that of the double trench MOSFETs. The thermal and mechanical stresses inside the devices during the short-circuit tests have been simulated to probe into the failure mechanisms and reveal the impact of the device structures on the device reliability. Finally, post-failure analysis has been carried out to verify the root causes of the device failure. Full article

(This article belongs to the Special Issue Wide Bandgap Semiconductor Materials and Devices)

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11 pages, 2919 KiB

Open AccessArticle

Influence of Different Device Structures on the Degradation for Trench-Gate SiC MOSFETs: Taking Avalanche Stress as an Example

by Zhaoxiang Wei, Hao Fu, Xiaowen Yan, Sheng Li, Long Zhang, Jiaxing Wei, Siyang Liu, Weifeng Sun, Weili Wu and Song Bai

Materials 2022, 15(2), 457; https://0-doi-org.brum.beds.ac.uk/10.3390/ma15020457 - 08 Jan 2022

Cited by 1 | Viewed by 2845

Abstract

The variations in the degradation of electrical characteristics resulting from different device structures for trench-gate SiC metal-oxide-semiconductor field effect transistors (MOSFETs) are investigated in this work. Two types of the most advanced commercial trench products, which are the asymmetric trench SiC MOSFET and [...] Read more.

The variations in the degradation of electrical characteristics resulting from different device structures for trench-gate SiC metal-oxide-semiconductor field effect transistors (MOSFETs) are investigated in this work. Two types of the most advanced commercial trench products, which are the asymmetric trench SiC MOSFET and the double-trench SiC MOSFET, are chosen as the targeted devices. The discrepant degradation trends caused by the repetitive avalanche stress are monitored. For the double-trench device, the conduction characteristic improves while the gate-drain capacitance (C_gd) increases seriously. It is because positive charges are injected into the bottom gate oxide during the avalanche process, which are driven by the high oxide electronic field (E_ox) and the high impact ionization rate (I.I.) there. Meanwhile, for the asymmetric trench SiC MOSFET, the I–V curve under the high gate bias condition and the C_gd remain relatively stable, while the trench bottom is well protected by the deep P+ well. However, it’s threshold voltage (V_th) decreases more obviously when compared with that of the double-trench device and the inclined channel suffers from more serious stress than the vertical channel. Positive charges are more easily injected into the inclined channel. The phenomena and the corresponding mechanisms are analyzed and proved by experiments and technology computer-aided design (TCAD) simulations. Full article

(This article belongs to the Special Issue Wide Bandgap Semiconductor Materials and Devices)

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10 pages, 2788 KiB

Open AccessArticle

SiC Fin-Shaped Gate Trench MOSFET with Integrated Schottky Diode

by Xiaochuan Deng, Rui Liu, Songjun Li, Ling Li, Hao Wu and Xuan Li

Materials 2021, 14(22), 7096; https://0-doi-org.brum.beds.ac.uk/10.3390/ma14227096 - 22 Nov 2021

Cited by 1 | Viewed by 2154

Abstract

A silicon carbide (SiC) trench MOSFET featuring fin-shaped gate and integrated Schottky barrier diode under split P type shield (SPS) protection (FS-TMOS) is proposed by finite element modeling. The physical mechanism of FS-TMOS is studied comprehensively in terms of fundamental (blocking, conduction, and [...] Read more.

A silicon carbide (SiC) trench MOSFET featuring fin-shaped gate and integrated Schottky barrier diode under split P type shield (SPS) protection (FS-TMOS) is proposed by finite element modeling. The physical mechanism of FS-TMOS is studied comprehensively in terms of fundamental (blocking, conduction, and dynamic) performance and transient extreme stress reliability. The fin-shaped gate on the sidewall of the trench and integrated Schottky diode at the bottom of trench aim to the reduction of gate charge and improvement on the third quadrant performance, respectively. The SPS region is fully utilized to suppress excessive electric field both at trench oxide and Schottky contact when OFF-state. Compared with conventional trench MOSFET (C-TMOS), the gate charge, Miller charge, V_on at third quadrant, R_on,sp·Q_gd, and R_on,sp·Q_g of FS-TMOS are significantly reduced by 34%, 20%, 65%, 0.1%, and 14%, respectively. Furthermore, short-circuit and avalanche capabilities are discussed, verifying the FS-TMOS is more robust than C-TMOS. It suggests that the proposed FS-TMOS is a promising candidate for next-generation high efficiency and high-power density applications. Full article

(This article belongs to the Special Issue Wide Bandgap Semiconductor Materials and Devices)

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12 pages, 5672 KiB

Open AccessArticle

Micropipes in SiC Single Crystal Observed by Molten KOH Etching

by Hejing Wang, Jinying Yu, Guojie Hu, Yan Peng, Xuejian Xie, Xiaobo Hu, Xiufang Chen and Xiangang Xu

Materials 2021, 14(19), 5890; https://0-doi-org.brum.beds.ac.uk/10.3390/ma14195890 - 08 Oct 2021

Cited by 10 | Viewed by 3884

Abstract

Micropipe, a “killer” defect in SiC crystals, severely hampers the outstanding performance of SiC-based devices. In this paper, the etching behavior of micropipes in 4H-SiC and 6H-SiC wafers was studied using the molten KOH etching method. The spectra of 4H-SiC and 6H-SiC crystals [...] Read more.

Micropipe, a “killer” defect in SiC crystals, severely hampers the outstanding performance of SiC-based devices. In this paper, the etching behavior of micropipes in 4H-SiC and 6H-SiC wafers was studied using the molten KOH etching method. The spectra of 4H-SiC and 6H-SiC crystals containing micropipes were examined using Raman scattering. A new Raman peak accompanying micropipes located near −784 cm⁻¹ was observed, which may have been induced by polymorphic transformation during the etching process in the area of micropipe etch pits. This feature may provide a new way to distinguish micropipes from other defects. In addition, the preferable etching conditions for distinguishing micropipes from threading screw dislocations (TSDs) was determined using laser confocal microscopy, scanning electron microscopy (SEM) and optical microscopy. Meanwhile, the micropipe etching pits were classified into two types based on their morphology and formation mechanism. Full article

(This article belongs to the Special Issue Wide Bandgap Semiconductor Materials and Devices)

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