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Micromachines
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Advanced Interconnect and Packaging
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Advanced Interconnect and Packaging

A special issue of Micromachines (ISSN 2072-666X). This special issue belongs to the section "E：Engineering and Technology".

Deadline for manuscript submissions: closed (20 October 2022) | Viewed by 32931

Printed Edition Available!
A printed edition of this Special Issue is available here.

Special Issue Editor

Prof. Dr. Wensheng Zhao

E-Mail Website
Guest Editor
School of Electronics and Information, Hangzhou Dianzi University, Hangzhou 310018, China
Interests: interconnect; packaging; TSV; 3-D IC
Special Issues, Collections and Topics in MDPI journals

Special Issue Information

Dear Colleagues,

Unlike transistors, the continuous downscaling of feature size in CMOS technology leads to a dramatic rise in interconnect resistivity and concomitant performance degradation. At nanoscale technology nodes, interconnect delay and reliability become the major bottleneck faced by modern integrated circuits. To resolve these interconnect problems, various emerging technologies including airgap, nanocarbon, optical, and through-silicon via (TSV) have been proposed and investigated. For example, by virtue of TSV technology, dies can be stacked to increase the integration density. More importantly, 3D integration and packaging also offer the most promising platform to implement “More-than-Moore” technologies, providing heterogenous materials and technologies on a single chip.

This Special Issue seeks to showcase research papers, communications, and review articles on new developments in advanced interconnect and packaging, i.e., on the design, modeling, fabrication, and reliability assessment of emerging interconnect and packaging technologies.

We look forward to receiving your submissions!

Prof. Dr. Wensheng Zhao
Guest Editor

Manuscript Submission Information

Manuscripts should be submitted online at www.mdpi.com by registering and logging in to this website. Once you are registered, click here to go to the submission form. Manuscripts can be submitted until the deadline. All submissions that pass pre-check are peer-reviewed. Accepted papers will be published continuously in the journal (as soon as accepted) and will be listed together on the special issue website. Research articles, review articles as well as short communications are invited. For planned papers, a title and short abstract (about 100 words) can be sent to the Editorial Office for announcement on this website.

Submitted manuscripts should not have been published previously, nor be under consideration for publication elsewhere (except conference proceedings papers). All manuscripts are thoroughly refereed through a single-blind peer-review process. A guide for authors and other relevant information for submission of manuscripts is available on the Instructions for Authors page. Micromachines is an international peer-reviewed open access monthly journal published by MDPI.

Please visit the Instructions for Authors page before submitting a manuscript. The Article Processing Charge (APC) for publication in this open access journal is 2600 CHF (Swiss Francs). Submitted papers should be well formatted and use good English. Authors may use MDPI's English editing service prior to publication or during author revisions.

Keywords

  • Interconnect
    • On-chip interconnect
    • Through-silicon via (TSV)
    • Transmission line
  • advanced packaging
  • 3D integrated circuits and microsystems
  • Antenna in Packaging (AiP)
  • Integrated Passive Device (IPD)

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Published Papers (18 papers)

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Editorial

Jump to: Research, Review

3 pages, 175 KiB  
Editorial
Editorial for the Special Issue on Advanced Interconnect and Packaging
by Wen-Sheng Zhao
Micromachines 2023, 14(1), 171; https://0-doi-org.brum.beds.ac.uk/10.3390/mi14010171 - 10 Jan 2023
Cited by 1 | Viewed by 1042
Abstract
Unlike transistors, the continuous downscaling of feature size in CMOS technology leads to a dramatic rise in interconnect resistivity and concomitant performance degradation [...] Full article
(This article belongs to the Special Issue Advanced Interconnect and Packaging)

Research

Jump to: Editorial, Review

12 pages, 5292 KiB  
Article
Dynamic Enhancement for Dual Active Bridge Converter with a Deadbeat Current Controller
by Chengfu Tian, Shusheng Wei, Jiayu Xie and Tainming Bai
Micromachines 2022, 13(12), 2048; https://0-doi-org.brum.beds.ac.uk/10.3390/mi13122048 - 23 Nov 2022
Cited by 1 | Viewed by 1152
Abstract
This paper investigates the deadbeat current controllers for isolated bidirectional dual-active-bridge dc-dc converter (IBDC), including the peak current mode (PCM) and middle current mode (MCM). The controller uses an enhanced single phase shift (ESPS) modulation method by exploiting pulse width as an extra [...] Read more.
This paper investigates the deadbeat current controllers for isolated bidirectional dual-active-bridge dc-dc converter (IBDC), including the peak current mode (PCM) and middle current mode (MCM). The controller uses an enhanced single phase shift (ESPS) modulation method by exploiting pulse width as an extra control variable in addition to phase shift ratio. The control variables for PCM controllers are derived in detail and the two different current controllers are compared. A double-closed-loop control method is then employed, which could directly control the high-frequency inductor current and eliminate the transient DC current bias of the transformer. Furthermore, load feedforward was introduced to further enhance the dynamic of the converter. With the proposed control method, the settling time could be reduced within several PWM cycles during load disturbance without transient DC current bias. A 5 kW IBDC converter prototype was built and the settling time of 6 PWM cycles during load change with voltage regulation mode was achieved, which verifies the superior dynamic performance of the control method. Full article
(This article belongs to the Special Issue Advanced Interconnect and Packaging)
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13 pages, 2250 KiB  
Article
Broadband Frequency Selective Rasorber Based on Spoof Surface Plasmon Polaritons
by Jin Bai, Qingzhen Yang, Yichao Liang and Xiang Gao
Micromachines 2022, 13(11), 1969; https://0-doi-org.brum.beds.ac.uk/10.3390/mi13111969 - 13 Nov 2022
Cited by 3 | Viewed by 1235
Abstract
A broadband frequency selective rasorber (FSR) based on spoofsurface plasmon polaritons (SSPP) is proposed. The FSR is composed of a multi-layer structure comprising frequency selective surface (FSS)-polyresin (PR)-indium tin oxide (ITO)-PR-FSS and placed vertically on a metal base plate. A periodic square cavity [...] Read more.
A broadband frequency selective rasorber (FSR) based on spoofsurface plasmon polaritons (SSPP) is proposed. The FSR is composed of a multi-layer structure comprising frequency selective surface (FSS)-polyresin (PR)-indium tin oxide (ITO)-PR-FSS and placed vertically on a metal base plate. A periodic square cavity structure is formed. The transmission characteristics of the FSR are studied by full-wave simulation and equivalent circuit method. The simulation results demonstrate that under normal incidence, the absorption rate of the structure remains 95% in the 5–30 GHz band, and the absorption rate is also 80% in the 3.5–5 GHz band. As the incident angle of the electromagnetic wave increases to 40°, the absorption rate in the 15–20 GHz band decreases to 70% in the transverse electric (TE) mode, and the absorption rate in the transverse magnetic (TM) mode is almost the same as that of vertical incidence. The transmission response of the structure is measured in an anechoic chamber. The measurement results agree well with the simulation results, proving the reliability of the design and fabrication. The structure is less sensitive to the incident angle of magnetic waves and has a better broadband absorbing ability. Full article
(This article belongs to the Special Issue Advanced Interconnect and Packaging)
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12 pages, 4774 KiB  
Article
Electrical Modeling and Characterization of Graphene-Based On-Chip Spiral Inductors
by Da-Wei Wang, Meng-Jiao Yuan, Jia-Yun Dai and Wen-Sheng Zhao
Micromachines 2022, 13(11), 1829; https://0-doi-org.brum.beds.ac.uk/10.3390/mi13111829 - 26 Oct 2022
Cited by 3 | Viewed by 1663
Abstract
This paper investigates the electrical performance of graphene-based on-chip spiral inductors by virtue of a physics-based equivalent circuit model. The skin and proximity effects, as well as the substrate loss effect, are considered and treated appropriately. The graphene resistance and inductance are combined [...] Read more.
This paper investigates the electrical performance of graphene-based on-chip spiral inductors by virtue of a physics-based equivalent circuit model. The skin and proximity effects, as well as the substrate loss effect, are considered and treated appropriately. The graphene resistance and inductance are combined into the circuit model. It is demonstrated that the electrical characteristics of the on-chip square spiral inductor can be improved by replacing copper with graphene. Moreover, graphene exhibits more effectiveness in improving the inductance in tapered inductors than uniform ones. Full article
(This article belongs to the Special Issue Advanced Interconnect and Packaging)
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16 pages, 5395 KiB  
Article
Design and Application of a Flexible Blood Oxygen Sensing Array for Wearable Devices
by Wen-Cheng Kuo, Tzu-Chien Wu and Jun-Sheng Wang
Micromachines 2022, 13(10), 1742; https://0-doi-org.brum.beds.ac.uk/10.3390/mi13101742 - 14 Oct 2022
Cited by 2 | Viewed by 2556
Abstract
The performance of portable or wearable oximeters is affected by improper movement or wear, which causes an error in the blood oxygen concentration calculation. The error comes from external incident stray light or light leakage caused by the improper fit of the sensor [...] Read more.
The performance of portable or wearable oximeters is affected by improper movement or wear, which causes an error in the blood oxygen concentration calculation. The error comes from external incident stray light or light leakage caused by the improper fit of the sensor to the skin. This study aimed to develop a flexible blood oxygen sensing system with a 3 × 3 array that uses a reflective-type blood oxygen sensing chip to sequentially measure the blood oxygen levels at nine locations through a time division pulse modulation method. Each sensing chip has light transmission and receiving parts. A flip chip package was used to integrate the sensing chip, and a flexible parylene substrate that could fit the curvature of the wrist and locate the array of photo diodes around the radial artery of the wrist was used. By scanning the sensor array in dynamic behavior, the correct light intensity can be extracted to obtain the blood oxygen concentration and prevent errors due to improper fit or sensor movement during exercise. Full article
(This article belongs to the Special Issue Advanced Interconnect and Packaging)
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11 pages, 3726 KiB  
Article
Reliability Evaluation Based on Mathematical Degradation Model for Vacuum Packaged MEMS Sensor
by Guizhen Du, Xianshan Dong, Xinglong Huang, Wei Su and Peng Zhang
Micromachines 2022, 13(10), 1713; https://0-doi-org.brum.beds.ac.uk/10.3390/mi13101713 - 11 Oct 2022
Cited by 5 | Viewed by 1135
Abstract
Vacuum packaging is used extensively in MEMS sensors for improving performance. However, the vacuum in the MEMS chamber gradually degenerates over time, which adversely affects the long-term performance of the MEMS sensor. A mathematical model for vacuum degradation is presented in this article [...] Read more.
Vacuum packaging is used extensively in MEMS sensors for improving performance. However, the vacuum in the MEMS chamber gradually degenerates over time, which adversely affects the long-term performance of the MEMS sensor. A mathematical model for vacuum degradation is presented in this article for evaluating the degradation of vacuum packaged MEMS sensors, and a temperature-accelerated test of MEMS gyroscope with different vacuums is performed. A mathematical degradation model is developed to fit the parameters of the degradation of Q-factor over time at three different temperatures. The results indicate that the outgassing rate at 85 °C is the highest, which is 0.0531 cm2/s; the outgassing rate at 105 °C is the lowest, which is 0.0109 cm2/s; and the outgassing rate at 125 °C is in the middle, which is 0.0373 cm2/s. Due to the different mechanisms by which gas was released, the rate of degradation did not follow this rule. It will also be possible to predict the long-term reliability of vacuum packaged MEMS sensors at room temperature based on this model. Full article
(This article belongs to the Special Issue Advanced Interconnect and Packaging)
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9 pages, 2907 KiB  
Article
Study on the Wetting Mechanism between Hot-Melt Nano Glass Powder and Different Substrates
by Yifang Liu, Junyu Chen and Gaofeng Zheng
Micromachines 2022, 13(10), 1683; https://0-doi-org.brum.beds.ac.uk/10.3390/mi13101683 - 06 Oct 2022
Cited by 1 | Viewed by 1182
Abstract
The wettability of molten glass powder plays an essential role in the encapsulation of microelectromechanical system (MEMS) devices with glass paste as an intermediate layer. In this study, we first investigated the flow process of nano glass powder melted at a high temperature [...] Read more.
The wettability of molten glass powder plays an essential role in the encapsulation of microelectromechanical system (MEMS) devices with glass paste as an intermediate layer. In this study, we first investigated the flow process of nano glass powder melted at a high temperature by simulation in COMSOL. Both the influence of the different viscosity of hot-melt glass on its wettability on SiO2 and the comparison of the wettability of hot-melt glass on Au metal lead and SiO2 were investigated by simulation. Then, in the experiment, the hot-melt glass flew and spread along the length of the Au electrode because of a good wettability, resulting in little coverage of the hot-melt glass on the Au electrode, with a height of only 500 nm. In order to reduce the wettability of the glass paste on the Au electrode, a SiO2 isolation layer was grown on the surface of golden lead by chemical vapor deposition. It successfully reduced the wettability, so the thickness of the hot-melt glass was increased to 1.95 μm. This proved once again that the wettability of hot-melt glass on Au was better. Full article
(This article belongs to the Special Issue Advanced Interconnect and Packaging)
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11 pages, 2793 KiB  
Article
Au Wire Ball Welding and Its Reliability Test for High-Temperature Environment
by Chenyang Wu, Junqiang Wang, Xiaofei Liu, Mengwei Li, Zehua Zhu and Yue Qi
Micromachines 2022, 13(10), 1603; https://0-doi-org.brum.beds.ac.uk/10.3390/mi13101603 - 27 Sep 2022
Cited by 3 | Viewed by 1428
Abstract
The long-term application of sensors in a high-temperature environment needs to address several challenges, such as stability at high temperatures for a long time, better wiring interconnection of sensors, and reliable and steady connection of the sensor and its external equipment. In order [...] Read more.
The long-term application of sensors in a high-temperature environment needs to address several challenges, such as stability at high temperatures for a long time, better wiring interconnection of sensors, and reliable and steady connection of the sensor and its external equipment. In order to systematically investigate the reliability of thin coatings at high temperatures for a long time, Au and Cr layers were deposited on silicon substrates by magnetron sputtering. Additionally, samples with different electrode thicknesses were annealed at different temperatures for a varied duration to study the effect of electrode thickness, temperature, and duration on the reliability of samples. The results of tensile and probe tests before and after heat treatment revealed that the mechanical strength and electrical properties have changed after annealing. In addition, the bonding interface was analyzed by a cross-sectional electron microscope. The analysis showed that long-term continuous high-temperature exposure would result in thinning of the electrode, formation of pores, recrystallization, and grain growth, all of which can affect the mechanical strength and electrical properties. In addition, it was observed that increasing the thickness of the gold layer will improve reliability, and the test results show that although the thin metal layer sample is in poor condition, it is still usable. The present study provides theoretical support for the application of thin coatings in high temperatures and harsh environments. Full article
(This article belongs to the Special Issue Advanced Interconnect and Packaging)
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11 pages, 7419 KiB  
Article
High Quality Pt–Pt Metal Bonding for High Temperature Packaging
by Jiazheng Liu, Junqiang Wang, Mengwei Li and Haikun Zhang
Micromachines 2022, 13(9), 1543; https://0-doi-org.brum.beds.ac.uk/10.3390/mi13091543 - 17 Sep 2022
Cited by 3 | Viewed by 1414
Abstract
Platinum is an ideal material for high-temperature resistant device packaging due to its higher melting point and good electrical properties. In this paper, the thermocompression bonding of Pt–Pt metal electrodes was successfully realized through process exploration, and the package interconnection that meets the [...] Read more.
Platinum is an ideal material for high-temperature resistant device packaging due to its higher melting point and good electrical properties. In this paper, the thermocompression bonding of Pt–Pt metal electrodes was successfully realized through process exploration, and the package interconnection that meets the requirements was formed. A square bump with a side length of 160 µm and a sealing ring with a width of 80 µm were fabricated by magnetron sputtering. Different pressure parameters were selected for chip-level bonding; the bonding temperature was 350 °C for about 20 min. Analysis of the interface under a scanning electron microscope found that the metal Cr diffused into Pt. It was found that two chips sputtered with 300 nm metal Pt can achieve shear resistance up to 30 MPa by flip-chip bonding at 350 °C and 100 MPa temperature and pressure, respectively. The leakage rate of the sample is less than 2 × 10–3 Pa·cm3/s, the bonding interface is relatively smooth, and the hot-pressed metal bonding of Pt electrodes with good quality is realized. By comparing the failure rates at different temperatures and pressures, the process parameters for Pt–Pt bonding with higher success rates were obtained. We hope to provide new ideas and methods for the packaging of high-temperature resistant devices. Full article
(This article belongs to the Special Issue Advanced Interconnect and Packaging)
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19 pages, 5565 KiB  
Article
Design of Power/Ground Noise Suppression Structures Based on a Dispersion Analysis for Packages and Interposers with Low-Loss Substrates
by Youngwoo Kim
Micromachines 2022, 13(9), 1433; https://0-doi-org.brum.beds.ac.uk/10.3390/mi13091433 - 30 Aug 2022
Cited by 3 | Viewed by 1128
Abstract
In this study, power/ground noise suppression structures were designed based on a proposed dispersion analysis for packages and interposers with low-loss substrates. Low-loss substrates are suitable for maintaining signal integrity (SI) of high-speed channels operating at high data rates. However, when the power/ground [...] Read more.
In this study, power/ground noise suppression structures were designed based on a proposed dispersion analysis for packages and interposers with low-loss substrates. Low-loss substrates are suitable for maintaining signal integrity (SI) of high-speed channels operating at high data rates. However, when the power/ground noise is generated in the power delivery network (PDN), low-loss substrates cannot suppress the power/ground noise, thereby causing PDN-induced crosstalk and various power integrity (PI) issues. To solve these issues, noise suppression structures generating electromagnetic bandgap were proposed and designed. The mechanism of the proposed structures was examined based on a proposed dispersion analysis. The proposed structures were designed and fabricated in glass interposer test vehicles, and the effectiveness of the structures on power/ground noise suppression was experimentally validated by measuring the noise suppression band. The proposed dispersion analysis was also verified by comparing the derived noise stopband edges (fL and fU) with electromagnetic (EM) simulation and experimental results, and they all showed good agreement. Compared to EM simulation, the proposed method required smaller computational resources but showed good accuracy. Using the proposed dispersion analysis, various power/ground noise suppression bands were designed considering the applications and design rules of packages and interposers. With measurements and EM/circuit simulations, the effectiveness of the designed structure in maintaining SI/PI was verified. By adopting the designed structures, the noise transfer properties in the PDN were suppressed in the target suppression frequency band, which is key for PI design. Finally, it was verified that the proposed structures were capable of suppressing power/ground noise propagation in the PDN by analyzing PDN-induced crosstalk in the high-speed channel. Full article
(This article belongs to the Special Issue Advanced Interconnect and Packaging)
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11 pages, 5009 KiB  
Article
Wideband Substrate Integrated Waveguide Chip Filter Using Spoof Surface Plasmon Polariton
by Dongzhe Pan, Bin You, Xuan Wen and Xungen Li
Micromachines 2022, 13(8), 1195; https://0-doi-org.brum.beds.ac.uk/10.3390/mi13081195 - 28 Jul 2022
Cited by 11 | Viewed by 1742
Abstract
This article presents a novel wideband bandpass filter based on the integration of a substrate integrated waveguide (SIW) and a spoof surface plasmon polariton (SSPP). An SIW cavity with periodic arrays of meander-slot units is etched on the top metallic layer to achieve [...] Read more.
This article presents a novel wideband bandpass filter based on the integration of a substrate integrated waveguide (SIW) and a spoof surface plasmon polariton (SSPP). An SIW cavity with periodic arrays of meander-slot units is etched on the top metallic layer to achieve the characteristics of a multi-order filter with good performance. The passbands can be flexibly selected by varying the geometric parameters of the SIW and SSPP to adjust the lower and upper sidebands independently. Using a redistribution layer (RDL) process, a novel 3D capacitive interconnection called a through-dielectric capacitor (TDC) is proposed and collaboratively designed with an interdigital capacitor to achieve capacitive source-load cross-coupling. The proposed filter has a center frequency of 60 GHz, with a wide 3-dB fractional bandwidth of about 45.8%. The improved simulated sideband suppression has a 30 dB rejection at 40 GHz and 75.4 GHz, corresponding to a 30-dB rectangular coefficient of 1.28. Full article
(This article belongs to the Special Issue Advanced Interconnect and Packaging)
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12 pages, 3092 KiB  
Article
Hermetic Packaging Based on Cu–Sn and Au–Au Dual Bonding for High-Temperature Graphene Pressure Sensor
by Junqiang Wang, Haikun Zhang, Xuwen Chen and Mengwei Li
Micromachines 2022, 13(8), 1191; https://0-doi-org.brum.beds.ac.uk/10.3390/mi13081191 - 28 Jul 2022
Cited by 1 | Viewed by 1242
Abstract
A chip-level hermetic package for a high-temperature graphene pressure sensor was investigated. The silicon cap, chip and substrate were stacked by Cu–Sn and Au–Au bonding to enable wide-range measurements while guaranteeing a high hermetic package. Prior to bonding, the sample was treated with [...] Read more.
A chip-level hermetic package for a high-temperature graphene pressure sensor was investigated. The silicon cap, chip and substrate were stacked by Cu–Sn and Au–Au bonding to enable wide-range measurements while guaranteeing a high hermetic package. Prior to bonding, the sample was treated with Ar (5% H2) plasma. The Cu–Sn bonding was firstly performed at 260 °C for 15 min with a pressure of 9.9 MPa, and the corresponding process conditions for Au–Au bonding has increased to 300 °C, 20 min and 19.8 MPa respectively. The average shearing strength was 14.3 MPa, and an excellent leak rate of 1.72 × 10−4 Pa·cm3/s was also achieved. After high-temperature storage (HTS) at 350 °C for 10 h, the resistance of graphene decreased slightly because the dual bonding provided oxygen-free environment for graphene. The leakage rate of the device slightly increased to 2.1 × 10−4 Pa·cm3/s, and the average shear strength just decreased to 13.5 MPa. Finally, under the pressure range of 0–100 MPa, the graphene pressure sensor exhibited a high average sensitivity of 3.11 Ω/MPa. In conclusion, the dual bonding that combined Cu–Sn and Au–Au is extremely suitable for hermetic packaging in high-temperature graphene pressure sensors. Full article
(This article belongs to the Special Issue Advanced Interconnect and Packaging)
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17 pages, 7546 KiB  
Article
A Novel Interposer Channel Structure with Vertical Tabbed Vias to Reduce Far-End Crosstalk for Next-Generation High-Bandwidth Memory
by Hyunwoong Kim, Seonghi Lee, Kyunghwan Song, Yujun Shin, Dongyrul Park, Jongcheol Park, Jaeyong Cho and Seungyoung Ahn
Micromachines 2022, 13(7), 1070; https://0-doi-org.brum.beds.ac.uk/10.3390/mi13071070 - 05 Jul 2022
Cited by 5 | Viewed by 2129
Abstract
In this paper, we propose and analyze a novel interposer channel structure with vertical tabbed vias to achieve high-speed signaling and low-power consumption in high-bandwidth memory (HBM). An analytical model of the self- and mutual capacitance of the proposed interposer channel is suggested [...] Read more.
In this paper, we propose and analyze a novel interposer channel structure with vertical tabbed vias to achieve high-speed signaling and low-power consumption in high-bandwidth memory (HBM). An analytical model of the self- and mutual capacitance of the proposed interposer channel is suggested and verified based on a 3D electromagnetic (EM) simulation. We thoroughly analyzed the electrical characteristics of the novel interposer channel considering various design parameters, such as the height and pitch of the vertical tabbed via and the gap of the vertical channel. Based on the frequency-dependent lumped circuit resistance, inductance, and capacitance, we analyzed the channel characteristics of the proposed interposer channel. In terms of impedance, insertion loss, and far-end crosstalk, we analyzed how much the proposed interposer channel improved the signal integrity characteristics compared to a conventional structure consisting of micro-strip and strip lines together. Compared to the conventional worst case, which is the strip line, the eye-width, the eye-height, and eye-jitter of the proposed interposer channel were improved by 17.6%, 29%, and 9.56%, respectively, at 8 Gbps. The proposed interposer channel can reduce dynamic power consumption by about 28% compared with the conventional interposer channel by minimizing the self-capacitance of the off-chip channel. Full article
(This article belongs to the Special Issue Advanced Interconnect and Packaging)
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13 pages, 5145 KiB  
Article
Average Power Handling Capability of Corrugated Slow-Wave Transmission Lines
by Zehao Zheng, Min Tang, Haochi Zhang and Junfa Mao
Micromachines 2022, 13(6), 961; https://0-doi-org.brum.beds.ac.uk/10.3390/mi13060961 - 17 Jun 2022
Cited by 1 | Viewed by 1577
Abstract
In this article, the average power handling capability (APHC) of corrugated slow-wave transmission lines (SWTLs) is investigated. Firstly, the attenuation constants of conductor and dielectric are extracted by the multiline method. Secondly, the thermal resistance of corrugated SWTLs is analyzed based on the [...] Read more.
In this article, the average power handling capability (APHC) of corrugated slow-wave transmission lines (SWTLs) is investigated. Firstly, the attenuation constants of conductor and dielectric are extracted by the multiline method. Secondly, the thermal resistance of corrugated SWTLs is analyzed based on the constant-angle model. To deal with the non-uniform corrugated structure of SWTLs, the concept of average heat-spreading width (AHSW) is introduced. Finally, the APHC of the corrugated SWTL is calculated using the attenuation constant and the thermal resistance. In addition, the APHC considering the temperature-dependent resistivity of metal conductor is also presented. For validation, the APHCs of SWTLs with different geometric parameters are evaluated. The results agree well with those obtained by the commercial software. Full article
(This article belongs to the Special Issue Advanced Interconnect and Packaging)
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13 pages, 13345 KiB  
Article
A New Low-Temperature Solder Assembly Technique to Replace Eutectic Sn-Bi Solder Assembly
by Lingyao Sun, Zhenhua Guo, Xiuchen Zhao, Ying Liu, Kingning Tu and Yingxia Liu
Micromachines 2022, 13(6), 867; https://0-doi-org.brum.beds.ac.uk/10.3390/mi13060867 - 31 May 2022
Cited by 3 | Viewed by 2312
Abstract
We successfully achieved low-temperature assembly by reflowing the 13.5Sn-37.5Bi-45In-4Pb quaternary eutectic solder paste and the SAC 305 solder ball together at 140 °C for 5 min. The wetting angle of the mixed solder joint is 17.55°. The overall atomic percent of Pb in [...] Read more.
We successfully achieved low-temperature assembly by reflowing the 13.5Sn-37.5Bi-45In-4Pb quaternary eutectic solder paste and the SAC 305 solder ball together at 140 °C for 5 min. The wetting angle of the mixed solder joint is 17.55°. The overall atomic percent of Pb in the mixed solder joint is less than 1%, which can be further reduced or eliminated. Moreover, after aging at 80 °C for 25 days, we observed no obvious decrease in shear strength of the fully mixed solder joint, which is the most advantage of this assembly technique over Sn58Bi solder assembly. The Bi phase segregation at the interface is slowed down compared with Sn-Bi solder joint. This low-temperature assembly is promising to be applied in advanced packaging technology to replace the eutectic Sn-Bi solder. Full article
(This article belongs to the Special Issue Advanced Interconnect and Packaging)
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10 pages, 3268 KiB  
Article
Antenna Current Calculation Based on Equivalent Transmission Line Model
by Shusheng Wei and Wusong Wen
Micromachines 2022, 13(5), 714; https://0-doi-org.brum.beds.ac.uk/10.3390/mi13050714 - 30 Apr 2022
Cited by 2 | Viewed by 1720
Abstract
This paper provides a new way for spatial current/field profiles for frequency-selective surface analytical approximation. It confirms that the per unit length radiation resistance of an equivalent transmission line model for line antenna has little influence on the normalized current distribution. The two-wire [...] Read more.
This paper provides a new way for spatial current/field profiles for frequency-selective surface analytical approximation. It confirms that the per unit length radiation resistance of an equivalent transmission line model for line antenna has little influence on the normalized current distribution. The two-wire equivalent transmission line model (typically used for transmitting line antenna) is applied to the receiving line antenna. In this case, the corresponding incident field is decomposed into odd and even mode for asymmetric distribution. A one-wire equivalent transmission line model is then introduced for any antenna composed of relative narrow strips. The incident field does not need to be decomposed. According to the simulation, the transmission line loss has little influence on the current distribution. Full article
(This article belongs to the Special Issue Advanced Interconnect and Packaging)
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Review

Jump to: Editorial, Research

19 pages, 2362 KiB  
Review
Recent Progress and Challenges Regarding Carbon Nanotube On-Chip Interconnects
by Baohui Xu, Rongmei Chen, Jiuren Zhou and Jie Liang
Micromachines 2022, 13(7), 1148; https://0-doi-org.brum.beds.ac.uk/10.3390/mi13071148 - 20 Jul 2022
Cited by 14 | Viewed by 2700
Abstract
Along with deep scaling transistors and complex electronics information exchange networks, very-large-scale-integrated (VLSI) circuits require high performance and ultra-low power consumption. In order to meet the demand of data-abundant workloads and their energy efficiency, improving only the transistor performance would not be sufficient. [...] Read more.
Along with deep scaling transistors and complex electronics information exchange networks, very-large-scale-integrated (VLSI) circuits require high performance and ultra-low power consumption. In order to meet the demand of data-abundant workloads and their energy efficiency, improving only the transistor performance would not be sufficient. Super high-speed microprocessors are useless if the capacity of the data lines is not increased accordingly. Meanwhile, traditional on-chip copper interconnects reach their physical limitation of resistivity and reliability and may no longer be able to keep pace with a processor’s data throughput. As one of the potential alternatives, carbon nanotubes (CNTs) have attracted important attention to become the future emerging on-chip interconnects with possible explorations of new development directions. In this paper, we focus on the electrical, thermal, and process compatibility issues of current on-chip interconnects. We review the advantages, recent developments, and dilemmas of CNT-based interconnects from the perspective of different interconnect lengths and through-silicon-via (TSV) applications. Full article
(This article belongs to the Special Issue Advanced Interconnect and Packaging)
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31 pages, 5679 KiB  
Review
Recent Progress in Physics-Based Modeling of Electromigration in Integrated Circuit Interconnects
by Wen-Sheng Zhao, Rui Zhang and Da-Wei Wang
Micromachines 2022, 13(6), 883; https://0-doi-org.brum.beds.ac.uk/10.3390/mi13060883 - 31 May 2022
Cited by 6 | Viewed by 3493
Abstract
The advance of semiconductor technology not only enables integrated circuits with higher density and better performance but also increases their vulnerability to various aging mechanisms which occur from front-end to back-end. Analysis on the impact of aging mechanisms on circuits’ reliability is crucial [...] Read more.
The advance of semiconductor technology not only enables integrated circuits with higher density and better performance but also increases their vulnerability to various aging mechanisms which occur from front-end to back-end. Analysis on the impact of aging mechanisms on circuits’ reliability is crucial for the design of reliable and sustainable electronic systems at advanced technology nodes. As one of the most crucial back-end aging mechanisms, electromigration deserves research efforts. This paper introduces recent studies on physics-based modeling of electromigration aging of on-chip interconnects. At first, the background of electromigration is introduced. The conventional method and physics-based modeling for electromigration are described. Then studies on how electromigration affects powers grids and signal interconnects are discussed in detail. Some of them focus on the comprehensiveness of modeling methodology, while others aim at the strategies for improving computation accuracy and speed and the strategies for accelerating/decelerating aging. Considering the importance of electromigration for circuit reliability, this paper is dedicated to providing a review on physics-based modeling methodologies on electromigration and their applications for integrated circuits interconnects. Full article
(This article belongs to the Special Issue Advanced Interconnect and Packaging)
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