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Nanomaterials for Electron Devices
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Nanomaterials for Electron Devices

A special issue of Nanomaterials (ISSN 2079-4991). This special issue belongs to the section "Nanoelectronics, Nanosensors and Devices".

Deadline for manuscript submissions: closed (10 December 2023) | Viewed by 43867

Special Issue Editors

Prof. Yung-Hsien Wu

E-Mail Website
Guest Editor
National Tsing Hua University, 101, Section 2, Kuang-Fu Road, Hsinchu 300, Taiwan
Interests: ferroelectric device; non-volatile memory; high-mobility channel material; neuromorphic computing; advanced metal gate/contact process
Prof. Dr. Albert Chin

E-Mail Website
Guest Editor
Inst. of Electronics Eng., National Yang Ming Chiao Tung University, Hsinchu, Taiwan
Interests: transistor; metal-oxide transistor; resistive random-access memory; ferroelectric random-access memory; DRAM

Special Issue Information

Dear Colleagues,

Electron devices are widely used in our daily lives in mobile phones, personal computers, cars, etc. Electron devices are also the enabling technology for the Fourth Industrial Revolution, artificial intelligence (AI), cloud computing, and autonomous drives.

Nanomaterials are the essential technologies for electron devices and integrated circuits (ICs), which have been implemented in metal-oxide-semiconductor field-effect transistors (MOSFETs), dynamic random-access memory (DRAM), and three-dimensional (3D) NAND flash memory. Nanomaterials will be even more important as electron devices downscale to sub-10 nm nodes and are used for gate-all-around (GAA) nanosheet transistors, ferroelectric DRAM, resistive RAM (RRAM), and emerging nonvolatile memories. Even after reaching the downscaled quantum-mechanical and technology limits, nanomaterials will still be crucial for monolithic 3D IC and brain-mimicking IC hardware.

In this Special Issue titled “Nanomaterials for Electron Devices” in the journal Nanomaterials, we invite potential authors to submit manuscripts on nanomaterials used for MOSFET, DRAM, 3D NAND flash memory, and thin-film transistors, as well as frontier topics of GAA nanosheet transistors, emerging nonvolatile memories, and future monolithic 3D IC and brain-mimicking IC hardware architectures. 

Accepted papers are published in the joint Special Issue in Nanomaterials or Nanomanufacturing (https://0-www-mdpi-com.brum.beds.ac.uk/journal/nanomanufacturing/special_issues/nanoelectron_devices).

Prof. Yung-Hsien Wu
Prof. Dr. Albert Chin
Guest Editors

Manuscript Submission Information

Manuscripts should be submitted online at www.mdpi.com by registering and logging in to this website. Once you are registered, click here to go to the submission form. Manuscripts can be submitted until the deadline. All submissions that pass pre-check are peer-reviewed. Accepted papers will be published continuously in the journal (as soon as accepted) and will be listed together on the special issue website. Research articles, review articles as well as short communications are invited. For planned papers, a title and short abstract (about 100 words) can be sent to the Editorial Office for announcement on this website.

Submitted manuscripts should not have been published previously, nor be under consideration for publication elsewhere (except conference proceedings papers). All manuscripts are thoroughly refereed through a single-blind peer-review process. A guide for authors and other relevant information for submission of manuscripts is available on the Instructions for Authors page. Nanomaterials is an international peer-reviewed open access semimonthly journal published by MDPI.

Please visit the Instructions for Authors page before submitting a manuscript. The Article Processing Charge (APC) for publication in this open access journal is 2900 CHF (Swiss Francs). Submitted papers should be well formatted and use good English. Authors may use MDPI's English editing service prior to publication or during author revisions.

Keywords

  • nanomaterials
  • MOSFET
  • DRAM
  • flash
  • thin-film transistor
  • GAA
  • nanosheet
  • monolithic 3D
  • emerging nonvolatile memory

Published Papers (19 papers)

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Research

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13 pages, 4067 KiB  
Article
Superior High Transistor’s Effective Mobility of 325 cm2/V-s by 5 nm Quasi-Two-Dimensional SnON nFET
by Pheiroijam Pooja, Chun Che Chien and Albert Chin
Nanomaterials 2023, 13(12), 1892; https://0-doi-org.brum.beds.ac.uk/10.3390/nano13121892 - 20 Jun 2023
Cited by 1 | Viewed by 984
Abstract
This work reports the first nanocrystalline SnON (7.6% nitrogen content) nanosheet n-type Field-Effect Transistor (nFET) with the transistor’s effective mobility (µeff) as high as 357 and 325 cm2/V-s at electron density (Qe) of 5 × 1012 [...] Read more.
This work reports the first nanocrystalline SnON (7.6% nitrogen content) nanosheet n-type Field-Effect Transistor (nFET) with the transistor’s effective mobility (µeff) as high as 357 and 325 cm2/V-s at electron density (Qe) of 5 × 1012 cm−2 and an ultra-thin body thickness (Tbody) of 7 nm and 5 nm, respectively. At the same Tbody and Qe, these µeff values are significantly higher than those of single-crystalline Si, InGaAs, thin-body Si-on-Insulator (SOI), two-dimensional (2D) MoS2 and WS2. The new discovery of a slower µeff decay rate at high Qe than that of the SiO2/bulk-Si universal curve was found, owing to a one order of magnitude lower effective field (Eeff) by more than 10 times higher dielectric constant (κ) in the channel material, which keeps the electron wave-function away from the gate-oxide/semiconductor interface and lowers the gate-oxide surface scattering. In addition, the high µeff is also due to the overlapped large radius s-orbitals, low 0.29 mo effective mass (me*) and low polar optical phonon scattering. SnON nFETs with record-breaking µeff and quasi-2D thickness enable a potential monolithic three-dimensional (3D) integrated circuit (IC) and embedded memory for 3D biological brain-mimicking structures. Full article
(This article belongs to the Special Issue Nanomaterials for Electron Devices)
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12 pages, 4639 KiB  
Article
Design Technology Co-Optimization Strategy for Ge Fraction in SiGe Channel of SGOI FinFET
by Shixin Li and Zhenhua Wu
Nanomaterials 2023, 13(11), 1709; https://0-doi-org.brum.beds.ac.uk/10.3390/nano13111709 - 23 May 2023
Viewed by 921
Abstract
FinFET devices and Silicon-On-Insulator (SOI) devices are two mainstream technical routes after the planar MOSFET reached the limit for scaling. The SOI FinFET devices combine the benefits of FinFET and SOI devices, which can be further boosted by SiGe channels. In this work, [...] Read more.
FinFET devices and Silicon-On-Insulator (SOI) devices are two mainstream technical routes after the planar MOSFET reached the limit for scaling. The SOI FinFET devices combine the benefits of FinFET and SOI devices, which can be further boosted by SiGe channels. In this work, we develop an optimizing strategy of the Ge fraction in SiGe Channels of SGOI FinFET devices. The simulation results of ring oscillator (RO) circuits and SRAM cells reveal that altering the Ge fraction can improve the performance and power of different circuits for different applications. Full article
(This article belongs to the Special Issue Nanomaterials for Electron Devices)
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17 pages, 4357 KiB  
Article
Design and Synthesis of Functional Silane-Based Silicone Resin and Application in Low-Temperature Curing Silver Conductive Inks
by Zhiqiang Tang, Yanxia Liu, Yagang Zhang, Zicai Sun, Weidong Huang, Zhikai Chen, Xiaoli Jiang and Lin Zhao
Nanomaterials 2023, 13(6), 1137; https://0-doi-org.brum.beds.ac.uk/10.3390/nano13061137 - 22 Mar 2023
Cited by 2 | Viewed by 1693
Abstract
In the field of flexible electronics manufacturing, inkjet printing technology is a research hotspot, and it is key to developing low-temperature curing conductive inks that meet printing requirements and have suitable functions. Herein, methylphenylamino silicon oil (N75) and epoxy-modified silicon oil (SE35) were [...] Read more.
In the field of flexible electronics manufacturing, inkjet printing technology is a research hotspot, and it is key to developing low-temperature curing conductive inks that meet printing requirements and have suitable functions. Herein, methylphenylamino silicon oil (N75) and epoxy-modified silicon oil (SE35) were successfully synthesized through functional silicon monomers, and they were used to prepare silicone resin 1030H with nano SiO2. 1030H silicone resin was used as the resin binder for silver conductive ink. The silver conductive ink we prepared with 1030H has good dispersion performance with a particle size of 50–100 nm, as well as good storage stability and excellent adhesion. Additionally, the printing performance and conductivity of the silver conductive ink prepared with n,n-dimethylformamide (DMF): proprylene glycol monomethyl ether (PM) (1:1) as solvent are better than those of the silver conductive ink prepared by DMF and PM solvent. Cured at a low temperature of 160 °C, the resistivity of 1030H-Ag-82%-3 conductive ink is 6.87 × 10−6 Ω·m, and that of 1030H-Ag-92%-3 conductive ink is 0.564 × 10−6 Ω·m, so the low-temperature curing silver conductive ink has high conductivity. The low-temperature curing silver conductive ink we prepared meets the printing requirements and has potential for practical applications. Full article
(This article belongs to the Special Issue Nanomaterials for Electron Devices)
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10 pages, 3356 KiB  
Article
Threshold Voltage Adjustment by Varying Ge Content in SiGe p-Channel for Single Metal Shared Gate Complementary FET (CFET)
by Chong-Jhe Sun, Chen-Han Wu, Yi-Ju Yao, Shan-Wen Lin, Siao-Cheng Yan, Yi-Wen Lin and Yung-Chun Wu
Nanomaterials 2022, 12(20), 3712; https://0-doi-org.brum.beds.ac.uk/10.3390/nano12203712 - 21 Oct 2022
Viewed by 3685
Abstract
We have demonstrated the method of threshold voltage (VT) adjustment by controlling Ge content in the SiGe p-channel of N1 complementary field-effect transistor (CFET) for conquering the work function metal (WFM) filling issue on highly scaled MOSFET. Single WFM shared gate [...] Read more.
We have demonstrated the method of threshold voltage (VT) adjustment by controlling Ge content in the SiGe p-channel of N1 complementary field-effect transistor (CFET) for conquering the work function metal (WFM) filling issue on highly scaled MOSFET. Single WFM shared gate N1 CFET was used to study and emphasize the VT tunability of the proposed Ge content method. The result reveals that the Ge mole fraction influences VTP of 5 mV/Ge%, and a close result can also be obtained from the energy band configuration of Si1-xGex. Additionally, the single WFM shared gate N1 CFET inverter with VT adjusted by the Ge content method presents a well-designed voltage transfer curve, and its inverter transient response is also presented. Furthermore, the designed CFET inverter is used to construct a well-behaved 6T-SRAM with a large SNM of ~120 mV at VDD of 0.5 V. Full article
(This article belongs to the Special Issue Nanomaterials for Electron Devices)
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11 pages, 2129 KiB  
Article
Sensitivity of Inner Spacer Thickness Variations for Sub-3-nm Node Silicon Nanosheet Field-Effect Transistors
by Sanguk Lee, Jinsu Jeong, Jun-Sik Yoon, Seunghwan Lee, Junjong Lee, Jaewan Lim and Rock-Hyun Baek
Nanomaterials 2022, 12(19), 3349; https://0-doi-org.brum.beds.ac.uk/10.3390/nano12193349 - 26 Sep 2022
Cited by 6 | Viewed by 1858
Abstract
The inner spacer thickness (TIS) variations in sub-3-nm, node 3-stacked, nanosheet field-effect transistors (NSFETs) were investigated using computer-aided design simulation technology. Inner spacer formation requires a high selectivity of SiGe to Si, which causes inevitable TIS variation (ΔTIS). [...] Read more.
The inner spacer thickness (TIS) variations in sub-3-nm, node 3-stacked, nanosheet field-effect transistors (NSFETs) were investigated using computer-aided design simulation technology. Inner spacer formation requires a high selectivity of SiGe to Si, which causes inevitable TIS variation (ΔTIS). The gate length (LG) depends on the TIS. Thus, the DC/AC performance is significantly affected by ΔTIS. Because the effects of ΔTIS on the performance depend on which inner spacer is varied, the sensitivities of the performance to the top, middle, and bottom (T, M, and B, respectively) ΔTIS should be studied separately. In addition, the source/drain (S/D) recess process variation that forms the parasitic bottom transistor (trpbt) should be considered with ΔTIS because the gate controllability over trpbt is significantly dependent on ΔTIS,B. If the S/D recess depth (TSD) variation cannot be completely eliminated, reducing ΔTIS,B is crucial for suppressing the effects of trpbt. It is noteworthy that reducing ΔTIS,B is the most important factor when the TSD variation occurs, whereas reducing ΔTIS,T and ΔTIS,M is crucial in the absence of TSD variation to minimize the DC performance variation. As the TIS increases, the gate capacitance (Cgg) decreases owing to the reduction in both parasitic and intrinsic capacitance, but the sensitivity of Cgg to each ΔTIS is almost the same. Therefore, the difference in performance sensitivity related to AC response is also strongly affected by the DC characteristics. In particular, since TSD of 5 nm increases the off-state current (Ioff) sensitivity to ΔTIS,B by a factor of 22.5 in NFETs, the ΔTIS,B below 1 nm is essential for further scaling and yield enhancement. Full article
(This article belongs to the Special Issue Nanomaterials for Electron Devices)
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15 pages, 7711 KiB  
Article
Effect of Silicate Additive on Structural and Electrical Properties of Germanium Nanowires Formed by Electrochemical Reduction from Aqueous Solutions
by Anna S. Eremina, Ilya M. Gavrilin, Nikolay S. Pokryshkin, Alexander Yu. Kharin, Alexander V. Syuy, Valentin S. Volkov, Valery G. Yakunin, Sergei S. Bubenov, Sergey G. Dorofeev, Sergey A. Gavrilov and Victor Yu. Timoshenko
Nanomaterials 2022, 12(16), 2884; https://0-doi-org.brum.beds.ac.uk/10.3390/nano12162884 - 22 Aug 2022
Viewed by 1751
Abstract
Layers of germanium (Ge) nanowires (NWs) on titanium foils were grown by metal-assisted electrochemical reduction of germanium oxide in aqueous electrolytes based on germanium oxide without and with addition of sodium silicate. Structural properties and composition of Ge NWs were studied by means [...] Read more.
Layers of germanium (Ge) nanowires (NWs) on titanium foils were grown by metal-assisted electrochemical reduction of germanium oxide in aqueous electrolytes based on germanium oxide without and with addition of sodium silicate. Structural properties and composition of Ge NWs were studied by means of the scanning and transmission electron microscopy, X-ray photoelectron spectroscopy, X-ray diffraction, and Raman spectroscopy. When sodium silicate was added to the electrolyte, Ge NWs consisted of 1–2 at.% of silicon (Si) and exhibited smaller mean diameter and improved crystallinity. Additionally, samples of Ge NW films were prepared by ultrasonic removal of Ge NWs from titanium foils followed with redeposition on corundum substrates with platinum electrodes. The electrical conductivity of Ge NW films was studied at different temperatures from 25 to 300 °C and an effect of the silicon impurity on the thermally activated electrical conductivity was revealed. Furthermore, the electrical conductivity of Ge NW films on corundum substrates exhibited a strong sensor response on the presence of saturated vapors of different liquids (water, acetone, ethanol, and isopropanol) in air and the response was dependent on the presence of Si impurities in the nanowires. The results obtained indicate the possibility of controlling the structure and electrical properties of Ge NWs by introducing silicate additives during their formation, which is of interest for applications in printed electronics and molecular sensorics. Full article
(This article belongs to the Special Issue Nanomaterials for Electron Devices)
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11 pages, 1789 KiB  
Article
Inspection of the Defect State Using the Mobility Spectrum Analysis Method
by Il-Ho Ahn, Deuk Young Kim and Woochul Yang
Nanomaterials 2022, 12(16), 2773; https://0-doi-org.brum.beds.ac.uk/10.3390/nano12162773 - 12 Aug 2022
Cited by 1 | Viewed by 1369
Abstract
Mobility spectrum analysis (MSA) is a method that enables the carrier density (and mobility) separation of the majority and minority carriers in multicarrier semiconductors, respectively. In this paper, we use the p-GaAs layer in order to demonstrate that the MSA can perform [...] Read more.
Mobility spectrum analysis (MSA) is a method that enables the carrier density (and mobility) separation of the majority and minority carriers in multicarrier semiconductors, respectively. In this paper, we use the p-GaAs layer in order to demonstrate that the MSA can perform unique facilities for the defect analysis by using its resolvable features for the carriers. Using two proven methods, we reveal that the defect state can be anticipated at the characteristic temperature Tdeep, in which the ratio (RNn/Nh) that is associated with the density of the minority carrier Nn, to the density of the majority carrier Nh, exceeds 50%. (1) Using a p-GaAs Schottky diode in a reverse bias regime, the position of the deep level transient spectroscopy (DLTS) peak is shown directly as the defect signal. (2) Furthermore, by examining the current–voltage–temperature (I–V–T) characteristics in the forward bias regime, this peak position has been indirectly revealed as the generation–recombination center. The DLTS signals are dominant around the Tdeep, according to the window rate, and it has been shown that the peak variation range is consistent with the temperature range of the temperature-dependent generation–recombination peak. The Tdeep is also consistent with the temperature-dependent thermionic emission peak position. By having only RNn/Nh through the MSA, it is possible to intuitively determine the existence and the peak position of the DLTS signal, and the majority carrier’s density enables a more accurate extraction of the deep trap density in the DLTS analysis. Full article
(This article belongs to the Special Issue Nanomaterials for Electron Devices)
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12 pages, 2460 KiB  
Article
All-Printed Flexible Memristor with Metal–Non-Metal-Doped TiO2 Nanoparticle Thin Films
by Maryam Khan, Hafiz Mohammad Mutee Ur Rehman, Rida Tehreem, Muhammad Saqib, Muhammad Muqeet Rehman and Woo-Young Kim
Nanomaterials 2022, 12(13), 2289; https://0-doi-org.brum.beds.ac.uk/10.3390/nano12132289 - 03 Jul 2022
Cited by 12 | Viewed by 2690
Abstract
A memristor is a fundamental electronic device that operates like a biological synapse and is considered as the solution of classical von Neumann computers. Here, a fully printed and flexible memristor is fabricated by depositing a thin film of metal–non-metal (chromium-nitrogen)-doped titanium dioxide [...] Read more.
A memristor is a fundamental electronic device that operates like a biological synapse and is considered as the solution of classical von Neumann computers. Here, a fully printed and flexible memristor is fabricated by depositing a thin film of metal–non-metal (chromium-nitrogen)-doped titanium dioxide (TiO2). The resulting device exhibited enhanced performance with self-rectifying and forming free bipolar switching behavior. Doping was performed to bring stability in the performance of the memristor by controlling the defects and impurity levels. The forming free memristor exhibited characteristic behavior of bipolar resistive switching with a high on/off ratio (2.5 × 103), high endurance (500 cycles), long retention time (5 × 103 s) and low operating voltage (±1 V). Doping the thin film of TiO2 with metal–non-metal had a significant effect on the switching properties and conduction mechanism as it directly affected the energy bandgap by lowering it from 3.2 eV to 2.76 eV. Doping enhanced the mobility of charge carriers and eased the process of filament formation by suppressing its randomness between electrodes under the applied electric field. Furthermore, metal–non-metal-doped TiO2 thin film exhibited less switching current and improved non-linearity by controlling the surface defects. Full article
(This article belongs to the Special Issue Nanomaterials for Electron Devices)
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10 pages, 2980 KiB  
Article
Optimal Energetic-Trap Distribution of Nano-Scaled Charge Trap Nitride for Wider Vth Window in 3D NAND Flash Using a Machine-Learning Method
by Kihoon Nam, Chanyang Park, Jun-Sik Yoon, Hyeok Yun, Hyundong Jang, Kyeongrae Cho, Ho-Jung Kang, Min-Sang Park, Jaesung Sim, Hyun-Chul Choi and Rock-Hyun Baek
Nanomaterials 2022, 12(11), 1808; https://0-doi-org.brum.beds.ac.uk/10.3390/nano12111808 - 25 May 2022
Cited by 1 | Viewed by 2367
Abstract
A machine-learning (ML) technique was used to optimize the energetic-trap distributions of nano-scaled charge trap nitride (CTN) in 3D NAND Flash to widen the threshold voltage (Vth) window, which is crucial for NAND operation. The energetic-trap distribution is a critical [...] Read more.
A machine-learning (ML) technique was used to optimize the energetic-trap distributions of nano-scaled charge trap nitride (CTN) in 3D NAND Flash to widen the threshold voltage (Vth) window, which is crucial for NAND operation. The energetic-trap distribution is a critical material property of the CTN that affects the Vth window between the erase and program Vth. An artificial neural network (ANN) was used to model the relationship between the energetic-trap distributions as an input parameter and the Vth window as an output parameter. A well-trained ANN was used with the gradient-descent method to determine the specific inputs that maximize the outputs. The trap densities (NTD and NTA) and their standard deviations (σTD and σTA) were found to most strongly impact the Vth window. As they increased, the Vth window increased because of the availability of a larger number of trap sites. Finally, when the ML-optimized energetic-trap distributions were simulated, the Vth window increased by 49% compared with the experimental value under the same bias condition. Therefore, the developed ML technique can be applied to optimize cell transistor processes by determining the material properties of the CTN in 3D NAND Flash. Full article
(This article belongs to the Special Issue Nanomaterials for Electron Devices)
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12 pages, 2502 KiB  
Article
Effects of the Operating Ambiance and Active Layer Treatments on the Performance of Magnesium Fluoride Based Bipolar RRAM
by Nayan C. Das, Minjae Kim, Dong-uk Kwak, Jarnardhanan R. Rani, Sung-Min Hong and Jae-Hyung Jang
Nanomaterials 2022, 12(4), 605; https://0-doi-org.brum.beds.ac.uk/10.3390/nano12040605 - 11 Feb 2022
Cited by 3 | Viewed by 1873
Abstract
This study investigates switching characteristics of the magnesium fluoride (MgFx)-based bipolar resistive random-access memory (RRAM) devices at different operating ambiances (open-air and vacuum). Operating ambiances alter the elemental composition of the amorphous MgFx active layer and Ti/MgFx interface region, [...] Read more.
This study investigates switching characteristics of the magnesium fluoride (MgFx)-based bipolar resistive random-access memory (RRAM) devices at different operating ambiances (open-air and vacuum). Operating ambiances alter the elemental composition of the amorphous MgFx active layer and Ti/MgFx interface region, which affects the overall device performance. The experimental results indicate that filament type resistive switching takes place at the interface of Ti/MgFx and trap-controlled space charge limited conduction (SCLC) mechanisms is dominant in both the low and high resistance states in the bulk MgFx layer. RRAM device performances at different operating ambiances are also altered by MgFx active layer treatments (air exposure and annealing). Devices show the better uniformity, stability, and a higher on/off current ratio in vacuum compared to an open-air environment. The Ti/MgFx/Pt memory devices have great potential for future vacuum electronic applications. Full article
(This article belongs to the Special Issue Nanomaterials for Electron Devices)
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11 pages, 5385 KiB  
Article
Optimization of Gate-All-Around Device to Achieve High Performance and Low Power with Low Substrate Leakage
by Changhyun Yoo, Jeesoo Chang, Sugil Park, Hyungyeong Kim and Jongwook Jeon
Nanomaterials 2022, 12(4), 591; https://0-doi-org.brum.beds.ac.uk/10.3390/nano12040591 - 09 Feb 2022
Cited by 3 | Viewed by 2420
Abstract
In this study on multi-nanosheet field-effect transistor (mNS-FET)—one of the gate-all-around FETs (GAAFET) in the 3 nm technology node dimension—3D TCAD (technology computer-aided design) was used to attain optimally reduced substrate leakage from options including a punch-through-stopper (PTS) doping scheme and a bottom [...] Read more.
In this study on multi-nanosheet field-effect transistor (mNS-FET)—one of the gate-all-around FETs (GAAFET) in the 3 nm technology node dimension—3D TCAD (technology computer-aided design) was used to attain optimally reduced substrate leakage from options including a punch-through-stopper (PTS) doping scheme and a bottom oxide (BO) scheme for bottom isolation, with the performance improvement being shown in the circuit-level dynamic operation using the mNS-FET. The PTS doping concentration requires a high value of >5 × 1018 cm−3 to reduce gate induced drain leakage (GIDL), regardless of the presence or absence of the bottom isolation layer. When the bottom isolation is applied together with the PTS doping scheme, the capacitance reduction is larger than the on-state current reduction, as compared to when only the PTS doping concentration is applied. The effects of such transistor characteristics on the performance and capabilities of various circuit types—such as an inverter ring oscillator (RO), a full adder (FA) circuit, and a static random-access memory (SRAM)—were assessed. For the RO, applying BO along with the PTS doping allows the operating speed to be increased by 11.3% at the same power, or alternatively enables 26.4% less power consumption at the same speed. For the FA, power can be reduced by 6.45%, energy delay product (EDP) by 21.4%, and delay by 16.8% at the same standby power when BO and PTS are both applied. Finally, for the SRAM, read current (IREAD) increased by 18.7% and bit-line write margin (BWRM) increased by 12.5% at the same standby power. Through the circuit simulations, the Case 5 model (PTS doping concentration: 5.1 × 1018 cm−3, with BO) is the optimum condition for the best device and circuit performance. These observations confirm that PTS and bottom isolation applications in mNS-FETs can be utilized to enable the superior characteristics of such transistors to translate into high performance integrated circuits. Full article
(This article belongs to the Special Issue Nanomaterials for Electron Devices)
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8 pages, 3452 KiB  
Article
Enhancement of Ferroelectricity in 5 nm Metal-Ferroelectric-Insulator Technologies by Using a Strained TiN Electrode
by Cheng-Hung Wu, Kuan-Chi Wang, Yu-Yun Wang, Chenming Hu, Chun-Jung Su and Tian-Li Wu
Nanomaterials 2022, 12(3), 468; https://0-doi-org.brum.beds.ac.uk/10.3390/nano12030468 - 29 Jan 2022
Cited by 2 | Viewed by 3529
Abstract
In this work, the ferroelectric characteristic of a 5 nm Hf0.5Zr0.5O2 (HZO) metal-ferroelectric-insulator-semiconductor (MFIS) device is enhanced through strained complementary metal oxide semiconductor (CMOS)-compatible TiN electrode engineering. Strained TiN top-layer electrodes with different nitrogen (N) concentrations are deposited [...] Read more.
In this work, the ferroelectric characteristic of a 5 nm Hf0.5Zr0.5O2 (HZO) metal-ferroelectric-insulator-semiconductor (MFIS) device is enhanced through strained complementary metal oxide semiconductor (CMOS)-compatible TiN electrode engineering. Strained TiN top-layer electrodes with different nitrogen (N) concentrations are deposited by adjusting the sputtering process conditions. The TiN electrode with 18% N exhibits a compressive characteristic, which induces tensile stress in a 5 nm HZO film. A device with 18% N in TiN shows a higher remanent polarization (2Pr) and larger capacitance value than the compared sample, indicating that the strained TiN is promising for enhancing the ferroelectricity of sub-5 nm HZO devices. Full article
(This article belongs to the Special Issue Nanomaterials for Electron Devices)
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17 pages, 4264 KiB  
Article
Numerical Analysis of Oxygen-Related Defects in Amorphous In-W-O Nanosheet Thin-Film Transistor
by Wan-Ta Fan, Po-Tsun Liu, Po-Yi Kuo, Chien-Min Chang, I-Han Liu and Yue Kuo
Nanomaterials 2021, 11(11), 3070; https://0-doi-org.brum.beds.ac.uk/10.3390/nano11113070 - 15 Nov 2021
Cited by 6 | Viewed by 1952
Abstract
The integration of 4 nm thick amorphous indium tungsten oxide (a-IWO) and a hafnium oxide (HfO2) high-κ gate dielectric has been demonstrated previously as one of promising amorphous oxide semiconductor (AOS) thin-film transistors (TFTs). In this study, the more positive threshold [...] Read more.
The integration of 4 nm thick amorphous indium tungsten oxide (a-IWO) and a hafnium oxide (HfO2) high-κ gate dielectric has been demonstrated previously as one of promising amorphous oxide semiconductor (AOS) thin-film transistors (TFTs). In this study, the more positive threshold voltage shift (∆VTH) and reduced ION were observed when increasing the oxygen ratio during a-IWO deposition. Through simple material measurements and Technology Computer Aided Design (TCAD) analysis, the distinct correlation between different chemical species and the corresponding bulk and interface density of states (DOS) parameters were systematically deduced, validating the proposed physical mechanisms with a quantum model for a-IWO nanosheet TFT. The effects of oxygen flow on oxygen interstitial (Oi) defects were numerically proved for modulating bulk dopant concentration Nd and interface density of Gaussian acceptor trap NGA at the front channel, significantly dominating the transfer characteristics of a-IWO TFT. Furthermore, based on the studies of density functional theory (DFT) for the correlation between formation energy Ef of Oi defect and Fermi level (EF) position, we propose a numerical methodology for monitoring the possible concentration distribution of Oi as a function of a bias condition for AOS TFTs. Full article
(This article belongs to the Special Issue Nanomaterials for Electron Devices)
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11 pages, 4089 KiB  
Article
An Organic/Inorganic Nanomaterial and Nanocrystal Quantum Dots-Based Multi-Level Resistive Memory Device
by Sae-Wan Kim, JinBeom Kwon, Jae-Sung Lee, Byoung-Ho Kang, Sang-Won Lee, Dong Geon Jung, Jun-Yeop Lee, Maeum Han, Ok-Geun Kim, Gopalan Saianand and Daewoong Jung
Nanomaterials 2021, 11(11), 3004; https://0-doi-org.brum.beds.ac.uk/10.3390/nano11113004 - 09 Nov 2021
Cited by 3 | Viewed by 2220
Abstract
A cadmium selenide/zinc sulfide (CdSe/ZnS) quantum dot (QD)-based multi-level memory device with the structure [ITO/PEDOT:PSS/QDs/ZnO/Al:Al2O3/QDs/Al] was fabricated via a spin-coating method used to deposit thin films. Two layers of QD thin films present in the device act as charge [...] Read more.
A cadmium selenide/zinc sulfide (CdSe/ZnS) quantum dot (QD)-based multi-level memory device with the structure [ITO/PEDOT:PSS/QDs/ZnO/Al:Al2O3/QDs/Al] was fabricated via a spin-coating method used to deposit thin films. Two layers of QD thin films present in the device act as charge storage layers to form three distinct states. Zinc oxide (ZnO) and aluminum oxide (Al2O3) were added to prevent leakage. ZnO NPs provide orthogonality between the two QD layers, and a poly(3,4-ethylenedioxythio-phene): poly(styrenesulfonate) (PEDOT:PSS) thin film was formed for effective hole injection from the electrodes. The core/shell structure of the QDs provides the quantum well, which causes the trapping of injected charges. The resistance changes according to the charging and discharging of the QDs’ trap site and, as a result, the current through the device also changes. There are two quantum wells, two current changes, and three stable states. The role of each thin film was confirmed through I–V curve analysis and the fabrication conditions of each thin film were optimized. The synthesized QDs and ZnO nanoparticles were evaluated via X-ray diffraction, transmission electron microscopy, and absorbance and photoluminescence spectroscopy. The measured write voltages of the fabricated device were at 1.8 and 2.4 V, and the erase voltages were −4.05 and −4.6 V. The on/off ratio at 0.5 V was 2.2 × 103. The proposed memory device showed retention characteristics of ≥100 h and maintained the initial write/erase voltage even after 200 iterative operations. Full article
(This article belongs to the Special Issue Nanomaterials for Electron Devices)
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11 pages, 4153 KiB  
Article
Unipolar Parity of Ferroelectric-Antiferroelectric Characterized by Junction Current in Crystalline Phase Hf1−xZrxO2 Diodes
by Kuo-Yu Hsiang, Chun-Yu Liao, Jer-Fu Wang, Zhao-Feng Lou, Chen-Ying Lin, Shih-Hung Chiang, Chee-Wee Liu, Tuo-Hung Hou and Min-Hung Lee
Nanomaterials 2021, 11(10), 2685; https://0-doi-org.brum.beds.ac.uk/10.3390/nano11102685 - 12 Oct 2021
Cited by 6 | Viewed by 2788
Abstract
Ferroelectric (FE) Hf1−xZrxO2 is a potential candidate for emerging memory in artificial intelligence (AI) and neuromorphic computation due to its non-volatility for data storage with natural bi-stable characteristics. This study experimentally characterizes and demonstrates the FE and antiferroelectric [...] Read more.
Ferroelectric (FE) Hf1−xZrxO2 is a potential candidate for emerging memory in artificial intelligence (AI) and neuromorphic computation due to its non-volatility for data storage with natural bi-stable characteristics. This study experimentally characterizes and demonstrates the FE and antiferroelectric (AFE) material properties, which are modulated from doped Zr incorporated in the HfO2-system, with a diode-junction current for memory operations. Unipolar operations on one of the two hysteretic polarization branch loops of the mixed FE and AFE material give a low program voltage of 3 V with an ON/OFF ratio >100. This also benefits the switching endurance, which reaches >109 cycles. A model based on the polarization switching and tunneling mechanisms is revealed in the (A)FE diode to explain the bipolar and unipolar sweeps. In addition, the proposed FE-AFE diode with Hf1−xZrxO2 has a superior cycling endurance and lower stimulation voltage compared to perovskite FE-diodes due to its scaling capability for resistive FE memory devices. Full article
(This article belongs to the Special Issue Nanomaterials for Electron Devices)
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10 pages, 6347 KiB  
Article
Oxygen Concentration Effect on Conductive Bridge Random Access Memory of InWZnO Thin Film
by Chih-Chieh Hsu, Po-Tsun Liu, Kai-Jhih Gan, Dun-Bao Ruan and Simon M. Sze
Nanomaterials 2021, 11(9), 2204; https://0-doi-org.brum.beds.ac.uk/10.3390/nano11092204 - 27 Aug 2021
Cited by 3 | Viewed by 2566
Abstract
In this study, the influence of oxygen concentration in InWZnO (IWZO), which was used as the switching layer of conductive bridge random access memory, (CBRAM) is investigated. With different oxygen flow during the sputtering process, the IWZO film can be fabricated with different [...] Read more.
In this study, the influence of oxygen concentration in InWZnO (IWZO), which was used as the switching layer of conductive bridge random access memory, (CBRAM) is investigated. With different oxygen flow during the sputtering process, the IWZO film can be fabricated with different oxygen concentrations and different oxygen vacancy distribution. In addition, the electrical characteristics of CBRAM device with different oxygen concentration are compared and further analyzed with an atomic force microscope and X-ray photoelectron spectrum. Furthermore, a stacking structure with different bilayer switching is also systematically discussed. Compared with an interchange stacking layer and other single layer memory, the CBRAM with specific stacking sequence of bilayer oxygen-poor/-rich IWZO (IWZOx/IWZOy, x < y) exhibits more stable distribution of a resistance state and also better endurance (more than 3 × 104 cycles). Meanwhile, the memory window of IWZOx/IWZOy can even be maintained over 104 s at 85 °C. Those improvements can be attributed to the oxygen vacancy distribution in switching layers, which may create a suitable environment for the conductive filament formation or rupture. Therefore, it is believed that the specific stacking bilayer IWZO CBRAM might further pave the way for emerging memory applications. Full article
(This article belongs to the Special Issue Nanomaterials for Electron Devices)
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13 pages, 5787 KiB  
Article
Semiconductor Chip Electrical Interconnection and Bonding by Nano-Locking with Ultra-Fine Bond-Line Thickness
by Jielin Guo, Yu-Chou Shih, Roozbeh Sheikhi, Jiun-Pyng You and Frank G. Shi
Nanomaterials 2021, 11(8), 1901; https://0-doi-org.brum.beds.ac.uk/10.3390/nano11081901 - 24 Jul 2021
Cited by 3 | Viewed by 1899
Abstract
The potential of an innovation for establishing a simultaneous mechanical, thermal, and electrical connection between two metallic surfaces without requiring a prior time-consuming and expensive surface nanoscopic planarization and without requiring any intermediate conductive material has been explored. The method takes advantage of [...] Read more.
The potential of an innovation for establishing a simultaneous mechanical, thermal, and electrical connection between two metallic surfaces without requiring a prior time-consuming and expensive surface nanoscopic planarization and without requiring any intermediate conductive material has been explored. The method takes advantage of the intrinsic nanoscopic surface roughness on the interconnecting surfaces: the two surfaces are locked together for electrical interconnection and bonding with a conventional die bonder, and the connection is stabilized by a dielectric adhesive filled into nanoscale valleys on the interconnecting surfaces. This “nano-locking” (NL) method for chip interconnection and bonding is demonstrated by its application for the attachment of high-power GaN-based semiconductor dies to its device substrate. The bond-line thickness of the present NL method achieved is under 100 nm and several hundred times thinner than those achieved using mainstream bonding methods, resulting in a lower overall device thermal resistance and reduced electrical resistance, and thus an improved overall device performance and reliability. Different bond-line thickness strongly influences the overall contact area between the bonding surfaces, and in turn results in different contact resistance of the packaged devices enabled by the NL method and therefore changes the device performance and reliability. The present work opens a new direction for scalable, reliable, and simple nanoscale off-chip electrical interconnection and bonding for nano- and micro-electrical devices. Besides, the present method applies to the bonding of any surfaces with intrinsic or engineered surface nanoscopic structures as well. Full article
(This article belongs to the Special Issue Nanomaterials for Electron Devices)
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9 pages, 2074 KiB  
Article
Improved Device Distribution in High-Performance SiNx Resistive Random Access Memory via Arsenic Ion Implantation
by Te-Jui Yen, Albert Chin and Vladimir Gritsenko
Nanomaterials 2021, 11(6), 1401; https://0-doi-org.brum.beds.ac.uk/10.3390/nano11061401 - 25 May 2021
Cited by 17 | Viewed by 2560
Abstract
Large device variation is a fundamental challenge for resistive random access memory (RRAM) array circuit. Improved device-to-device distributions of set and reset voltages in a SiNx RRAM device is realized via arsenic ion (As+) implantation. Besides, the As+-implanted [...] Read more.
Large device variation is a fundamental challenge for resistive random access memory (RRAM) array circuit. Improved device-to-device distributions of set and reset voltages in a SiNx RRAM device is realized via arsenic ion (As+) implantation. Besides, the As+-implanted SiNx RRAM device exhibits much tighter cycle-to-cycle distribution than the nonimplanted device. The As+-implanted SiNx device further exhibits excellent performance, which shows high stability and a large 1.73 × 103 resistance window at 85 °C retention for 104 s, and a large 103 resistance window after 105 cycles of the pulsed endurance test. The current–voltage characteristics of high- and low-resistance states were both analyzed as space-charge-limited conduction mechanism. From the simulated defect distribution in the SiNx layer, a microscopic model was established, and the formation and rupture of defect-conductive paths were proposed for the resistance switching behavior. Therefore, the reason for such high device performance can be attributed to the sufficient defects created by As+ implantation that leads to low forming and operation power. Full article
(This article belongs to the Special Issue Nanomaterials for Electron Devices)
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Review

Jump to: Research

19 pages, 30588 KiB  
Review
Factors Affecting Surface Plasmon Coupling of Quantum Wells in Nitride-Based LEDs: A Review of the Recent Advances
by Muhammad Farooq Saleem, Yi Peng, Kai Xiao, Huilu Yao, Yukun Wang and Wenhong Sun
Nanomaterials 2021, 11(5), 1132; https://0-doi-org.brum.beds.ac.uk/10.3390/nano11051132 - 27 Apr 2021
Cited by 4 | Viewed by 2435
Abstract
Surface plasmon (SP)-enhanced quantum-well (QW) LEDs have proved their potential in replacing conventional lighting devices for their high-performance capabilities in ultraviolet (UV), blue and green spectral ranges. The SP-enhanced QW-LEDs have applications in light emission enhancement, light polarization, color conversion, and speed modulation. [...] Read more.
Surface plasmon (SP)-enhanced quantum-well (QW) LEDs have proved their potential in replacing conventional lighting devices for their high-performance capabilities in ultraviolet (UV), blue and green spectral ranges. The SP-enhanced QW-LEDs have applications in light emission enhancement, light polarization, color conversion, and speed modulation. The electric field of the plasmonic mode of a metal couples with the exciton energy of QWs in resonance results in efficiency enhancement to several folds. The strength of the SP–QW coupling is mainly influenced by the type of metal used for SP enhancement, the metal nanostructure geometry, and the penetration depth of the SP fringing field in the p-GaN. The use of an appropriate dielectric interlayer between the metal and the p-GaN allows further control over SP resonance with QW emission wavelength. The penetration depth defines the p-GaN thickness and the QW period number for effective SP–QW coupling. The optimization of these parameters is key to achieve high efficiencies in SP-enhanced QW-LEDs for various applications. This review explains the SP enhancement mechanism and the key challenges facing the SP enhancement of QW-LEDs. The main factors that affect the SP–QW coupling have been explained in detail based on recent reports devoted to this field. Full article
(This article belongs to the Special Issue Nanomaterials for Electron Devices)
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