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Forward Error Correction Architectures for beyond 5G New Radio Wireless Communication

A special issue of Sensors (ISSN 1424-8220). This special issue belongs to the section "Communications".

Deadline for manuscript submissions: closed (30 June 2022) | Viewed by 3602

Special Issue Editor


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Guest Editor
Department of Information and Communication Engineering, Inha University, Incheon 22212, Republic of Korea
Interests: VLSI architectures for DSP; forward error correction architectures; hardware cryptographic architectures; artificial intelligent HW design
Special Issues, Collections and Topics in MDPI journals

Special Issue Information

Dear Colleagues,

Forward error correction (FEC) maintains an extremely crucial role in data transmission systems. In the early 1960s, R. Gallager introduced low-density parity-check (LDPC) codes. After that, in 1996, they were rediscovered by MacKay and Neal. Since their performance in error correction and implementation, LDPC codes have been attracting considerable attention from the research community and have been selected as one of the channel coding schemes for 5G new radio wireless communication.

Polar codes are the first linear block error correcting codes that can provably achieve channel capacity for any given binary-input discrete memoryless channels (B-DMCs). Due to their undoubted significance, research on polar codes has drawn increasing attention from both academia and industry. Compared to classic error correcting codes, polar codes enjoy advantages, including higher coding gain, no error floor, better reliability, and lower power costs under equivalent complexity. However, the channel coding schemes, such as LDPC codes, polar codes, and their variant, will find more commercial development in the future applications beyond 5G. Furthermore, establishing efficient architectures, where there is a trade-off between low hardware complexity, high throughput, low power, etc., represents a present challenge. Therefore, the efficiencies in designs of FEC architectures are greatly desirable.

The main purpose of this Special Issue will focus on seeking high-efficient FEC architecture designs that highlight emerging applications for 5G and beyond. The topics of interest include, but are not limited to, the following:

  • Architectures for LDPC codes, polar codes, and their variants;
  • Algebraic constructions of low-density graph codes;
  • Hardware FEC architectures;
  • Non-binary LDPC decoder architectures;
  • Hardware implementation of FEC architectures;
  • Techniques for reducing hardware complexity of FEC designs;
  • Channel-coded modulations.

Prof. Dr. Hanho Lee
Guest Editor

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Keywords

  • Forward error correction (FEC)
  • Error correction codes (ECC)
  • LDPC codes
  • Polar codes
  • Non-binary LDPC (NB-LDPC) codes
  • Fifth generation (5G)
  • New radio (NR)

Published Papers (1 paper)

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Research

13 pages, 976 KiB  
Article
Low-Complexity Multi-Size Circular-Shift Network for 5G New Radio LDPC Decoders
by Tuy Tan Nguyen, Tram Thi Bao Nguyen and Hanho Lee
Sensors 2022, 22(5), 1792; https://0-doi-org.brum.beds.ac.uk/10.3390/s22051792 - 24 Feb 2022
Cited by 2 | Viewed by 1982
Abstract
This paper presents a low-complexity multi-size circular-shift network (MCSN) structure for 5th-generation (5G) New Radio (NR) quasi-cyclic low-density parity-check (QC-LDPC) decoders. In particular, a fine-coarse approach-based multi-size cyclic shift network, which decomposes the cyclic shift size into fine part and coarse part, is [...] Read more.
This paper presents a low-complexity multi-size circular-shift network (MCSN) structure for 5th-generation (5G) New Radio (NR) quasi-cyclic low-density parity-check (QC-LDPC) decoders. In particular, a fine-coarse approach-based multi-size cyclic shift network, which decomposes the cyclic shift size into fine part and coarse part, is introduced. The proposed MCSN structure is composed of a pre-rotator performing the fine part of the cyclic shift, and a main rotator executing the coarse part of the cyclic shift. In addition, a forward routing circular-shift (FRCS) network, which is based on the barrel shifter and the forward routing process is presented. The proposed switch network is able to support all 51 different submatrix sizes as defined in the 5G NR standard through an efficient forward routing switch network and help reduce the hardware complexity using a cyclic shift size decomposition method. The proposed MCSN is analyzed, and indicates a substantial reduction in the hardware complexity. The experimental results on TSMC 65-nm CMOS technology show that the proposed MCSN structure for 5G NR LDPC decoder offers an area saving up to 56.75% compared to related works in the literature. Full article
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