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Hardware–Software Co-Design for Decimal Multiplication

Graduate School of Science and Technology, Nara Institute of Science and Technology, Ikoma 630-0192, Japan
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Received: 28 December 2020 / Revised: 18 January 2021 / Accepted: 23 January 2021 / Published: 27 January 2021
Decimal arithmetic using software is slow for very large-scale applications. On the other hand, when hardware is employed, extra area overhead is required. A balanced strategy can overcome both issues. Our proposed methods are compliant with the IEEE 754-2008 standard for decimal floating-point arithmetic and combinations of software and hardware. In our methods, software with some area-efficient decimal component (hardware) is used to design the multiplication process. Analysis in a RISC-V-based integrated co-design evaluation framework reveals that the proposed methods provide several Pareto points for decimal multiplication solutions. The total execution process is sped up by 1.43× to 2.37× compared with a full software solution. In addition, 7–97% less hardware is required compared with an area-efficient full hardware solution. View Full-Text
Keywords: decimal arithmetic; decimal multiplication; decimal floating-point; hardware-software co-design decimal arithmetic; decimal multiplication; decimal floating-point; hardware-software co-design
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MDPI and ACS Style

Mian, R.-u.-h.; Shintani, M.; Inoue, M. Hardware–Software Co-Design for Decimal Multiplication. Computers 2021, 10, 17. https://0-doi-org.brum.beds.ac.uk/10.3390/computers10020017

AMA Style

Mian R-u-h, Shintani M, Inoue M. Hardware–Software Co-Design for Decimal Multiplication. Computers. 2021; 10(2):17. https://0-doi-org.brum.beds.ac.uk/10.3390/computers10020017

Chicago/Turabian Style

Mian, Riaz-ul-haque; Shintani, Michihiro; Inoue, Michiko. 2021. "Hardware–Software Co-Design for Decimal Multiplication" Computers 10, no. 2: 17. https://0-doi-org.brum.beds.ac.uk/10.3390/computers10020017

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