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Article

Improved Frequency Compensation Technique for Three-Stage Amplifiers

1
Electronic Systems Department, Universidad Autonoma de Aguascalientes, Aguascalientes 20131, Mexico
2
Electrical & Computer Engineering, New Mexico State University, Las Cruces, NM 88003, USA
3
School of Engineering and Sciences, Tecnologico de Monterrey, Monterrey 64849, Mexico
*
Author to whom correspondence should be addressed.
Academic Editor: Fabian Khateb
J. Low Power Electron. Appl. 2021, 11(1), 11; https://0-doi-org.brum.beds.ac.uk/10.3390/jlpea11010011
Received: 25 January 2021 / Revised: 6 March 2021 / Accepted: 8 March 2021 / Published: 12 March 2021

Abstract

Improved frequency compensation is proposed for a three-stage amplifier with reduced total capacitance, improved slew rate, and reduced settling time. The proposed compensation uses an auxiliary feedback to increase the total effective compensation capacitance without loading the output node. The proposed compensation scheme is validated in simulation by implementing a three-stage amplifier driving 10 pF load capacitor in a 0.18 μm CMOS process. A detailed comparison of the compensation with a conventional nested Miller compensation is also presented. The simulation results showed a reduction in total compensation capacitance and improvement in slew rate compared to conventional nested Miller compensation and the other reported techniques in the literature.
Keywords: frequency compensation; nested Miller compensation; high slew rate; low settling time; three-stage amplifier; Routh–Hurwitz stability criterion frequency compensation; nested Miller compensation; high slew rate; low settling time; three-stage amplifier; Routh–Hurwitz stability criterion

1. Introduction

Recent furtherance in the field of analog circuit design allowed for the evolution of new electronic devices supporting various applications. A wide market opportunity has been created for battery-operated portable devices such as smartphones, health monitor watches, home assistants, earphones, etc. The two essential characteristics of devices for such applications are device runtime on battery and the form-factor [1,2]. The device runtime is extended by either using a low power consumption circuits for the application or using high-efficiency DC–DC converters. Restriction of power consumption on the application core circuitry can compromise the performance of system. The use of high-efficiency DC–DC converters increases the runtime, and the use of fully-integrated converters, such as switched-capacitor converters, further helps to reduce the overall solution size [3]. Additionally, increasing the switching frequency of the DC–DC converter reduces the size of the energy element such as the inductor or capacitor [4].
Switching converters have output voltage ripples that make them not suitable for all applications. Low drop-out (LDO) regulators are popular when a clean and quiet power supply is required [5]. The LDO regulators are efficient when the output voltage is close to the input supply voltage, and its efficiency is the ratio of output to input voltage. As the supply voltage rails are reduced in lower CMOS process technologies, where the length of the FET is shrunk, the gain obtained from a single stage amplifier is lower. The DC accuracy and transient response of an LDO is directly set by the closed-loop gain and bandwidth of the error amplifier. Moreover, the design for such high frequency requires transistor models to include all the parasitic capacitances [6].
Multi-stage amplifiers are used for overall high gain. Increasing the number of stages creates additional high impedance nodes making the amplifier unstable due to multiple poles [7]. A simple Miller compensation (SMC) and nested Miller compensation (NMC) are commonly used in two-stage and three-stage amplifiers for closed-loop stability, respectively. However, these multi-stage amplifiers suffers from bandwidth reduction as explained in [8,9]. In deep submicron CMOS process, a three-stage amplifier is sufficient to achieve acceptable overall gain for many applications.
Nested Miller compensation (NMC) is a popular frequency compensation technique used to stabilize three-stage amplifiers [10], this compensation scheme is shown in Figure 1. It must be noticed that if R C is 0, the circuit shown in Figure 1 configures to a traditional NMC circuit. The compensation in a NMC scheme uses two capacitors connected between the output node and intermediate nodes of the amplifier. The nulling resistor, R C allows cancellation of the RHP zero created by g m 10 , and increasing R C > 1 / g m 10 creates an LHP zero which helps in phase boost [11]. This variant of an NMC circuit is denominated as nested Miller compensation with nulling resistor (NMCNR). The transfer function of NMC with nulling resistor is given by:
H ( s ) = A D C 1 C C 2 ( 1 g m 10 R C ) s C C 1 C C 2 g m 7 g m 10 s 2 1 + s w p 3 d B 1 + C C 2 ( k 1 g m 10 g m 7 ) g m 7 g m 10 s + C C 2 C L k 2 g m 7 g m 10 s 2
where A D C = g m 1 R 1 g m 7 R 3 g m 10 R O , w p 3 d B = 1 R 1 ( g m 7 R 3 g m 10 R O ) C C 1 , k 1 = 1 + g m 7 R c , k 2 = 1 + R c R 2 . Resistors R 1 , R 2 and R 3 are the output impedance at nodes V 1 , V 2 and V 3 , respectively. The transfer function of a traditional NMC can be obtained by evaluating the Equation (1) with R C = 0 .
NMC has one RHP zero, one LHP zero and three LHP poles when k 1 g m 10 g m 7 . As the compensation capacitors are loading the output, this amplifier suffers from poor slew rate at high frequency. Under the slewing condition, V O is required to pull up by charging the load capacitor C L , the internal node V 3 is pulled down towards the ground to allow more current to flow through M 10 . When V 3 is pulled low, the compensation capacitor C C 2 appears to be in parallel with C L loading the output node causing a slow slew rate. Moreover, this changes the overall compensation of the circuit where C C 2 disappears and the entire circuit is compensated by C C 1 only. This changes the amplifier stability conditions considerably and increases the settling time. To design a stable NMC amplifier, the compensation capacitors must be chosen with the following conditions [7]:
C C 1 = 4 g m 1 g m 10 C L
C C 2 = 2 g m 7 g m 10 C L
The load capacitor affects the location of non-dominant poles and gain bandwidth (GBW) product making this compensation suitable only for applications with small range of load capacitance. GBW for NMC is given by [12]:
G B W = g m 1 C C 1 = 1 4 g m 10 C L
Reverse nested Miller compensation (RNMC) is another compensation where the output of the first stage of the amplifier is loaded with both compensation capacitors causing the internal voltage to be slew limited [13,14]. Referring to Figure 2, RNMC requires non-inverting configuration in the third stage between V 2 and V O . This limits the driving capability of the output stage due to limited voltage swing on V 2 A . The transfer function of RNMC is given by [13]:
H ( s ) = A D C 1 C C 2 g m 6 + C C 1 g m 6 g m 9 R 2 s C C 1 C C 2 g m 6 g m 9 s 2 1 + s ω P 1 1 + C C 2 C L g m 9 C C 1 C C 2 g m 6 + C C 2 g m 9 s + C C 2 C L g m 6 g m 9 s 2
where A D C = g m 1 R 1 g m 6 R 2 g m 9 R O , and ω P 1 = 1 / R 1 ( g m 6 R 2 g m 9 R O ) C C 1 ) .
Multiple advanced compensation techniques are published in the literature to extend the bandwidth, such as the double pole–zero canceling technique [15], multipath NMC (MNMC) [10], nested Gm-C compensation (NGCC) [16] and damping factor control frequency compensation (DFCFC) [7]. However, all these compensation techniques have strong dependency on output load capacitor for stability. NMC and RNMC with combination of voltage and current buffers are proposed in the literature to isolate the output node or compensate for RHP zero [17]. The proposed compensation scheme described in the next section solves these challenges.

2. Proposed Improved Frequency Compensation

An improved frequency compensation method is proposed using a single capacitor with auxiliary feedback loop connected between the two intermediate nodes as shown in Figure 3. Typically, the internal nodes of a multi-stage amplifier have a finite voltage swing compared to its output voltage swing. The use of the compensation capacitor on the high-swing output node severely affects the circuit slew rate compared to loading compensation capacitors on internal nodes where the voltage swing is limited. Using this advantage, the proposed compensation scheme uses internal circuit nodes V 1 and V 2 for compensation.
Referring to Figure 3, M 0 4 , M 5 , 6 and M 7 , 8 are the three stages of the amplifier. M 9 12 are used for compensation, where M 9 and M 10 generate a Miller effect over C C adding one LHP zero-pole pair to the amplifier transfer function. The small-signal model for the proposed compensation is shown in Figure 4, where R 1 , R 2 , R 3 , R 4 and R O are the output impedance, and C 1 , C 2 , C 3 , C 4 are the total parasitic capacitances at nodes V 1 , V 2 , V 3 , V 4 and C L is the load capacitor at node V O . The transfer function is given by:
H ( s ) = A D C 1 + R 3 C C 1 s 1 + s ω p 3 d B 1 + R O C L s 1 + C 2 g m 6 s + C 1 C 2 g m 10 g m 6 s 2
where A D C = g m 1 R 1 g m 6 R 2 g m 8 R O , and ω p 3 d B = 1 R 1 ( g m 6 R 2 g m 10 R 3 ) C C 1 .
The proposed compensation has one LHP zero and four LHP poles. Two of these poles ω p 2 , 3 are high frequency poles set by C 1 and C 2 parasitic capacitaces at nodes V 1 and V 2 , respectively. Observe that C 4 is connected to a low impedance node and the pole associated with C 4 is located at a very high frequency and can be neglected. Similarly, parasitic capacitance C 3 is connected to a node where the effect of C C 1 capacitor is dominant; therefore, it can be also neglected. Additionally, a pole-zero cancellation can be achieved by selecting R 3 C C 1 R O C L , and this condition is controlled by the relationship between the transconductances g m 8 and g m 10 , where g m 10 = n × g m 8 . The compensation capacitor C C 1 can be selected by using C C 1 = C L / n . Observe that the compensation capacitor C C 1 can be reduced by increasing the output transconductace g m 10 . The dominant pole ω p 3 d b at node V 1 is set by g m 6 × R 2 and g m 10 × R 3 , where these gains divide the node frequency pole ( 1 / ( R 1 C C 1 ) to move the pole to a low frequency. Sizing C C 1 adequately, the non-dominant pole ( 1 + R O C L s ) can be compensated. If parasitic capacitors are neglected such as most of the models reported in the literature, the transfer of Equation (6) can be approximated to a single pole transfer function. The pole zero location illustration is shown in Figure 5, where ω p H F and ω Z H F are a very high frequency pole and zero from intermediate nodes.
Phase margin is given by:
P M = 180 tan 1 G B W ω p 3 d b tan 1 G B W p 1 + tan 1 G B W z 1 tan 1 G B W p 2 tan 1 G B W p 3
P M 180 tan 1 G B W ω p 3 d b
Observe that the pole-zero cancelled transfer function in Equation (9) yields similar response when well-known techniques such as voltage followers, current followers, and multipath Miller approaches are used [15]; except that in the proposed compensation, the second and third poles are located at high frequency, which is set by parasitic capacitances at the output of the first and second stages instead of compensation capacitors to provide a phase boost.
H ( s ) = A D C 1 1 + s ω p 3 d B 1 + C 2 g m 6 s + C 1 C 2 g m 10 g m 6 s 2
Referring to the slew-rate degradation in NMC, the proposed compensation scheme remains connected in the original configuration during slewing condition, and no settling time degradation is observed. The proposed compensation can be used for improved load transient response in LDOs where high output load capacitance is used.

3. Stability Analysis

Phase margin and gain margin are the two essential parameters used to characterize the stability of an amplifier, and they are measured in an open-loop configuration. Nevertheless, these parameters do not guarantee a good stability in closed-loop operation as explained in detail in [1]. Routh–Hurwitz stability criterion is an alternative method that can be used to identify conditions that make the closed-loop configuration unstable [18,19].
For Routh–Hurwitz stability criterion, consider an unitary feedback with a closed-loop gain transfer function given by T ( s ) in Equation (10). Observe that the open-loop zero of H ( s ) in Equation (6) is part of the characteristic polynomial, and the closed-loop poles positions in the denominator are modified. Therefore, a closed-loop stability should be analyzed using Routh–Hurwitz stability criterion.
T ( s ) = A D C ( 1 + C C 1 R 3 s ) ( 1 + C L R O s ) 1 + s ω p 3 d B C 1 C 2 s 2 g m 1 0 g m 6 + C 2 s g m 6 + 1 + A D C 1 + C C 1 R 3 s
The characteristic polynomial of poles in the Equation (10) can be simplified and represented by:
a 4 s 4 + a 3 s 3 + a 2 s 2 + a 1 s + a 0
According to the Routh–Hurwitz stability criterion, it can be concluded that the closed-loop transfer function with fourth-degree polynomial characteristics should meet the following criteria to avoid any RHP pole creation [1]:
a 2 > a 4 · a 1 a 3
Solving for parameters a 4 , a 3 , a 2 and a 1 from the characteristic polynomial of the transfer function T ( s ) , the closed-loop stability criterion for the proposed compensation scheme is given by:
C L > C 1 g m 1 g m 8 g m 10 2

4. Simulation Results

A conventional three-stage amplifier with the proposed improved frequency compensation is implemented in a 0.18 μm CMOS process. A conventional three-stage amplifier with NMC, NMCNR and RNMC is also implemented for comparison. All amplifiers are designed to drive a load capacitance of 10 pF with VDD = 1.8 V and DC gain = 90 dB. Transistor parameters are given in Table 1.
The transfer function shown in Equation (6) is verified with a simulation of transfer function equation and a transistor level implementation. The ac response of both implementations is shown in Figure 6. Observe that both AC responses overlap with each other to match up to high frequency. The mismatch at high frequency is due to high-frequency parasitic capacitances that are neglected in the transfer function for simplicity.
Referring to Figure 7, the AC response of the proposed compensation scheme is compared with NMC, NMCNR and RNMC compensation schemes. Observe that the response of the proposed scheme almost overlaps with the RNMC scheme, with the difference that the proposed compensation moves high-frequency poles to a much higher frequency. It is clear that the stability of the other compensation scheme is conditioned to maintain a good separation between their high frequency poles set by compensation capacitors, and the high frequency poles set by parasitic capacitances. This limits the highest achievable GBW with relatively good stability, whereas in the proposed compensation scheme, the design can operate with the highest GBW with relatively good stability as no high frequency poles are added. The only limitation is by the increment of parasitic capacitors obtained by growing the output stage transistors. Referring to Figure 7, the high-frequency improvement achieved by this compensation scheme increased the phase and gain margin showing better stability parameters with respect to the other compensation scheme used to compare the performance of the proposed compensation scheme.
The settling time improvement is validated with large-signal and small-signal step response stimulus at different rise and fall times. For large-signal settling response, a 500 mV pulse with a rise and fall time of 300 ns is applied with a DC offset of 0.9 V to all amplifiers with different compensations, and the response is shown in Figure 8. Since NMC amplifier has a lower GBW and not good gain margin, some oscillations can be observed in its output signal. NMCNR, RNMC and the proposed compensation showed higher GBW with better phase margin and gain margin, and no oscillations are observed. An intentional large offset is added to the figures for readability.
Small-signal settling is validated by applying 50 mV pulse with a rise and fall time of 50 ns as shown in Figure 9a. Observe that the proposed compensation does not show any voltage ring or peaking due to increased phase margin. Additionally, a large signal settling of 500 mV with a rise and fall time of 50 ns representing the slewing condition is shown in Figure 9b. Observe that the NMC shows a degraded response and higher fall settling time, whereas the proposed compensation scheme has no degradation during slewing condition. Similar responses are seen in NMCNR and RNMC. RNMC shows reduced fall settling degradation and this can be attributed to the fact that in order to design a stable amplifier, the trasconductance of second stage must be increased, which increases the slew rate and power consumption.
The total compensation capacitance required is reduced from 12 pF with NMC, 5.5 pF with NMCNR, 3.5 pF with RNMC to 2 pF and no nulling resistor. The phase margin is improved from 53 deg to 82.5 deg and the gain margin from 4.71 dB to 21.9 dB when compared with NMC as the proposed compensation scheme do not add high-frequency poles. Moreover, a significant improvement in the slew rate is observed with the proposed compensation. The proposed compensation is compared with the literature and is shown in Table 2, where unity gain frequency (UGF), DC gain ( A 0 ), phase margin (PM), gain margin (GM), total compensation capacitance ( C C ), total compensation resistance ( R C ), load capacitance ( C L ), average slew rate (SR), power consumption (P), and figure of merits (FOM) are given. Observe that the proposed scheme slew rate is 146% higher than NMC and 60% higher than NMCNR. RNMC has similar slew rate but consumes high power. Three different figures of merit (FOMs) are used to compare the performance of the proposed compensation scheme and are shown below. A FOM proposed in [14], F O M R considers GBW, total sum of all transconductances and compensation capacitances. Observe that the proposed compensation scheme has higher F O M S , F O M L , F O M I S , F O M I L , and F O M R . A summary of stability and settling time results is the proposed compensation are shown in Table 3.
F O M S = G B W H z · C L V D D · I D D ( M H z · p F / m W )
F O M L = S R · C L V D D · I D D ( V / μ s · p F / m W )
F O M R = ω G B W · C L g m 1 + g m 2 + g m 3 + g m C O M P
The process corner simulation results at different temperatures are shown in Table 4. Observe that the phase margin and gain margin are maintained greater than 81 and 22 dB, respectively. A maximum deviation of 3.9 MHz is observed for unity-gain frequency from typical process and room temperature. Despite the process variation, the proposed compensation scheme maintained good stability for a temperature range from 40 to 125 .

5. Conclusions

The proposed compensation scheme for a three-stage amplifier uses lower compensation capacitance to achieve dynamic response superior to NMC and NMCNR, and is similar to RNMC without consuming higher power nor using a nulling resistor. The proposed compensation allows the amplifier to operate with the highest GBW with relatively good stability as no high frequency compensation poles are added. The slew-rate degradation observed in NMC is solved with the proposed compensation scheme, where the intended compensation remains connected in the original configuration during slewing condition. The proposed compensation can be used for improved load transient response in LDOs.

Author Contributions

The research problem is identified, executed, and solved by A.R.L. conducted a feasibility study through simulation, and transfer function calculations. A.V. conducted the literature review and advised on the architecture and wrote the initial draft manuscript. L.A.F.O., L.A.C.M., and D.M.F. supervised research that includes and is not limited to project administration, design and simulation results review, manuscript review, and corrections. All authors have read and agreed to the published version of the manuscript.

Funding

This research received no external funding.

Institutional Review Board Statement

Not applicable.

Informed Consent Statement

Not applicable.

Acknowledgments

This work has been supported by PRODEP program from SEP (Secretariat of Public Education, Mexico) and Universidad Autonoma de Aguascalientes, Aguascalientes, Mexico.

Conflicts of Interest

The authors declare no conflict of interest.

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Figure 1. Nested Miller compensation.
Figure 1. Nested Miller compensation.
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Figure 2. Reverse nested Miller compensation.
Figure 2. Reverse nested Miller compensation.
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Figure 3. Proposed improved frequency compensation.
Figure 3. Proposed improved frequency compensation.
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Figure 4. Small signal model of the proposed improved frequency compensation.
Figure 4. Small signal model of the proposed improved frequency compensation.
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Figure 5. Pole zero location illustration (not to scale).
Figure 5. Pole zero location illustration (not to scale).
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Figure 6. AC response of proposed frequency compensation with transfer function and transistors.
Figure 6. AC response of proposed frequency compensation with transfer function and transistors.
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Figure 7. AC response of proposed frequency compensation compared with nested Miller compensation.
Figure 7. AC response of proposed frequency compensation compared with nested Miller compensation.
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Figure 8. Large signal settling of proposed and nested Miller compensation with 300 ns rise and fall time. An intentional offset is added to the figure to distinguish the signals.
Figure 8. Large signal settling of proposed and nested Miller compensation with 300 ns rise and fall time. An intentional offset is added to the figure to distinguish the signals.
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Figure 9. Output voltage signal settling of proposed and nested Miller compensation. An intentionaloffset is added to the figure to distinguish the signals.
Figure 9. Output voltage signal settling of proposed and nested Miller compensation. An intentionaloffset is added to the figure to distinguish the signals.
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Table 1. Transistor parameters.
Table 1. Transistor parameters.
DevicesValueUnits
W L M 0 x2, M 1 , M 2 , M 5 , M 7 x5, M 9 , M 11 1.8/0.72μm/μm
M 3 , M 4 , M 6 , M 8 x5, M 10 , M 12 7.2/0.72μm/μm
g m M 1 , M 2 , M 6 , M 9 , M 10 , M 12 160μV/A
M 8 800μV/A
I B I A S 125μA
V D D 1.8V
Table 2. Results comparison.
Table 2. Results comparison.
[20][10][16][21][7]
TypeProposedNMCNMCNRRNMCDPZCMNMCNGCCNMCFNRDFCFC
Process (μm)0.180.180.180.180.350.350.350.350.35
UGF (MHz)12.313.26.7610.20.40.540.250.80.96
C C ( p F ) 2125.53.549.51419428.735
R C (k Ω )0060-----
C L ( p F ) 10101010100100100100100
SR ( V / μ s )166.510150.3750.40.270.750.78
P (μW)495450450675345431365345372
FOM s 2497115015111612568232256
FOM L 32314422222210993101217208
FOM IS 447128270272232250136472512
FOM IL 5810.180.350.36218186202434416
FOM R 0.6250.180.350.360.240.210.130.390.56
Table 3. Stability and settling time results.
Table 3. Stability and settling time results.
TypeProposedNMCNMCNRRNMC
UGF (MHz)12.313.26.7610.2
A 0 (dB)90.790.790.790.7
PM (deg)82.5536162
GM (dB)224.719.510.8
t r 1 / t f 1 (ns) V S = 50 mV, t r , f = 50 ns77/93286/28978/12667/63
t r 2 / t f 2 (ns) V S = 0.5 V, t r , f = 50 ns297/297338/374307/310300/300
t r 2 / t f 2 (ns) V S = 0.5 V, t r , f = 300 ns65/72213/41478/23565/125
Table 4. Process corners at different temperatures.
Table 4. Process corners at different temperatures.
Temperature 40 C
CornerTTSSFFSFFS
UGF (MHz)15.4814.7716.4814.9316.23
Phase Margin (deg)838382.783.4582.35
Gain Margin (dB)23.7223.7723.624.2523.11
Temperature 27 C
CornerTTSSFFSFFS
UGF (MHz)12.311.613.111.7612.86
Phase Margin (deg)82.586.5383.183.8782.74
Gain Margin (dB)2224.372424.6323.57
Temperature 125 C
CornerTTSSFFSFFS
UGF (MHz)9.298.75108.969.83
Phase Margin (deg)8484.2683.784.583.4
Gain Margin (dB)25.1225.3224.7525.6624.4
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