Wafer-Level Packaging for Heterogeneous Integration

Dear Colleagues,

Miniaturization, performance improvement, enhanced product functionality, and cost reduction are the primary driving forces behind contemporary innovations in packaging. These factors have led to the development of new architectures that combine a wide range of different technologies. Wafer packaging and heterogeneous integration are at the forefront of semiconductor technology, enabling the creation of smaller, more powerful, and versatile electronic devices at a lower cost. Recent innovations have pushed the boundaries of what is possible in the field of electronics and have transformed our digital world. The objective of this Special Issue is to present the latest developments in wafer packaging and heterogeneous integration, including technologies such as redistribution layers, wafer bumping, through-via technologies, fan-out-wafer-level-packaging, wafer-to-wafer bonding, chip-to-wafer bonding, wafer thinning, 3D stacking and chiplets.

We look forward to receiving your contributions.

Dr. Jean-Charles Souriau
Guest Editor

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• wafer-level packaging
• heterogeneous integration
• fan-out-WLP
• system-on-wafer
• silicon interposer