High Step-Up Three-Level Soft Switching DC-DC Converter for Photovoltaic Generation Systems

Abstract

In this paper, a high step-up three-level DC–DC converter with a symmetric structure for PV application is proposed. The converter has high voltage gain. This is achieved due to the use of two high step-up cells and two resonant paths in its structure. The converter has low input current ripples and the voltage stress across all switches is equal to half of the output voltage. The proposed converter uses simple pulse–width modulation (PWM) to trigger the switches. Hence, the proposed converter benefits from a simple structure and control circuit. All semiconductor devices are turned on/off under ZCS conditions. Thus, the switching losses are decreased, and the total efficiency is increased. The converter is implemented and tested through a laboratory prototype. The experimental results verify the theoretical analysis.

1. Introduction

The demand for photovoltaic (PV) power generation has increased significantly in recent years. Many reasons are effective to reach this aim, such as the reduction of PV cost and increment of PV power generation capacity. In addition, global warming and environmental pollution are other important reasons that have forced different countries to use renewable energy sources, especially PV to generate electricity instead of using fossil fuels [1,2]. In a grid-connected PV system, the voltage level, which is generated by PV arrays, cannot be used to feed the grid-connected side. In fact, the low input voltage should be boosted with high voltage gain. Hence, high step-up DC-DC converters are presented to use as a liaison between low-voltage PV arrays and high-voltage grid-connected sides, as shown in Figure 1 [3,4]. On the other hand, soft switching techniques can be used in the interface circuit to increase the converter efficiency, as well as to reduce the cost and dissipation of the system. Amongst the fundamental techniques for soft switching, one can name zero current switching (ZCS) and zero voltage switching (ZVS) [5]. Undoubtedly, numerous high step-up DC–DC converters achieved with various techniques are presented in the literature. Using transformers [6], stacked converters [7], switched capacitors [8], switched inductors [9], coupled inductors [10], input-parallel-output-series connections [11], and cascaded structures [12] is a well known techniques for achieving high voltage gain. Most of the mentioned techniques have a complex structure with a high number of elements [13]. In addition, they usually suffer from high voltage stress across semiconductor devices. Three-level DC–DC converters (TLDC) have extensively decreased the semiconductor voltage stress, down to the half of the output voltage. As a result, TLDCs are very attractive to use in high output voltage applications. A high step-up soft switched TLDC with an active clamp has been presented in [14]. Though the voltage stress had been lowered, the use of four power switches is explicitly associated with a more complex control circuit. A high step-up TLDC has been introduced in [15], which has utilised a voltage doubler circuit and coupled inductor in its structure. The converter only uses two switches in its topology. However, the hard switching was associated with lower efficiency, as expected. In [16], a hybrid high step-up TLDC for PV applications has been introduced. The topology is derived from a diode-clamped three-level inverter. Moreover, it uses only one inductor in its structure. Besides, a high step-up TLDC neutral-point-clamped has been presented in [17]. Unfortunately, both presented converters in [16,17] have complex structures due to the use of four switches. High step-up TLDC with active clamp is presented in [18]. The converter efficiency is high due to the soft switching operation. The converter has a complex structure. A high number of passive elements, such as coupled inductors, switched capacitors, clamp capacitors, and output capacitors, are used in the converter. A double-input three-level topology is proposed in [19]. The structure consists of buck-boost half-bridge modules, which can feed the loads when one of the input sources have been failed. The converter uses an active clamp to create soft switching, which leads to high efficiency. Moreover, a cascaded arrangement is used to decrease the voltage stress across the power switches. A dual-output three-level quadratic boost topology is proposed in [20]. Quadratic static gain is achieved with a low number of elements. The input and output have connection points, while their polarity is opposite. The dual-output voltages are balanced by using only two power devices. [21] proposes a three-level power converter, where the higher number of levels means the higher voltage gain ratio. A high step-up feature is achieved by using a three-winding coupled inductor in its structure. All switches are turned on under ZCS condition and the diodes are turned off naturally. In this way, the converter does not suffer from the reverse recovery problem, and its efficiency increases significantly. By using the advantages of interleaved and three-level structures, a boost converter has been proposed in [22], where the inputs were connected in parallel, and the outputs were put in series. The converter can operate with an extensive input voltage range properly. High step-up capability is achieved by applying two capacitors at the output side. Low input current ripple and low voltage stress across semiconductor devices (V_O/2) are the main advantages of the proposed converter. A single-switch boost converter is proposed in [23], which uses diode–capacitor modules in its structure. The converter achieves high voltage gain with a low-duty cycle. Low voltage stress across active components (V_O/n) and simple structure are the main advantages of the proposed converter. A boost three-level converter is proposed in [24]. It uses a diode rectification quasi-Z source structure in the topology. The converter has common ground between the input and the load, low voltage stress across semiconductor devices, and wide voltage gain. Quasi Z-source is used to clamp the flying-capacitor voltage to V_O/2. ZVS condition is achieved for synchronous rectification switch, which leads to high efficiency. A non-isolated converter with high voltage gain is proposed in [25]. High step-up operation is obtained by using switched capacitor and a switched inductor. The proposed DC–DC converter has high safety conditions due to the use of common ground between the input and the load. Moreover, the voltage stress on the semiconductors is lowered, i.e., equivalent to half of the output (V_O/2).

This paper deals with introducing a high step-up TLDC with a symmetric configuration. The converter has high voltage gain due to the use of two high step-up cells and two resonant paths in its structure. The energy stored in the cells transfers to the output when the switches are turned off. Moreover, the energy stored in the resonant elements, the input filter, the input source, and high step-up cells is transferred to the output. The above two factors increase the voltage gain as much as possible. Input filter inductors L₁ and L₂ cause the converter has a low input ripple current. The voltage stress across all switches is equal to half of the output voltage. In addition, the voltage stress across all diodes is also less than or equal to V_O/2. This characteristic leads the converter to be used in many high voltage, high power applications. The resonant cells in the proposed converter are positioned in such a way that the peak current of the resonant inductors does not pass through the switch. As a result, the switches have low current stress. A symmetric structure leads to simplify the converter design and reduces its complexity. The proposed converter uses simple PWM to trigger the switches. Only two switches related to TLDC are used in the converter. The gating signals of the switches have a phase difference of 180 degrees with respect to each other. As a result, the converter does not have any auxiliary switch. Hence, the proposed converter has a simple structure and control circuit. All semiconductor devices are turned on/off under ZCS condition. Thus, the switching losses are decreased, and the total efficiency is increased. The converter does not have any coupled inductor to increase the voltage gain. High step-up operation is based on the proper power transfer to the output.

The following sections are ordered as follows. Circuit structure and its characteristics are described in Section 2. Consideration of operating modes is analyzed in Section 3. The equations, obtained values, and types of components are explained in Section 4. Section 5 presents the simulation and experimental results of the prototype. Ultimately, Section 6 concludes the findings.

2. Circuit Structure and Its Characteristics

The proposed converter is shown in Figure 2. Inductors L₁ and L₂ act as the input filter inductors. There are two voltage step-up cells with linear operation that are located symmetrically. These cells include: inductors L₃ and L₄, capacitors C₁ and C₂, and diodes D₁ and D₂. Furthermore, the converter has two resonant cells which consist of inductors L₅, L₆ and capacitors C₃, C₄. The mentioned cells are also positioned symmetrically. Two series inductors L₇ and L₈ tune the current that flows through the linear and resonant cells. Output diodes D₃ and D₄ are used to transfer the power to the load. Capacitors C_O1 and C_O2 are usually used in conventional TLDCs. It should be noted that the voltage across each capacitor is equal to half of the output voltage. The theoretical waveforms are shown in Figure 3.

3. Consideration of Operating Modes

Interval 1: (t₀–t₁) [seeFigure 4a]: This mode starts when switch M₂ is turned on at t₀, while switch M₁ is also turned on. Since switch M₂ is connected in series with inductor L_8, which has zero current at t₀, the switch is turned on under ZCS condition. Hence, diode D₄ is also switched off at zero current. On the other hand, diode D₂ is switched on under ZCS condition to flow inductor current I_L8.

$$I_{D2}=I_{L4}+I_{L8}=I_{L2}+I_{L4}-I_{L6}$$

(1)

During this mode, capacitors C₁ and C₂ are charging. Moreover, capacitor C₃ charges while capacitor C₄ discharges.

$$I_{L6}=I_{CO2}+I_O$$

(2)

$$I_{CO1}=I_O+I_{L5}$$

(3)

$$I_{L7}=I_{M1}=I_{M2}+I_{CO1}+I_{CO2}$$

(4)

$$\frac{V_{in}}{2}=V_{L1}+V_{L7}$$

(5)

Since the proposed converter has a symmetric structure, V_L1 = −V_L2, V_C1 = V_C2, and L₃ = L₄.

$$t_1-t_0=\frac{V_{C1}}{L_3}\mathsf{\Delta }{I}_{L3}=\frac{V_{C2}}{L_4}\mathsf{\Delta }{I}_{L4}$$

(6)

During this mode, a resonance starts between capacitor C₃ and inductor L₅. In this condition, the capacitor voltage decreases, and the inductor current increases in a resonance manner.

$$V_{C3}(t)=V_{C3}(t_0)+V_{C3}(m)\sin {\omega }_{r1}\left(t-t_0\right)$$

(7)

$$i_{L5}\left(t\right)=i_{L5}\left(t_0\right)\cos {\omega }_{r1}\left(t-t_0\right)$$

(8)

Furthermore, another resonance occurs between capacitor C₄ and inductor L₆. The resonance increases V_C4 and decreases I_L6.

$$V_{C4}(t)=V_{C4}(t_0)+V_{C4}(m)\sin {\omega }_{r2}\left(t-t_0\right)$$

(9)

$$i_{L6}\left(t\right)=i_{L6}\left(t_0\right)\cos {\omega }_{r2}\left(t-t_0\right)$$

(10)

$${\omega }_{r1}={\omega }_{r2}=\frac{1}{\sqrt{C_3{L}_5}}=\frac{1}{\sqrt{C_4{L}_6}}$$

(11)

During this mode, diode D₁ is switched on to transfer the energy stored in the input filter inductors to series inductors (L₇ and L₈). At the end of this mode, inductor current I_L5 reaches I_in.

$$t_1-t_0=\frac{\arccos \left(\frac{I_{in}}{i_{L5}\left(t_0\right)}\right)}{{\omega }_{r1}}$$

(12)

$$V_{C3}\left(t_1\right)=V_{C3}\left(t_0\right)+V_{C3}\left(m\right)\sqrt{1-{\left(\frac{I_{in}}{i_{L5}\left(t_0\right)}\right)}^2}$$

(13)

$$V_{C4}\left(t_1\right)=V_{C4}\left(t_0\right)+V_{C4}\left(m\right)\sqrt{1-{\left(\frac{I_{in}}{i_{L5}\left(t_0\right)}\right)}^2}$$

(14)

$$i_{L6}\left(t_1\right)=\frac{i_{L6}\left(t_0\right)}{i_{L5}\left(t_0\right)}{I}_{in}$$

(15)

Besides, the following equations are obtained for mode 1.

$$\mathsf{\Delta }{I}_{L3}=\frac{L_3}{{\omega }_{r1}{V}_{C1}}\arccos \left(\frac{I_{in}}{i_{L5}\left(t_0\right)}\right)$$

(16)

$$\mathsf{\Delta }{I}_{L4}=\frac{L_4}{{\omega }_{r1}{V}_{C2}}\arccos \left(\frac{I_{in}}{i_{L5}\left(t_0\right)}\right)$$

(17)

$$i_{C3}\left(t\right)=i_{L5}\left(t\right)\to i_{L5}\left(t_0\right)=\frac{C_3{V}_{C3}\left(m\right)}{{\omega }_{r1}}$$

(18)

$$i_{C4}\left(t\right)=i_{L6}\left(t\right)\to i_{L6}\left(t_0\right)=\frac{C_4{V}_{C4}\left(m\right)}{{\omega }_{r2}}$$

(19)

In fact, mode 1 ends when switch M₁ is turned off at t₁.

Interval 2: (t₁–t₂) [seeFigure 4b]: This mode starts when switch M₁ is turned off at t₁ while switch M₂ is still turned on. When switch M₁ is turned off, diode D₃ is switched on and conducts the current that flows through inductor L₇. During this mode, diodes D₁ and D₂ are switched on as same as the former mode. A resonance starts between C₃, L₅, L₇, and C₁ in this mode. Hence, inductor current I_L5 and capacitor voltage V_C3 decrease in a resonance manner. At the end of this mode, the inductor current reaches zero, and the capacitor voltage will be equal to −V_o/2.

$$i_{L5}\left(t\right)=I_{in}\cos {\omega }_{r3}\left(t-t_1\right)$$

(20)

$$V_{C3}\left(t\right)=V_{C3}\left(t_1\right)-V_{C3}\left(m\right)\sin {\omega }_{r3}\left(t-t_1\right)$$

(21)

$$t=t_2\to i_{L5}\left(t_2\right)=0\to t_2-t_1=\frac{1}{4f_3}$$

(22)

$$t=t_2\to V_{C3}\left(t_1\right)-V_{C3}\left(m\right)=-\frac{V_O}{2}$$

(23)

$$V_{C3}\left(t_0\right)=V_{C3}\left(m\right)\left(1-\sqrt{1-{\left(\frac{I_{in}}{i_{L5}\left(t_0\right)}\right)}^2}\right)-\frac{V_O}{2}$$

(24)

The resonance between C₄ and L₆ continues as same as mode 1.

$${\omega }_{r3}=\frac{1}{\sqrt{C_{eq1}{L}_{eq1}}}$$

(25)

$$C_{eq1}=\frac{C_1{C}_3}{C_1+C_3}$$

(26)

$$L_{eq1}=L_5+L_7$$

(27)

Interval 3: (t₂–t₃) [seeFigure 4c]: This mode starts when inductor current I_L5 reaches zero at t₂. As a result, the inductor current will be reversed during this mode. The current that flows through inductor L₇ decreases and reaches zero at the end of this mode. In addition, diodes D₁ and D₃ are switched off under ZCS condition at t₃. During this mode, the resonance continues between C₄ and L₆. Finally, inductor current I_L6 reaches zero, and the voltage across capacitor C₄ reaches its peak value.

$$t=t_3\to i_{L6}\left(t_3\right)=0\to t_3-t_0=\frac{1}{4f_2}$$

(28)

$$t=t_3\to V_{C4}\left(t_3\right)=V_{C4}\left(t_0\right)+V_{C4}\left(m\right)$$

(29)

$$\begin{array}{l}{t}_3-t_2=\left(t_3-t_0\right)-\left(t_1-t_0\right)-\left(t_2-t_1\right)=\\ \frac{1}{4}\left(\frac{1}{f_2}-\frac{1}{f_3}\right)-\frac{\arccos \left(\frac{I_{in}}{i_{L5}\left(t_0\right)}\right)}{{\omega }_{r2}}\end{array}$$

(30)

$$\mathsf{\Delta }{I}_{L4}=\frac{V_{C2}}{L_4}\left(t_3-t_2\right)$$

(31)

$$\mathsf{\Delta }{I}_{L3}=\frac{V_{C1}}{L_3}\left(t_3-t_2\right)$$

(32)

During this mode, inductor current I_L8 increases.

Interval 4: (t₃–t₄) [seeFigure 4d]: This mode starts when I_L7 reaches zero and diodes D₁ and D₃ are switched off under ZCS condition. Besides, I_L3 also equals zero at t₃. Consequently, the energies stored in the input source, input filter inductors, capacitor C₁, and inductor L₅ are transferred to the output and capacitor C₃. During this mode, the resonance between capacitor C₃ and inductor L₅ stops. On the other hand, inductor current I_L6 will be reversed. As a result, a new resonance occurs among inductors L₆, L₈, and capacitor C₄ through diode D₂ and switch M₂. Hence, I_L6 increases based on the direction, which is shown in Figure 4d.

$$i_{L6}\left(t\right)=i_{L6}\left(m\right)\sin {\omega }_{r4}\left(t-t_3\right)$$

(33)

$$V_{C4}\left(t\right)=V_{C4}\left(t_0\right)+V_{C4}\left(m\right)\cos {\omega }_{r4}\left(t-t_3\right)$$

(34)

$${\omega }_{r4}=\frac{1}{\sqrt{C_4{L}_{eq2}}}$$

(35)

$$L_{eq2}=L_6+L_8$$

(36)

This mode ends when switch M₁ is turned on at t₄.

Interval 5: (t₄–t₅) [seeFigure 4e]: This mode starts when switch M₁ is turned on at t₄ while switch M₂ is still turned on. As same as the former mode, diodes D₃ and D₄ are reverse biased. When switch M₁ is turned on, the current that flows through inductor L₇ increases from zero. Thus, the switch is turned on under ZCS condition at t₄.

$$t_5-t_4=\frac{L_{eq3}}{V_{in}}\mathsf{\Delta }{I}_{Leq3}$$

(37)

$$L_{eq3}=L_7+L_8$$

(38)

During this mode, a resonance starts between capacitor C₃ and inductor L₅. In this condition, the inductor current is reduced, and the capacitor voltage rises.

$$V_{C3}(t)=V_{C3}(t_4)+V_{C3}(m)\sin {\omega }_{r1}\left(t-t_4\right)$$

(39)

$$i_{L5}\left(t\right)=i_{L5}\left(t_4\right)+\frac{V_{C3}\left(m\right)}{{\omega }_{r1}}\cos {\omega }_{r1}\left(t-t_4\right)$$

(40)

Similar to mode 4, the resonance between inductors L₆, L₈, and capacitor C₆ through diode D₂ and switch M₂ continues. On the other hand, the energy stored in inductor L₃ is transferred to capacitor C₁, while the energy stored in capacitor C₂ is transmitted to inductor L₄. This mode terminates when switch M₂ is turned off at t₅.

4. Small Signal Modelling

Small signal modeling is used to analyze the stability of a closed-loop system. This method is used by a state space average model. In this model, state space variables are capacitor voltage and inductor current. By considering the converter operating in CCM, state space equations can be calculated as follows.

$$\widehat{x}\left(t\right)=A_{j}x\left(t\right)+Bu\left(t\right)$$

(41)

$$y\left(t\right)=C_{j}x\left(t\right)+Du\left(t\right)$$

(42)

where, x(t) is the state space variable, $\widehat{x}\left(t\right)$ is derivative of x(t), and A, B, C and D, respectively, denote the matrices of the state, input, output and input–output. Besides, j is the number of operation modes in the proposed converter (j = 1, 2,…,5). Due to symmetric structure of the proposed converter, state variables are defined as follows.

$$x\left(t\right)={\left[\begin{array}{ccccccc}{i}_{L1}& i_{L3}& i_{L5}& i_{L7}& V_{C1}& V_{C3}& V_{CO1}\end{array}\right]}^{}$$

(43)

$$u\left(t\right)=\left[\begin{array}{cc}{V}_{in}& i_{in}\end{array}\right]\&y=\left[V_O\right]$$

(44)

Kirchhoff’s laws in Mode 1 leads to the following equations.

$$\frac{d{i}_{L1}}{dt}=\frac{V_{in}+V_{C1}-2V_{C3}-V_O}{2L_1}$$

(45)

$$\frac{d{i}_{L3}}{dt}=\frac{V_{C1}}{L_3}$$

(46)

$$\frac{d{i}_{L5}}{dt}=\frac{V_O}{2L_5}-\frac{V_{CO2}}{L_5}$$

(47)

$$\frac{d{i}_{L7}}{dt}=\frac{V_O+2V_{C3}-V_{C1}}{2L_7}$$

(48)

$$\frac{d{V}_{C1}}{dt}=\frac{i_{L5}-i_{L3}}{C_1}$$

(49)

$$\frac{d{V}_{C3}}{dt}=\frac{-i_{L5}}{C_3}$$

(50)

$$\frac{d{V}_{CO1}}{dt}=\frac{-V_O}{C_{O1}{R}_O}-\frac{i_{L5}}{C_{O1}}$$

(51)

Accordingly, Mode 2 yields the following equations.

$$\frac{d{i}_{L1}}{dt}=\frac{V_{in}+V_{C1}-2V_{C3}-V_O}{2L_1}$$

(52)

$$\frac{d{i}_{L3}}{dt}=\frac{V_{C1}}{L_3}$$

(53)

$$\frac{d{i}_{L5}}{dt}=\frac{V_O}{2L_5}-\frac{V_{CO2}}{L_5}$$

(54)

$$\frac{d{i}_{L7}}{dt}=\frac{2V_{C3}+V_O-V_{C1}-V_{CO1}}{2L_7}$$

(55)

$$\frac{d{V}_{C1}}{dt}=\frac{i_{L5}-i_{L3}}{C_1}$$

(56)

$$\frac{d{V}_{C3}}{dt}=\frac{-i_{L5}}{C_3}$$

(57)

$$\frac{d{V}_{CO1}}{dt}=\frac{i_{L7}-i_{L5}-\frac{V_O}{R_O}}{C_{O1}}$$

(58)

The following equations are associated with Mode 3.

$$\frac{d{i}_{L1}}{dt}=\frac{V_{in}+V_{C1}-2V_{C3}-V_O}{2L_1}$$

(59)

$$\frac{d{i}_{L3}}{dt}=\frac{V_{C1}}{L_3}$$

(60)

$$\frac{d{i}_{L5}}{dt}=\frac{V_{CO1}-V_O-V_{C1}}{2L_5}$$

(61)

$$\frac{d{i}_{L7}}{dt}=\frac{2V_{C3}+V_O-V_{C1}-V_{CO1}}{2L_7}$$

(62)

$$\frac{d{V}_{C1}}{dt}=\frac{-i_{L5}-i_{L3}}{C_1}$$

(63)

$$\frac{d{V}_{C3}}{dt}=\frac{+i_{L5}}{C_3}$$

(64)

$$\frac{d{V}_{CO1}}{dt}=\frac{i_{L7}+i_{L5}-\frac{V_O}{R_O}}{C_{O1}}$$

(65)

Applying Kirchhoff’s laws to Mode 4 yields:

$$\frac{d{i}_{L1}}{dt}=\frac{V_{in}-V_O+V_{C1}-2V_{C3}}{2L_1}$$

(66)

$$\frac{d{i}_{L3}}{dt}=0$$

(67)

$$\frac{d{i}_{L5}}{dt}=\frac{V_{in}-V_O-2V_{C3}}{L_5}$$

(68)

$$\frac{d{i}_{L7}}{dt}=0$$

(69)

$$\frac{d{V}_{C1}}{dt}=\frac{-i_{L1}}{C_1}$$

(70)

$$\frac{d{V}_{C3}}{dt}=\frac{i_{L1}}{C_3}$$

(71)

$$\frac{d{V}_{CO1}}{dt}=\frac{-i_{L5}-\frac{V_O}{R_O}}{C_{O1}}$$

(72)

Eventually, by inspection, the associated equations with Mode 5 are as follows.

$$\frac{d{i}_{L1}}{dt}=\frac{V_{in}+V_{C1}-2V_{C3}-V_O}{2L_1}$$

(73)

$$\frac{d{i}_{L3}}{dt}=\frac{V_{C1}}{L_3}$$

(74)

$$\frac{d{i}_{L5}}{dt}=\frac{V_O}{2L_5}-\frac{V_{CO2}}{L_5}$$

(75)

$$\frac{d{i}_{L7}}{dt}=\frac{V_O+2V_{C3}-V_{C1}}{2L_7}$$

(76)

$$\frac{d{V}_{C1}}{dt}=\frac{i_{L3}}{C_1}$$

(77)

$$\frac{d{V}_{C3}}{dt}=-\frac{i_{L5}}{C_3}$$

(78)

$$\frac{d{V}_{CO1}}{dt}=\frac{-i_{L5}-\frac{V_O}{R_O}}{C_{O1}}$$

(79)

A_ave, B_ave, and C_ave can be determined by state space averaging as follows.

$$A_{ave}=\left[\begin{array}{ccccccc}0& 0& 0& 0& \frac{1}{2L_1}& \frac{-1}{L_1}& 0\\ 0& 0& 0& 0& \frac{1}{L_3}& 0& 0\\ 0& 0& 0& 0& \frac{-D_3}{2L_5}& \frac{-2D_4}{L_5}& \frac{D_3-2\left(D_1+D_2+D_5\right)}{2L_5}\\ 0& 0& 0& 0& \frac{-\left(D_1+D_2+D_3+D_5\right)}{2L_7}& \frac{D_1+D_2+D_3+D_5}{L_7}& \frac{-\left(D_2+D_3\right)}{2L_7}\\ \frac{-D_4}{C_1}& \frac{D_5-\left(D_1+D_2+D_3\right)}{C_1}& \frac{D_1+D_2-D_3}{C_1}& 0& 0& 0& 0\\ \frac{D_4}{C_3}& 0& \frac{D_3-\left(D_1+D_2+D_5\right)}{C_3}& 0& 0& 0& 0\\ 0& 0& \frac{-1}{C_{O1}}& \frac{D_2+D_3}{C_{O1}}& 0& 0& 0\end{array}\right]$$

(80)

$$B_{ave}=\left[\begin{array}{cc}\frac{1}{2L_1}& 0\\ 0& 0\\ \frac{D_4}{L_5}& 0\\ 0& 0\\ 0& 0\\ 0& 0\\ 0& 0\end{array}\right]$$

(81)

$$C_{ave}=\left[\begin{array}{ccccccc}-\frac{1}{2L_1}& 0& \frac{D_1+D_2+D_5-D_3-2D_4}{2L_5}& \frac{D_1+D_2+D_3+D_5}{2L_7}& 0& 0& -\frac{1}{R{C}_{O1}}\end{array}\right]$$

(82)

The Laplace transform can be applied to the matrices above to derive the open-loop signal-to-output transfer functions.

$$G\left(S\right)=\frac{Y\left(S\right)}{U\left(S\right)}=C_{ave}{\left[SI-A_{ave}\right]}^{-1}+D$$

(83)

Open loop conversion function is obtained by substituting (80) and (82) into (83). Zeros and poles of the conversion function at the continuous time state space can be reached by using Gzpk command in MATLAB software. Obtained zeros and poles lie within the left-half of the s-plane. As a result, the open loop conversion function is stable.

5. Design Considerations

This part explains the design consideration of the proposed converter. The essential equations to design different parts are presented. Furthermore, the selection of elements based on the design guidelines and obtained values are described in detail. It should be noted that the proposed converter has a symmetric structure. In this condition, the elements in the symmetric parts have the same values.

5.1. Design of Input Filter Inductors L₁, L₂

The calculation of the input filter inductors in the proposed converter is similar to a conventional boost converter. Since L₁ and L₂ have equal inductances and they are connected in series with each other, the following equation is obtained.

$$L_1=L_2\ge \frac{V_{in}{D}_k}{4\mathsf{\Delta }{I}_{L1}{f}_{sw}}$$

(84)

In (84), D_k indicates the on-time duration of both switches M₁ and M₂. ΔI_L1 represents the half value of the current ripple that flows through input inductors. It should be designed in such a way that the proposed converter operates in CCM.

5.2. Design of Output Capacitors C_o1, C_o2

Since the proposed topology is a three-level converter that has a symmetric structure, C_O1 and C_O2 are equal. These capacitors act as an output filter.

$$C_O=\frac{C_{O1}\times C_{O2}}{C_{O1}+C_{O2}}$$

(85)

The output capacitor in the worst condition in CCM operation can be calculated as follows.

$$C_O=\frac{D_k}{2R\left(\frac{\mathsf{\Delta }{V}_O}{V_O}\right)f_{sw}}$$

(86)

$$C_O=\frac{C_{O1}}{2}$$

(87)

$$C_{O1}=C_{O2}=\frac{D_k}{4R\left(\frac{\mathsf{\Delta }{V}_O}{V_O}\right)f_{sw}}$$

(88)

In (86) and (88), R indicates the output load resistor and ΔV_O/V_O calculates the relative error in the output voltage.

5.3. Design of Series Inductors L₇, L₈

According to the converter operation in mode 5, the following equations are reached.

$$L_7=L_8=\frac{L_{eq3}}{2}=\frac{L_7+L_8}{2}$$

(89)

$$L_7=L_8=\frac{2V_{in}{D}_5{T}_{sw}}{2\mathsf{\Delta }{I}_{L7}}$$

(90)

Inductors L₇ and L₈ can be operated either in resonant or linear modes in the proposed converter. The maximum current that flows through the inductors is equal to the peak resonant current.

$$\mathsf{\Delta }{I}_{L7}=\mathsf{\Delta }{I}_{L8}=i_{L5}\left(m\right)=i_{L6}\left(m\right)=I_{in}$$

(91)

5.4. Design of Inductors L₃, L₄

Inductors L₃ and L₄ have equal inductances.

$$L_3=L_4=\frac{V_{C1}}{2\mathsf{\Delta }{I}_{L3}}\left(D_1+D_2\right)T_{sw}$$

(92)

$$\left(D_1+D_2\right)\frac{T_{sw}}{2}=t_2-t_0$$

(93)

In (92), ΔI_L3 = ΔI_L4. Moreover, their values are equal to half the peak-to-peak current that flows through L₃ and L₄.

5.5. Design of Capacitors C₁, C₂

Based on the capacitor charge balance, the following equations are computed.

$$\frac{1}{T_{sw}}{\displaystyle \underset{0}{\overset{T_{sw}}{\int }}{i}_{C1}}\left(t\right)dt=\langle i_{C1}\left(t\right)\rangle =0$$

(94)

$${\displaystyle \underset{0}{\overset{\left(D_1+D_2\right)\frac{T_{sw}}{2}}{\int }}{i}_{C1}}\left(t\right)dt=-{\displaystyle \underset{\left(D_1+D_2\right)\frac{T_{sw}}{2}}{\overset{\left(D_3+D_4+D_5\right)\frac{T_{sw}}{2}}{\int }}{i}_{C1}\left(t\right)}dt$$

(95)

$$D_1+D_2=\frac{1}{2}-\left(D_3+D_4+D_5\right)$$

(96)

Since the capacitors have linear operation, the following equation can be used.

$$C_1\mathsf{\Delta }{V}_{C1}=i_{C1}\left(t\right)\left(D_1+D_2\right)\frac{T_{sw}}{2}$$

(97)

Based on the converter operation during modes 1 and 2, the following formula is obtained.

$$i_{C1}\left(t\right)=I_{in}+i_{L7}\left(t\right)+i_{L3}\left(t\right)$$

(98)

Because i_L3 has a small value, it is ignored.

$$i_{C1}\left(t\right)=I_{in}+i_{L7}\left(m\right)=\frac{2P_O}{V_{in}}$$

(99)

$$C_1=C_2=\frac{2I_{in}}{\mathsf{\Delta }{V}_{C1}}\left(D_1+D_2\right)T_{sw}$$

(100)

In (100), ΔV_C1 is usually 10% of the rated output voltage.

5.6. Design of Switches M₁ and M₂

Voltage and current stresses should be calculated to select the appropriate type of switches. 50 kHz is selected as the switching frequency for the proposed converter.

$$V_{M1}\left(\max \right)=V_{M2}\left(\max \right)=\frac{V_O\left(\max \right)}{2}$$

(101)

$$I_{M1}\left(\max \right)=I_{M2}\left(\max \right)=I_{in}+i_{L5}\left(\max \right)=\frac{2P_O}{V_{in}}$$

(102)

5.7. Design of Output Diodes D₃, D₄

The voltage and current stresses of the diodes can be calculated as follows.

$$V_{D3}\left(\max \right)=V_{D4}\left(\max \right)=\frac{V_O\left(\max \right)}{2}$$

(103)

$$I_{D3}\left(\max \right)=I_{D4}\left(\max \right)=I_O+\frac{P_O}{V_{in}}$$

(104)

5.8. Design of Input Diodes D₁, D₂

Voltage and current stresses of the diodes can be considered as follows.

$$\begin{array}{l}{V}_{D1}\left(\max \right)=V_{D2}\left(\max \right)=\\ V_{C1}\left(\max \right)=V_{C2}\left(\max \right)\end{array}$$

(105)

$$I_{D1}\left(\max \right)=I_{D2}\left(\max \right)=\frac{P_O}{V_{in}}$$

(106)

5.9. Design of Resonant Elements C₃, C₄, L₅, L₆

The maximum current that flows through the resonant elements is considered equal to the input current.

$$I_{in}=\frac{P_O}{V_{in}}\to I_{L5}=I_{L6}=\frac{V_{C3}\left(m\right)}{Z_{r1}}$$

(107)

$$Z_{r1}=\sqrt{\frac{L_5}{C_3}}$$

(108)

By considering 20% as over-design, the following equation is computed.

$$Z_{r1}=\frac{V_{C3}\left(m\right)}{0.6I_{in}}$$

(109)

According to the converter operation, the resonant frequency should be at least twice the switching frequency.

$$T_{res}=2\pi \sqrt{C_3{L}_5}\ge \frac{T_{sw}}{2}$$

(110)

By using (109) and (110), the values of resonant inductors (L₅ = L₆) and resonant capacitors (C₃ = C₄) are obtained. It should be noted that the voltage gain of the proposed converter in CCM can be calculated as follows.

$$G_{CCM}=\frac{2}{1-2D}$$

(111)

6. Control of the Proposed DC-DC Converter

Figure 5 shows the general block diagram of the control circuit followed by the detailed diagram presented in Figure 6. The first two blocks, i.e., the output sampler and isolator, are realised through TL431. These are then followed by error amplifier and a PID compensator block. This is eventually directed to the SG3527 for PWM and then to the pulse delay circuit to adjust the produced signal.

At different loads, the output voltage should be stabilized by the control circuit. Hence, the influence of load variations on the output voltage is illustrated in Figure 7. As can be shown from the figure, the control circuit performs well during sudden load changes. Changing of the load is 25 to 100% and 50 to 100% of the rated load in Figure 7a,b, respectively.

7. Simulation and Experimental Results

To confirm the theoretical analysis of the proposed converter, simulation waveforms using Pspice software are shown in Figure 8. Moreover, a prototype of the proposed converter is constructed. According to the design consideration, the value for each element is presented in

Table 1. Main parameters of the converter.

Parameter	Value	Type	Number
Input Voltage	48 V	--	--
Output Voltage	700 V	--	--
Switching Frequency	50 kHz	--	--
Output Power	250 W	--	--
Inductors L1, L2, L3, L4	300 µH	--	4
Resonant Inductors L5, L6	20 µH	--	2
Series Inductors L7, L8	15 µH	--	2
Capacitors C1, C2	200 µF	Electrolytic	2
Resonant Capacitors C3, C4	1 µF	Electrolytic	2
Output Capacitors CO1, CO2	80 µF	Electrolytic	2
Power Switches M1, M2	--	IRFP242	2
Output Diodes D3, D4	--	MUR840	2
Power Diodes D1, D2	--	BYV27-200	2

. A prototype of the proposed converter is presented in Figure 9.

The derived voltage and current waveforms of the active power switches M₂ and M₁ are, respectively, shown in Figure 10 and Figure 11. According to the converter operation in mode 1, the switch is turned on under ZCS condition. This is performed because the switch is connected in series with inductor L₈, which has zero current at t₀. Due to the symmetric structure, the waveforms of switch M₁ are similar to M₂. The gating signals of the TLDC should have a phase difference of 180 degrees to each other.

The output capacitors, i.e., C_O1 and C_O2, operate as expected with the dc voltage waveforms shown in Figure 12. Due to the three-level structure, the voltage across each capacitor is equal to half of the output voltage. Figure 13 illustrates the input and output voltages.

Figure 14 presents the voltage and current waveforms of diode D₄, which is connected in series with inductor L₈. Based on the converter operation in mode 1, the diode is switched off under ZCS condition when switch M₂ is turned on. Due to the symmetric structure, the voltage and current waveforms of diode D₃ are similar to diode D₄.

Inductor currents I_L7 and I_L8 are shown in Figure 15. Moreover, inductor current I_L3 is depicted in Figure 16. As mentioned earlier, I_L3 increases and decreases linearly.

In the second half of the switching cycle, inductor current I_L4 is similar to I_L3. Capacitor voltage V_C1 is presented in Figure 17. Due to the symmetric structure, capacitor voltage V_C2 is similar to V_C1 in the second half of the switching cycle.

Voltage and current waveforms of diode D₂ are displayed in Figure 18. The diode is forward-bioased under ZCS at t₀ to flow I_L8.

Voltage waveforms of resonant capacitors C₃ and C₄ are shown in Figure 19. In addition, current waveforms of resonant inductors L₅ and L₆ are depicted in Figure 20.

The comparison between the proposed converter and other high step-up TLDCs in terms of voltage gain, voltage stress, soft switching, switching frequency, and the number of active elements is presented in

Table 2. A comprehensive comparison between the proposed converter and other TLDCs.

Ref.	Voltage Gain	Switch Voltage Stress	Diode Voltage Stress	Soft Switching	Efficiency	Switching Frequency	No. of Active Elements
							S	D	L	C
[18]	$\frac{1+n}{1-D}$	$\frac{V_O}{2\left(1+n\right)}$	$\frac{V_O}{2\left(1+n\right)}$	Yes	94%	100 kHz	3	4	3	8
[14]	Load Dependent	$\frac{V_{in}}{2\left(1-D\right)}$	$V_O$	Yes	95.7%	20 kHz	4	7	1	4
[15]	$\frac{2\left(1+nD\right)}{1-D}$	$\frac{V_O}{2}$	$\frac{V_O}{2}$	No	91.1%	25 kHz	2	4	2	2
[16]	$\frac{1}{1-\left(D_1+D_2\right)}$	$\frac{V_O}{2}$	$V_O$	No	90.3%	11.5 kHz	4	8	2	4
[17]	$\frac{1}{1-D}$	$\frac{V_O}{2}$	--	No	98%	50 kHz	4	0	1	2
[22]	$\frac{2}{1-D}$	$\frac{V_O}{2}$	$\frac{V_O}{2}$	No	94.14%	20 kHz	2	3	2	3
[23]	$\frac{2}{1-D}$	$\frac{V_O}{2}$	$\frac{V_O}{2}$	No	90.53%	20 kHz	1	3	1	3
[24]	$\frac{2}{3-4D}$	$\frac{V_O}{2}$	$\frac{V_O}{2}$	No	95.66%	10 kHz	3	4	2	4
[25]	$\frac{2\left(1-D\right)}{1-2D}$	$\le \frac{V_O}{2}$	$\le \frac{V_O}{2}$	No	93.1%	20 kHz	2	5	1	4
Proposed	$\frac{2}{1-2D}$	$\frac{V_O}{2}$	$\frac{V_O}{2}$	Yes	96.2%	50 kHz	2	4	8	6

.

Figure 21 show the efficiency variations with variations in the output load. Moreover, the operation of the converter under hard switching conditions is also plotted in this figure. It is obvious that the total efficiency of the proposed converter under soft-switching conditions is equal to 96.2% at full load.

The voltage gain obtained by (111) is shown in Figure 22 for different values of the duty cycle. It is obvious that the voltage gain of the proposed converter is sufficiently high that it can be used for PV applications. Moreover, the voltage gains of other selected converters are depicted in Figure 22 to compare with the proposed converter. The power loss distribution at 250 W for the proposed TLDC is plotted in Figure 23. To explain Figure 23, power loss calculation with details is shown in

Table 3. Power losses of high step-up three-level soft switching DC-DC converter.

Type of Loss	Formula	Proposed Converter
Switching Loss in Switches	$(\frac{1}{2}{V}_{in}.I_O.(t_{on}+t_{off})+V_{in}.(I_O+I_{rr}).t_{rr}).F_{SW}$	(0.5 × 48 × 0.36 × (100 + 100) × 10−9 + 48 × (0.36 + 0.1) × 100 × 10−9) × 50 × 103
Parasitic Capacitance Loss in Switches	$\frac{1}{2}.C_S.V_{DS}^2.F_{SW}$	0.5 × 20 × 10−6 × 442 × 50 × 103
Conduction Loss in Switches	$R_{ds}.{(F_{SW}.{\displaystyle {\int }_0^T{I}_S^2}.dt)}^{0.5}$	0.18 × (50 × 103 × 24.6 × 2 × 10−5)0.5
Conduction Loss in the Input Diodes (D1 and D2)	$I_{ave}.V_F$	4.64 × 0.5
Conduction Loss in the Output Diodes (D3 and D4)	$I_{ave}.V_F$	0.24 × 0.5
The Loss of Inductors	$\begin{array}{l}{P}_{Loss}=P_{Core}+P_{Copper}\\ P_{Core}=K_1.F_{SW}.B^y.V_e\\ P_{Copper}=P_{DCR}+P_{ACR}=\\ I_{rms1}^2.DCR+I_{rms2}^2.ACR\end{array}$	4.55
The Loss of Capacitors	$P_d=ESR+I_{ave}^2$	0.75
Total Losses	-	PLoss = 9.2 W

.

8. Conclusions

A Three-level DC-DC converter has been proposed, which benefits from a high voltage gain and a symmetric structure. The voltage gain ratio can reach up to 15 times, while no transformer or coupled inductor has been used. This high step-up capability is achieved by using two high step-up cells and two resonant paths in the converter topology. The converter has low input current ripple. Moreover, the voltage and current stresses of the switches are quite low. As the zero current switching has been achieved, the switching losses have been lowered, and the total efficiency of the proposed converter reaches 96.2% at full load. The proposed converter uses simple PWM to trigger only two power switches in its structure. A comprehensive comparison with the existing topologies, as well as simulations and experiments on a 250 W prototype, have confirmed the analysis for the operating conditions of 48 V as the input voltage and 700 V as the output voltage, with a switching frequency of 50 kHz