Modified Active-Clamped Current-Fed DC–DC Push–Pull Converter

Abstract

This work presents a modified version of the current-fed dc–dc push–pull converter associated with an active clamping circuit for mitigating voltage spikes on the primary-side switches. Unlike the traditional push–pull topology, saturation due to asymmetrical gating signals applied to the active switches is not likely to occur in the high-frequency transformer because the converter allows for connecting a blocking capacitor in series with the primary winding. In addition, the leakage inductance will not cause high voltage spikes on the primary-side semiconductors owing to the clamping capacitors. Since all active switches operate under the zero-voltage switching (ZVS) condition, one can obtain a high efficiency over a wide load range when comparing the structure with its hard-switching counterpart. Experimental results obtained from a laboratory prototype rated at 1 kW are presented and discussed to validate the theoretical claims.

1. Introduction

Isolated dc–dc converters are often employed in many practical applications that demand a wide voltage conversion range and galvanic isolation [1]. Among several topologies available in the literature for this purpose, the conventional dc–dc push–pull converter represents a simple solution that does not require isolated drivers, but the possible core saturation due to flux imbalance is of major concern [2]. Another important issue is that the voltage stresses on the active switches of the primary side are somewhat high, whereas the reverse recovery current through the secondary-side diodes causes high switching losses during turn-off in both voltage-fed and current-fed converters [3].

The aforementioned drawbacks motivated the development of distinct approaches in terms of topological modifications and modulation techniques. For instance, the authors in [4] combined the push–pull converter and the three-state switching cell (3SSC), which in turn was formerly introduced in [5]. A blocking capacitor is connected in series with one of the windings that constitute the autotransformer of the 3SSC to eliminate the dc bias and avoid saturation. In turn, the dual inductor current-fed push–pull converter described in [6] relies on a modified switching strategy so that the primary-side switches operate under soft-switching conditions during turn-on and turn-off.

The authors in [7] propose a modified topology that can increase efficiency significantly when compared with its hard-switching counterpart. However, a detailed loss breakdown shows that the overall conduction losses in the active switches increase significantly. The modified current-fed push–pull converter in [8] requires fewer components than other traditional topologies, but it is only possible to obtain zero-voltage switching (ZVS) in the primary-side switches under light load conditions.

Three-phase push–pull converters have also been proposed in the literature for high-power applications. The authors in [9] introduce a three-phase current-fed topology, whose efficiency drops significantly as the duty cycle increases. The six-switch voltage-fed structure proposed in [10] is only adequate for low input voltages because the voltage stresses on the primary-side semiconductors are somewhat high. The current-fed topology in [11] employs an active clamping circuit composed of three auxiliary switches and one capacitor to obtain a high efficiency over a wide load range. In turn, the three-phase push–pull converter in [12] relies on asymmetrical pulse width modulation (PWM), and flux imbalance issues are minimized owing to the high-impedance characteristic of the current-fed side.

Active clamping strategies are used in both single- and three-phase push–pull converters not only to mitigate the high voltage spikes on the semiconductors but also to minimize the switching losses while enabling the operation at higher frequencies. In this sense, the voltage-fed push–pull converter described in [13] is combined with an active clamping circuit composed of two auxiliary switches, five diodes, one inductor, and two capacitors, resulting in a high component count. The far simpler topology in [14] relies on a single additional switch connected between the input voltage source and the midpoint of two primary windings, but it requires a saturable inductor. One can also add an auxiliary switch and a clamping capacitor to the primary side and a voltage-doubler rectifier to the secondary side of the conventional push–pull converter as in [15].

The complementary active clamping strategy reported in [16] does not require additional auxiliary switches, but two bulky leakage inductors are used instead. The auxiliary circuit proposed in [17] employs one auxiliary switch instead of two, unlike most similar solutions, but one major drawback is the discontinuous input current. A similar topology that uses three active switches is introduced in [18], in which the primary-side switches and the secondary-side rectifier diodes operate under ZVS and zero-current switching (ZCS), respectively.

Impulse commutation strategies allow for minimizing the root mean square (RMS) currents through the active switches to reduce the resulting conduction losses and improve overall efficiency as demonstrated in [19]. Resonant techniques have also been proposed as a possible solution for alleviating the voltage spikes in push–pull converters. A partial-resonance-pulse-based LC resonant circuit is presented in [20] to obtain natural ZCS commutation in terms of a snubberless converter. The topology described in [21] relies on an active clamping circuit on the primary side and a voltage-doubler rectifier on the secondary side, resulting in a high efficiency over a wide load range, but at the cost of two additional external inductors. The series resonant converter in [22] can operate over a wide range of input voltage and output voltage while achieving ZVS in the primary-side switches and ZCS in the output diodes. The resonant dc–dc push-converter addressed in [23] can obtain high efficiency in medium-power applications, but unfortunately, it requires four switches on the primary side and an additional bidirectional switch on the secondary side, thus leading to a high component count and additional drive complexity.

The current-fed push–pull converter in [24] relies on replacing the diodes of the voltage-doubler circuit on the secondary side with switches, resulting in a naturally clamped structure capable of providing ZCS. The authors in [25] propose the connection of an external inductor in parallel with the secondary winding of the transformer to extend the ZVS range of the active switches while also using an active clamping circuit that requires a single auxiliary switch for suppressing voltage spikes during turn-off transients.

In this context, the main contribution of the present work is the introduction of a modified current-fed dc–dc push–pull converter associated with an active clamping circuit. Unlike most similar topologies described before, one can connect a blocking capacitor in series with the primary winding of the high-frequency transformer to avoid saturation without the need for complex active control schemes [26]. The active clamping circuit is responsible for suppressing the high voltage spikes on the primary-side switches, which operate under ZVS conditions, resulting in a high efficiency over a wide load range. Even though this structure relies on two transformers, it allows for deriving multiple independent and isolated outputs, resulting in a better distribution of the overall magnetic volume and losses.

Another important issue is that it is possible to extend it to a multiport three-phase configuration meant for applications involving bidirectional power flow. For instance, dc microgrids will inevitably require multiport isolated dc–dc converters to provide the interconnection of several sources and loads with distinct ratings, as well as galvanic isolation for safety reasons [27]. Modular multilevel converters (MMCs) will also benefit from the proposed topology because it can provide regulated dc voltages to supply the submodules in terms of a scalable approach [28]. Neutral-point-clamped (NPC) and cascaded multilevel inverters typically used in machine drives and uninterruptible power systems (UPSs) consist of other interesting applications for which the introduced architecture presents prominent advantages [29].

The remainder of this work is organized as follows. Section 2 describes the proposed topology in detail, from which an in-depth theoretical analysis is carried out. Section 3 compares the converter with other similar topologies reported in the literature. Section 4 discusses some important results obtained from a laboratory prototype. Section 5 presents the concluding remarks.

2. Proposed Topology

Let us consider a unidirectional version of the topology shown in Figure 1, which is the focus of the present study. It consists of the dc input voltage source V_i; the input filter inductor L_b; the main active switches S₁ and S₂; transformer HFT1, which comprises two primary windings T₁ and T₂ with the same number of turns, while one can add several secondary windings if necessary; transformer HFT2 represented in terms of the magnetizing inductance L_m; a voltage-doubler rectifier bridge composed of diodes D₁…D₄; the output filter capacitor C_o; and the load R_o. In turn, the active clamping circuit requires two auxiliary switches S₁′ and S₂′, as well as their respective body diodes; two switching capacitors C_s1 and C_s2; one clamping capacitor C_c; and one resonant inductor L_r. It is also necessary to connect a blocking capacitor C_b in series with the primary winding of HFT1 to avoid saturation due to the asymmetric drive signals of the active switches.

One can derive a multiport configuration with inherent design flexibility from Figure 1 by replacing the secondary-side diodes with active switches aiming to achieve bidirectional power flow. In addition, it is possible to couple multiple secondary windings to transformers HFT1 and HFT2 considering the polarities denoted by “*” and “●”, respectively, resulting in the three-phase architecture shown in Figure 2. This topology allows for achieving higher power levels, as well as improved distribution of losses and higher power density associated with the magnetics responsible for providing galvanic isolation and multiple regulated outputs. It is worth mentioning that one can replace the loads R_oa and R_ob with photovoltaic (PV) modules, fuel cells, wind turbines, or the conventional ac grid for deriving a multiport structure, for instance [30]. However, a thorough analysis of the arrangement depicted in Figure 2 is not part of the scope of this work.

The converter shown in Figure 1 results from a topological modification of the 3SSC, which is used in the conception of a family of non-isolated dc–dc converters in [5]. The forthcoming analysis considers that it operates in the steady-state condition and continuous conduction mode (CCM); all power stage elements are ideal; the drive signals of the main switches are overlapped, that is, the duty cycle is D > 0.5; and the switching frequency is constant.

2.1. Qualitative Analysis

One can analyze the operation of the proposed topology from Figure 3 and Figure 4. There are 14 operating stages, but only the first seven will be described here owing to the inherent circuit symmetry.

First stage (Figure 3a) [t₀, t₁]: Switches S₁ and S₂ are both on. The currents through the primary windings of HFT1 are equal to each other, and the resulting magnetic flux is null. The current through L_b increases linearly and is equally shared between the branches composed of the transformer windings and the main switches. The output filter capacitor is responsible for supplying the load.

Second stage (Figure 3b) [t₁, t₂]: Switch S₁ is turned off at t₁, whereas S₂ remains on. The energy stored in L_r is responsible for charging C_s1, thus allowing for S₁ to be turned off under ZVS conditions. The drain-source voltage across S₁ increases until it becomes equal to the voltage across C_c. In addition, there is no energy transfer to the load.

Third stage (Figure 3c) [t₂, t₃]: The auxiliary switch S₁′ is turned on at t₂. The resonant inductor current flows through the body diode of S₁′ to charge C_c, until it becomes null at t₃. In this stage, switch S₂ is responsible for ensuring the energy transfer to the load.

Fourth stage (Figure 3d) [t₃, t₄]: The current through L_r changes its direction at t₃ and starts flowing through S₁′, while S₂ remains on. Thus, the clamping capacitor supplies energy to the load. The auxiliary switch S₁′ is turned off at t₄, while the energy transfer to the load remains.

Fifth stage (Figure 3e) [t₄, t₅]: Resonance occurs between L_r and C_s1, causing the switching capacitor to be discharged as a consequence. It is noteworthy that one can only turn on S₁ when the voltage across C_s1 becomes null, which does occur at t₅.

Sixth stage (Figure 3f) [t₅, t₆]: The body diode of S₁ is forward biased at t₅, and switch S₁ is turned on under ZVS conditions. The diode current decreases until it becomes null at t₆. There is still energy transfer to the load.

Seventh stage (Figure 3g) [t₆, t₇]: The current starts flowing through S₁ instead of its respective body diode at t₆. It increases until becoming equal to half of the current through L_b, whereas the energy transfer to the load stops at t₇.

2.2. Quantitative Analysis

Analyzing the instantaneous voltage across L_b corresponding to v_L(t) in Figure 4, one can apply the volt-second balance principle to obtain the voltage gain as in (1). Figure 5 evidences the influence of the resonant inductance L_r and the turns ratio of HFT2 corresponding to a on the voltage gain G. It is reasonable to state that the gain decreases significantly as the duty cycle increases. Therefore, one should limit the maximum duty cycle in practice to mitigate this inconvenience.

$$G=\frac{V_o}{V_i}=\frac{a}{1-D}-\frac{a^2{I}_o{L}_r{f}_s}{V_i{\left(1-D\right)}^2}$$

(1)

where V_o is the average output voltage, I_o is the average output current, and f_s is the switching frequency.

One can obtain the theoretical value of the resonant inductance from (2). However, one must also incorporate the leakage inductance of transformer HFT2 represented by L_lkg into the physical design of the resonant inductor while using the value of L_ref in (3) for this purpose. Considering that L_lkg = 0.05⋅L_m is a conservative estimate, a more accurate design results from measuring L_lkg in the laboratory.

$$L_r=\frac{\left(1-D\right)\left[a{V}_i-\left(1-D\right)V_o\right]}{I_o{a}^2{f}_s},$$

(2)

$$L_{ref}=L_r-L_{lkg}.$$

(3)

According to [31], a large clamping capacitor may affect the converter dynamics. To avoid such an inconvenience, one can consider that the resonance period associated with L_r and C_c is equal to the switching period T_s = 1/f_s for simplicity, resulting in (4). The clamping voltage across C_c is also calculated from (5).

$$2\pi \sqrt{L_r{C}_c}=T_s.$$

(4)

$$V_{Cc}=\frac{V_i}{1-D}.$$

(5)

One can determine the input filter inductance from (6).

$$L_b=\frac{V_o\left(2D-1\right)\left(1-D\right)}{2a\Delta I_{Lb}{f}_s},$$

(6)

where ΔI_Lb is the peak-to-peak current ripple through L_b, whose average current is equal to the average input current I_i.

Transformer HFT1 must be designed while considering half of the output power P_o and a unity turns ratio [32]. Thus, its respective RMS current I_T1(RMS) and maximum voltage V_T1(max) are given by (7) and (8), respectively.

$$I_{T1\left(\mathrm{RMS}\right)}=\frac{I_i}{2},$$

(7)

$$V_{T1\left(\max \right)}=\frac{V_i}{2\left(1-D\right)}.$$

(8)

In turn, transformer HFT2 processes the whole output power. The RMS primary current I_T2p(RMS) and maximum primary voltage V_T2p(max) are calculated from (9) and (10), respectively. Similarly, one can obtain the RMS secondary current I_T2s(RMS) and maximum secondary voltage V_T2s(max) from (11) and (12), respectively.

$$I_{T2p\left(\mathrm{RMS}\right)}=I_i\sqrt{\frac{1-D}{2}},$$

(9)

$$V_{T2p\left(\max \right)}=\frac{V_o}{a}$$

(10)

$$I_{T2s\left(\mathrm{RMS}\right)}=\frac{I_i}{a}\sqrt{\frac{1-D}{2}},$$

(11)

$$V_{T2s\left(\max \right)}=V_o.$$

(12)

One can design the blocking capacitor connected in series with the primary winding of HFT2 according to (13).

$$C_b\ge \frac{I_i\left(1-D\right)}{2\Delta V_{Cb}{f}_s},$$

(13)

where ΔV_Cb is the peak-to-peak voltage ripple across C_b as defined by (14).

$$\Delta V_{Cb}=\frac{\xi V_o}{a},$$

(14)

where ξ is a constant associated with the primary winding of HFT2, which may be between 0.05 and 0.15 [32]. It is also worth mentioning that the RMS current through C_b is I_Cb(RMS) = I_T2p(RMS).

The output filter capacitor can be determined from (15), whereas its respective RMS current I_Co(RMS) is calculated from (16).

$$C_o\ge \frac{I_o\left(2D-1\right)}{2\Delta V_o{f}_s},$$

(15)

$$I_{Co\left(\mathrm{RMS}\right)}=I_o\sqrt{\frac{1-4D\left(1-D\right)}{1-D}},$$

(16)

where ΔV_o is the peak-to-peak voltage ripple across C_o.

The average and RMS currents through the active switches corresponding to I_S(avg) and I_S(RMS) are calculated from (17) and (18), respectively. One can also determine the maximum voltage V_S(max) from (19).

$$I_{S\left(\mathrm{avg}\right)}=\frac{I_i}{2},$$

(17)

$$I_{S\left(\mathrm{RMS}\right)}=I_i\sqrt{\frac{3}{4}-\frac{D}{2}},$$

(18)

$$V_{S\left(\max \right)}=V_{Cc}=\frac{V_i}{1-D}.$$

(19)

The average current I_D(avg), the RMS current I_D(RMS), and the maximum voltage V_S1(max) of the rectifier diodes are obtained from (20), (21), and (22), respectively.

$$I_{D\left(\mathrm{avg}\right)}=\frac{I_o}{2}$$

(20)

$$I_{D\left(\mathrm{RMS}\right)}=\frac{I_o}{2}\sqrt{\frac{1}{1-D}},$$

(21)

$$V_{D\left(\max \right)}=-V_o.$$

(22)

2.3. Soft-Switching Conditions

It is necessary to analyze the second and fifth stages represented in Figure 3b,f, respectively, to ensure the accurate design of the clamping circuit and achieve ZVS of the active switches. During the second stage, the switching capacitor C_s1 is charged with half of the input current, and the turn-off time is defined by (23).

$$t_{off}=\frac{2V_{Cc}{C}_{s1}}{I_i}.$$

(23)

In turn, the resonance between L_r and C_s1 occurs in the fifth stage, resulting in an equivalent circuit represented in terms of (24).

$$v_{Cs1}\left(t\right)=v_{Lr}\left(t\right)+\frac{V_o}{a}.$$

(24)

where v_Cs1(t) and v_Lr(t) are the instantaneous voltages across C_s1 and L_r, respectively.

Expanding (24) and solving the resulting differential equation, one can obtain i_Lr(t), that is, the instantaneous current through L_r from (25).

$$i_{Lr}\left(t\right)=I_{Lr0}\cos \left({\omega }_{0}t\right)+\left(V_{Cc}-\frac{V_o}{a}\right)\frac{1}{Z_0}\sin \left({\omega }_{0}t\right),$$

(25)

where I_Lr0 is the initial current through L_r, while ω₀ and Z₀ are the angular resonance frequency and the characteristic impedance calculated from (26) and (27), respectively.

$${\omega }_0=2\pi f_0=\frac{1}{\sqrt{L_r{C}_{s1}}},$$

(26)

$$Z_0=\sqrt{\frac{L_r}{C_{s1}}},$$

(27)

f₀ being the linear resonance frequency.

Substituting (25) in (24), one can obtain (28). In addition, the voltage across C_s1 is null at t = t_on, that is, the instant at which the active switch is turned on. Substituting this condition in (28) yields (29).

$$v_{Cs1}\left(t\right)=-I_{Lr0}{Z}_0\sin \left({\omega }_{0}t\right)+\left(V_{Cc}-\frac{V_o}{a}\right)\frac{1}{Z_0}\cos \left({\omega }_{0}t\right)+\frac{V_o}{a},$$

(28)

$$t_{on}=\frac{1}{\pi f_0}\arctan \left(\frac{\sqrt{a^2{I_{Lr0}}^2{Z_0}^2+{V_{Cc}}^2{a}^2-2a{V}_o{V}_{Cc}}+a{I}_{Lr0}{Z}_0}{2V_o-a{V}_{Cc}}\right).$$

(29)

Thus, one can determine I_Lr0 from the line equation that represents the instantaneous current through C_c, that is, i_Cc(t) during the interval [t₂, t₄] in Figure 4, resulting in (30).

$$I_{Lr0}=\left(V_{Cc}-\frac{V_o}{a}\right)\frac{\left(1-D\right)}{2L_r{f}_s}.$$

(30)

Substituting (30) in (29) and normalizing both the turn-on time and the switching frequency as ${\overline{t}}_{on}$ and ${\overline{f}}_s$ according to (31) and (32), respectively, one can write (33).

$${\overline{t}}_{on}=\frac{t_{on}}{T_s},$$

(31)

$${\overline{f}}_s=\frac{f_s}{f_0},$$

(32)

$${\overline{t}}_{on}=\frac{{\overline{f}}_s}{\pi }\arctan \left(\begin{array}{l}\frac{\sqrt{{V_{Cc}}^2-a^2-2a{V}_o{V}_{Cc}+\frac{2{\pi }^2{\left(1-D\right)}^2{\left(V_o-a{V}_{Cc}\right)}^2}{{\overline{f}}_s}}}{2V_o-a{V}_{Cc}}\\ +\frac{\pi \left(1-D\right)\left(a{V}_{Cc}-V_o\right)}{{\overline{f}}_s\left(2V_o-a{V}_{Cc}\right)}\end{array}\right),$$

(33)

Figure 6 shows the behavior of ${\overline{t}}_{on}$ as a function of ${\overline{f}}_s$ for several values of the duty cycle while considering the ratings adopted for V_Cc, V_o, and a in the design of an experimental prototype of the converter as described in Section 4. This plot can be used to design C_s1 and C_s2 considering that ${\overline{t}}_{on}$ corresponds to a small portion of T_s, e.g., 2%. Thus, one can obtain the corresponding value of ${\overline{f}}_s$ graphically from Figure 6 and calculate the switching capacitances using (34).

$$C_{s1}=C_{s2}=\frac{{{\overline{f}}_s}^2}{4{\pi }^2{L}_r{f}_s}.$$

(34)

The average and RMS currents through auxiliary switches (S₁′ and S₂′), namely I_S’(avg) and I_S’(RMS), can be calculated from the instantaneous current through C_c, resulting in (35) and (36). One can also calculate the maximum voltage across an auxiliary switch corresponding to V_S’(max) from (37).

$$I_{S^{\prime }\left(\mathrm{avg}\right)}=\frac{\left(1-D\right)I_i}{8},$$

(35)

$$I_{S^{\prime }\left(\mathrm{RMS}\right)}=\frac{I_i}{2}\sqrt{\frac{1-D}{3}},$$

(36)

$$V_{S^{\prime }\left(\max \right)}=V_{Cc}=\frac{V_i}{1-D}.$$

(37)

Another important issue lies in determining the load range for which the converter can operate under soft-switching conditions. For this purpose, let us consider that the secondary winding of the high-frequency transformer HFT2 in Figure 1 is open. The main switches S₁ and S₂, as well as the auxiliary switches S₁′ and S₂′, will operate under ZVS conditions, as ensured by the switching capacitors C_s1 and C_s2. The latter elements charge and discharge considering the reactive power flow involving the filter inductor L_b, the clamping capacitor C_c, and the magnetizing inductance L_m.

Figure 7 shows the main waveforms of the converter operating under no-load conditions in terms of the drive signals of the switches, current through L_b, the current through winding T₁ of transformer HFT1, the magnetizing current through the high-frequency transformer HFT2, the voltage and current on S₁, and the voltage and current on S₁’. Owing to the symmetrical operation of the legs formed by the active switches, the analysis focuses solely on the leg composed of switches S₁ and S₁’. Under no-load conditions, the average current through L_b is zero. However, its respective RMS value is not null and depends on the current ripple ΔI_Lb chosen in the design procedure. One can determine the current ripple from (38), which defines the behavior of the instantaneous voltage across the inductor corresponding to v_Lb(t).

$$v_{Lb}\left(t\right)=L_b\frac{d{i}_{Lb}\left(t\right)}{dt}.$$

(38)

Since v_Lb(t) = V_i, di_Lb(t) = ΔI_Lb, and t = (D − 0.5)T_s, one can write (38) as (39).

$$\Delta I_{Lb}=\frac{V_i\left(D-0.5\right)T_s}{L_b}.$$

(39)

The instantaneous currents through S₁ and S₁′ corresponding to i_S1(t) and i_S1′(t) can be calculated from (40) and (41), respectively.

$$i_{S1}\left(t\right)=\frac{i_{Lb}\left(t\right)}{2}-i_{Lm}\left(t\right),$$

(40)

$$i_{S{1}^{\prime }}\left(t\right)=i_{Lm}\left(t\right)-\frac{i_{Lb}\left(t\right)}{2},$$

(41)

where i_Lm(t) is the instantaneous current through the magnetizing current of the high-frequency transformer HFT2.

Neglecting the magnetizing current in (40) and (41), the charging and discharging currents of capacitors C_s1 and C_s2 at the turn-on instant t_on and turn-off instant t_off are approximated by (42).

$${\left.i_{S1}\left(t\right)\right|}_{t=t_{on},t=t_{off}}={\left.i_{S{1}^{\prime }}\left(t\right)\right|}_{t=t_{on},t=t_{off}}=\frac{\Delta I_{Lb}}{2}.$$

(42)

Therefore, the currents through the switches during the switching transitions depend on the inductor current ripple when the converter operates under the no-load condition. Therefore, the converter is capable of achieving soft switching over the entire load range.

2.4. Converter Efficiency

Using well-known equations available in didactic books like [33,34], one can calculate the losses in the power stage elements. For instance, the power loss in a diode can be calculated from (43), where the first and second terms of the sum are the conduction and switching losses, respectively.

$$P_D=\left[V_F{I}_{D\left(\mathrm{avg}\right)}+r_D{I}_{D\left(\mathrm{RMS}\right)}^2\right]+\left[\frac{I_{D\left(\mathrm{avg}\right)}{f}_s{t}_{rr}\left(V_{F\left(\max \right)}-V_F\right)}{2}+\left(V_{D\left(\max \right)}{Q}_{rr}{f}_s\right)\right],$$

(43)

where I_D(avg) and I_D(RMS) are the average and RMS currents through the diode, respectively; V_D(max) is the maximum voltage across the diode; V_F and V_F(max) are the rated and maximum values of the forward voltage drop, respectively; r_D is the body resistance; t_rr is the reverse recovery time; and Q_rr is the reverse recovery charge.

The power loss in a metal-oxide-semiconductor field-effect transistor (MOSFET) can be calculated from (44), where the first and second terms of the sum account for the conduction and switching losses, respectively.

$$P_S=\left[R_{ds\left(\mathrm{on}\right)}{I_{d\left(\mathrm{RMS}\right)}}^2\right]+\left[\frac{f_s{I}_{d\left(\mathrm{avg}\right)}{V}_{ds\left(\max \right)}\left(t_r+t_f\right)}{2}\right],$$

(44)

where R_ds(on) is the drain-source on-resistance; I_d(avg) and I_d(RMS) are the average and RMS drain currents, respectively; V_ds(max) is the maximum drain-source voltage; t_r and t_f are the rise time and fall time of the drain current, respectively.

The power loss in an inductor can be obtained from (45), where the first and second terms of the sum are the copper and core losses, respectively.

$$P_L=\left[\frac{{\rho }_{Cu}{l}_L{N}_L{I_{L\left(\mathrm{RMS}\right)}}^2}{n_L{S}_L}\right]+\left[\Delta B^{2.4}\left(K_h{f}_L+K_f{f_L}^2\right)V_e\right],$$

(45)

where ρ_Cu is the copper resistivity; l_L is the average length of a turn; N_L is the number of turns; n_L is the number of parallel-connected wires; S_L is the cross-sectional area of the conductor; I_L(RMS) is the RMS current through the winding; ΔB is the magnetic flux variation; K_h is the hysteresis loss coefficient; K_f is the eddy-current loss coefficient; f_L is the operating frequency; and V_e is the core volume.

The power loss in transformer HFT1 can be calculated from (46), where the first and second terms of the sum are the copper and core losses, respectively.

$$P_{HFT1}=\frac{2{\rho }_{Cu}{l}_T{N}_T{I_{T\left(\mathrm{RMS}\right)}}^2}{n_T{S}_T},$$

(46)

where l_T is the average length of a turn; N_T is the number of turns; n_T is the number of parallel-connected wires; S_T is the cross-sectional area of the conductor; and I_T(RMS) is the RMS current through the winding. It is worth mentioning that a similar equation can be used to calculate the losses in the high-frequency transformer HFT2. However, the number of turns, number of parallel-connected wires, cross-sectional area of the conductor used, and RMS current are not the same for the primary and secondary windings, unlike in HFT1, which has a unity turns ratio.

The power loss in a capacitor can be obtained from (47).

$$P_C=R_{SE}{I}_{C\left(\mathrm{RMS}\right)}^2,$$

(47)

where R_SE is the equivalent series resistance (ESR) of the capacitor and I_C(RMS) is the RMS current through the capacitor.

3. Comparison with Other Push–Pull Converters

Table 1. Comparison among active-clamped current-fed dc–dc push–pull converters.

Parameter	[8]	[18]	[21]	[23]	[24]	[25]	Proposed Converter
Ideal voltage gain	$\frac{a}{1-D}$	$\frac{a}{1-D}$	$\frac{2a}{1-D}$	$4a\gamma , \gamma \ge 1$ *	$\frac{a}{3}$	The gain varies as a function of fs and Po.	$\frac{a}{1-D}$
Primary-side/secondary-side switches	3/0	3/0	4/0	4/0	2/4	3/0	4/0
Isolated gate drivers	3	3	3	4	4	3	3
Diodes/capacitors/ inductors	2/3/1	4/2/1	2/5/1	4/4/2	0/2/2	2/3/1	4/5/1
Blocking capacitor	No	No	No	No	No	No	Yes
Total number of cores	2	2	2	3	3	2	4
Voltage stresses on the main switches	$\frac{V_i}{1-D}$	$\frac{V_i}{1-D}$	$\frac{V_i}{1-D}$	$2V_i$	$\frac{2V_o}{n}$	$\frac{V_i}{1-D}$	$\frac{V_i}{1-D}$
Voltage stresses on the auxiliary switches	$\frac{V_i}{2\left(1-D\right)}$	$\frac{V_i}{1-D}$	$\frac{V_i}{1-D}$	$\begin{array}{l}2V_i\\ V_o\end{array}$	Vo	$\frac{V_i}{2\left(1-D\right)}$	$\frac{V_i}{1-D}$
Voltage stresses on the diodes	Vo	Vo	Vo	Vo	—	Vo	Vo

* The authors did not define parameter γ in [23].

presents a qualitative comparison among current-fed push–pull converters that rely on active clamping circuits while considering the voltage gain, component count, and stresses on the semiconductors. The topology proposed in [8] relies on a low component count, but a loss breakdown at the rated power shows that the turn-off losses are somewhat high because the primary-side switches will achieve ZVS only at light load conditions. A similar structure operating at a very high switching frequency is described in [18], but the conduction losses in the active switches are mainly responsible for degrading the efficiency. The converter in [21] requires two auxiliary switches while achieving the highest rated power among all compared circuits. The authors claim that the magnetic flux imbalance is not of major concern because the converter uses two clamping capacitors. However, this condition was not assessed experimentally while considering asymmetric gating signals.

The authors in [23] present a push–pull converter that requires four primary-side switches and one bidirectional switch associated with the secondary winding of the transformer, resulting in a costly and complex arrangement. In turn, the topology in [24] replaces the diode bridge in the secondary with active switches, while using a proper modulation technique to mitigate voltage spikes on the semiconductors at turn-off. Even though it can achieve voltage clamping naturally, magnetic saturation is still likely to occur. The topology proposed in [25] also requires a single additional switch, resulting in a simple circuit, but a major drawback is that the voltage gain varies with both the switching frequency and the load even in CCM. Last but not least, it is noteworthy that the introduced active-clamped current-fed push–pull converter is the only one that allows for the connection of a blocking capacitor in series with the primary winding of the transformer to avoid saturation.

4. Experimental Results

Table 2. Specifications of the experimental prototype.

Parameter	Specification
Input voltage	Vi = 48 V
Output voltage	Vo = 400 V
Rated output power	Po = 1 kW
Switching frequency	fs = 25 kHz
Rated and maximum duty ratios	D = 0.64, Dmax = 0.75
Input current ripple	ΔILb = 18%·Ii
Output voltage ripple	ΔVo = 1%·Vo
Transformer turns ratio	a = 3
Inductor Lb	Lb = 72 μH, 13 turns, core NEE 55/28/21 by Thornton, 41 parallel-connected wires AWG26
Transformer HFT1	15:15 turns, core NEE 55/28/21 by Thornton, both windings composed of 23 parallel-connected wires AWG26
Transformer HFT2	19:57 turns, Llkg = 1.5 μH, core NEE 55/28/21 by Thornton, primary and secondary windings composed of 13 and 5 parallel-connected wires AWG26, respectively
Inductor Lr	Lref = 19.5 μH, 13 turns, core NEE 30/15/7 by Thornton, 12 parallel-connected wires AWG25
Blocking capacitor Cb	One polypropylene capacitor—20 μF/250 V
Output filter capacitor Co	Two parallel-connected electrolytic capacitors—470 μF/450 V
Switching capacitors Cs1, Cs2	Two polyester capacitors—6.8 nF/630 V
Clamping capacitor Cc	One polyester capacitor—2.2 μF/400 V
Main switches S1, S2	Two MOSFETs model IRFP4768PbF by Infineon Technologies
Auxiliary switches S1′, S2′	Two MOSFETs model IRFP460 by International Rectifier
Diodes D1…D4	Four hyperfast diodes model 30EPH06 by Vishay Semiconductor

summarizes the specifications of the experimental prototype represented in Figure 8. It is also worth mentioning that all waveforms were measured at the rated load condition, while the converter shown in Figure 1 was designed from the procedure described in Section 2.

Figure 9 presents the voltage and current waveforms of switch S₁, which can achieve ZVS during turn-on according to the detailed view in Figure 10. Similarly, the auxiliary switches operate under ZVS conditions during turn-on as demonstrated in Figure 11 and Figure 12. It is also noteworthy that there are no voltage spikes on the main and auxiliary switches during turn-on.

Figure 13 shows the waveforms of the clamping capacitor, which is charged and discharged by the current through the resonant inductor. Evidence presented in Figure 14 shows that the current through one of the primary windings of HFT1 is half of the input current, that is, around 10 A in this case. In turn, the maximum voltage across the rectifier diodes corresponds to the output voltage, that is, 400 V, according to Figure 15.

Figure 16 compares the efficiency curves of the current-fed push–pull converter employing the active clamping circuit and a passive dissipative snubber. The maximum efficiency is 93.8% and 94.2% at 330 W when using the dissipative snubber and the active clamping circuit, respectively. In turn, the efficiency is 91.8% at the rated power using the proposed solution, that is, 0.6% higher than that obtained with the dissipative snubber.

Figure 17 shows the loss breakdown at the rated load power, which was calculated from the equations presented in Section 2.4. Since the turn-on losses are negligible, the conduction losses are predominant in the switches. Owing to the limited availability of components in the laboratory, the adopted auxiliary switches are MOSFETs model IRFP460, which have a high drain-source on-resistance of 0.27 Ω. Therefore, it is reasonable to state that there is room for improving the converter efficiency by replacing S₁′ and S₂′ with components with improved characteristics. As for the magnetics, transformer HFT1 accounts for the major portion of losses.

5. Conclusions

This work has presented an active-clamped current-fed dc–dc push–pull converter, which can be arranged as a multiport configuration. Even though the topology employs two high-frequency transformers, it is possible to obtain multiple isolated outputs using both magnetic elements. Unlike most similar structures found in the literature, it allows for connecting a blocking capacitor in series with the primary winding to avoid saturation. Thus, it is not necessary to employ costly and complex control schemes for mitigating the magnetic flux imbalance caused by asymmetrical gating signals applied to the active switches.

The active clamping circuit enables all primary-side switches to operate under ZVS conditions during turn-on. In addition, there are no voltage spikes on the active switches during turn-off, and the resulting switching losses are negligible. Overall, it is reasonable to state that the proposed architecture presents prominent characteristics for applications that require multiport converters and bidirectional power flow.

The results have shown that the operation under soft-switching conditions will yield a higher efficiency over a wide load range when compared with a dissipative snubber, typically used in practical applications. The conduction losses in the active switches account for the major portion of losses, which means that there is room for improvement by choosing MOSFETs with a low drain-source on-resistance. In this sense, future work includes the possibility of not only designing a prototype with optimized components but also exploring a multiport configuration of the converter.