Sensitivity of Inner Spacer Thickness Variations for Sub-3-nm Node Silicon Nanosheet Field-Effect Transistors

Abstract

The inner spacer thickness (T_IS) variations in sub-3-nm, node 3-stacked, nanosheet field-effect transistors (NSFETs) were investigated using computer-aided design simulation technology. Inner spacer formation requires a high selectivity of SiGe to Si, which causes inevitable T_IS variation (ΔT_IS). The gate length (L_G) depends on the T_IS. Thus, the DC/AC performance is significantly affected by ΔT_IS. Because the effects of ΔT_IS on the performance depend on which inner spacer is varied, the sensitivities of the performance to the top, middle, and bottom (T, M, and B, respectively) ΔT_IS should be studied separately. In addition, the source/drain (S/D) recess process variation that forms the parasitic bottom transistor (tr_pbt) should be considered with ΔT_IS because the gate controllability over tr_pbt is significantly dependent on ΔT_IS,B. If the S/D recess depth (T_SD) variation cannot be completely eliminated, reducing ΔT_IS,B is crucial for suppressing the effects of tr_pbt. It is noteworthy that reducing ΔT_IS,B is the most important factor when the T_SD variation occurs, whereas reducing ΔT_IS,T and ΔT_IS,M is crucial in the absence of T_SD variation to minimize the DC performance variation. As the T_IS increases, the gate capacitance (C_gg) decreases owing to the reduction in both parasitic and intrinsic capacitance, but the sensitivity of C_gg to each ΔT_IS is almost the same. Therefore, the difference in performance sensitivity related to AC response is also strongly affected by the DC characteristics. In particular, since T_SD of 5 nm increases the off-state current (I_off) sensitivity to ΔT_IS,B by a factor of 22.5 in NFETs, the ΔT_IS,B below 1 nm is essential for further scaling and yield enhancement.

1. Introduction

Silicon fin-shaped field-effect transistors (FinFETs) have been continuously scaled down from 22-nm to 5-nm nodes using fins with high aspect ratios and design technology co-optimization [1,2,3,4,5,6]. However, increasing the fin aspect ratio is challenging owing to the process complexity, and FinFETs with narrow fins exhibit threshold-voltage variations and performance degradation induced by the quantum confinement effect [7,8,9,10]. By contrast, Silicon gate-all-around nanosheet field-effect transistors (NSFETs) have received considerable attention as promising devices that can replace FinFETs in sub-3-nm nodes, as they can overcome these limitations through stacked nanosheet (NS) channels [11]. Furthermore, NSFETs provide excellent electrostatics because the gate surrounds the NS channels and drives a larger current within the same footprint with a wider effective channel width than FinFETs [11,12].

The inner spacer is a distinctive structural feature of NSFETs that has not been employed in previous devices. Typically, selective etching of the SiGe sacrificial layers is performed to form the inner spacer. However, selective etching requires a high selectivity of SiGe to Si and lateral etching. Therefore, it can be vulnerable to process variations [13,14]. Furthermore, because the inner spacer determines the gate length (L_G), these variations result in NSFETs with unintended L_G changes and cause unoptimized leakage and DC/AC performance [11,15]. Therefore, precise control of the inner spacer thickness (T_IS) is crucial for performance optimization.

Previous studies related to the inner spacer have focused on the electrical properties of NSFETs, assuming the same shape and thickness from the top inner spacer to the bottom inner spacer [11,15]. However, in the actual process, the T_IS variation (ΔT_IS) may not occur uniformly [11,16]. In addition, for three-stacked NSFETs, the top and middle inner spacers adjoin two adjacent NS channels, while the bottom inner spacer adjoins only one NS channel and a punch-through stopper (PTS) region. Thus, the thickness variations of the top/middle/bottom (T/M/B) inner spacers have different effects on the device behavior; i.e., the T/M/B ΔT_IS (ΔT_IS,T/ΔT_IS,M/ΔT_IS,B) have different effects on the performance. Therefore, the performance sensitivities must be studied separately. Additionally, the over-etched S/D recess is a crucial factor determining the effects of the parasitic bottom transistor (tr_pbt) on the DC performance [17]. The effects of tr_pbt on performance become more pronounced as L_G decreases, which is a potential threat for further scaling [17,18]. However, there have been no studies on the effects of the S/D recess depth (T_SD) along with T/M/B ΔT_IS on the device behavior. In this study, for the first time, we comprehensively analyzed the sensitivity of the DC/AC characteristics to each ΔT_IS considering the T_SD, and the off-state characteristics were analyzed in detail using fully calibrated computer-aided design (TCAD) simulation technology [19].

2. Device Structure and Simulation Methodology

The sub-3-nm node NSFETs investigated in this study were simulated using Sentaurus TCAD tools. The following physical models were considered in the TCAD simulation:

• The drift–diffusion model was considered using Poisson’s equations and the continuity equations to determine the electrostatic potential and carrier transport.
• The density gradient model was considered for the quantum confinement effect in the drift-diffusion model [20,21].
• The Slotboom bandgap narrowing model was considered for doping-dependent bandgap narrowing in Si and SiGe [22,23].
• A low-field ballistic mobility model was considered for quasi-ballistic transport [24].
• Mobility degradation at the interfaces was considered for remote phonon scattering and remote Coulomb scattering [25].
• The inversion and accumulation layer mobility models were considered for Coulomb impurity, phonon scattering, and surface roughness scattering [26].
• A high-field saturation model was considered for carrier velocity saturation under a strong electric field [27].
• The deformation potential model was considered for the strain-induced density of states, effective mass of carriers, and energy-band shift [28].
• The Auger and Shockley–Read–Hall (SRH) recombination models were used.

Figure 1a shows schematics of the sub-3-nm node 3-stacked NSFETs. Among the T/M/B ΔT_IS, we varied only one of the T/M/B T_IS, with the others fixed at 5 nm, to investigate the effects of the T/M/B ΔT_IS on the DC/AC characteristics separately. Here, the thicknesses of the T/M/B inner spacers were defined as T_IS,T, T_IS,M, and T_IS,B, respectively. In addition, T_SD of 0 and 5 nm were used to consider the effects of T_SD on the performance along with those of ΔT_IS [14]. Therefore, a comprehensive analysis of ΔT_IS considering the T_SD effect was performed.

The T_IS without variation (T_IS,ref) was set as 5 nm, and only one of the three T_IS was varied from 3 to 7 nm (Figure 1b). In this study, ΔT_IS was defined as T_IS − T_IS,ref, and the L_G of each channel depended on ΔT_IS (L_G = 22 − 2 × (T_IS,ref + ΔT_IS)). Si_0.98C_0.02 (Si_0.5Ge_0.5) S/D doped with phosphorus (boron) at 4 × 10²⁰ cm⁻³ was used for the NFETs (PFETs). The contact resistance of the S/D was set as 1 nΩ·cm². The PTS layer was doped at 3 × 10¹⁸ cm⁻³, and the drain voltage (V_ds) was fixed at |0.7| V. The geometric parameters are presented in

Table 1. Geometric parameters for sub-3-nm node NSFETs.

Fixed Parameters	Values
Contact poly pitch (CPP)	42 nm
Fin pitch (FP)	60 nm
Gate length (LG)	12 nm
Spacing thickness (TSP)	10 nm
NS thickness (TCH)	5 nm
NS width (WNS)	25 nm
Interfacial layer thickness (TIL)	0.6 nm
HfO2 thickness (THK)	1.1 nm
TIS without variation (TIS,ref)	5 nm
S/D doping concentration (NSD)	4 × 1020 cm−3
PTS doping concentration (NPTS)	3 × 1018 cm−3
Variable parameters	Values
Excess S/D recess depth (TSD)	0 or 5 nm
Inner spacer thickness (TIS)	3–7 nm

. The NSFETs were calibrated to TSMC’s 5-nm node FinFETs [5], and the same physical parameters were used, as shown in our previous studies [29]. The drain current was fitted by adjusting the doping profile, ballistic coefficient, and saturation velocity. The doping profile was changed to fit the subthreshold swing and DIBL since the doping profile is deeply concerned with the device behaviors in the subthreshold region. The ballistic coefficient was tuned to fit the drain current in the linear region, and the saturation velocity was set to fit the drain current in the saturation region. We extracted the on-state current (I_on) and gate capacitance (C_gg) at |V_gs| = 0.7 V and |V_ds| = 0.7 V. Moreover, the off-state current (I_off) and parasitic capacitance (C_para) were extracted at |V_gs| = 0 V and |V_ds| = 0.7 V.

3. Results and Discussion

Figure 2 shows the transfer curves of NSFETs with different T_IS,B for T_SD = 0 and 5 nm. No significant dependence of the DC performance on ΔT_IS,B was observed at T_SD = 0 (Figure 2a). By contrast, at T_SD = 5 nm, the I_off increased significantly as T_IS,B increased (Figure 2b). The T_SD typically impacts the I_off of tr_pbt [17], where T_IS,B determines the L_G of tr_pbt. Because the L_G of tr_pbt affects the gate controllability over the PTS region, an increase in ΔT_IS,B significantly degrades the DC performance. As an increase in T_SD degrades the gate controllability of tr_pbt, T_IS,B is a critical factor determining the parasitic punch-through current (I_pt) in the PTS region. Therefore, the subthreshold swing and DIBL are significantly degraded, as shown in the inset of Figure 2 and

Table 2. DIBL of NSFETs according to the T_IS,B and T_SD.

Type	TIS,B [nm]	DIBL [mV/V]
		TSD = 0 nm	TSD = 5 nm
NFETs	3	60	67
	5	62	72
	7	67	81
PFETs	3	51	54
	5	53	57
	7	58	61

.

The I_off sensitivities to the T/M/B ΔT_IS (S_Ioff,T/S_Ioff,M/S_Ioff,B) are compared in Figure 3. We defined S_Ioff as the slope of I_off−ΔT_IS, which indicates how sensitively I_off varies with respect to ΔT_IS. For the NFETs with T_SD = 0 nm, the S_Ioff,T (0.208) and S_Ioff,M (0.228) slightly exceeded the S_Ioff,B (0.104 nA/nm), and similar S_Ioff tendencies were observed for the PFETs. The T_SD variation not only increased I_off, but also significantly increased S_Ioff,B for both the NFETs and the PFETs. The S_Ioff,B for the NFETs is greater than that for the PFETs, which is mainly attributed to the S/D dopant diffusion into the PTS region. Phosphorus has a higher diffusivity than boron; therefore, more S/D dopant diffuses into the PTS region in NFETs than in PFETs [30]. Consequently, the NFETs are more sensitive to the ΔT_IS,B in terms of I_off. For the NFETs with T_SD = 5 nm, S_Ioff,T, S_Ioff,M, and S_Ioff,B were 0.195, 0.209, and 2.34 nA/nm, respectively. S_Ioff,T and S_Ioff,M were almost identical regardless of the T_SD, but S_Ioff,B increased by a factor of 22.5 when the T_SD increased from 0 to 5 nm. This indicated that the S/D recess process variation slightly affects S_Ioff,T and S_Ioff,M but significantly affects S_Ioff,B. Thus, if the T_SD variation is not perfectly eliminated, ΔT_IS,B should be controlled below 1 nm, because devices with greater than 10 times in I_off are not suitable for the intended system-on-chip applications.

The differences in the S_Ioff shown in Figure 3 can be explained using the I_off-density profiles (Figure 4). In NSFETs with T_SD = 0 nm, most carriers existed in the NS channels, and a few were in the PTS region owing to the heavily doped PTS. Furthermore, ΔT_IS-induced I_off density variations mainly arose in the NS channels next to the inner spacer with variations in the thickness. Thus, the top and middle inner spacers adjacent to the NS channels with high carrier concentrations exhibited larger changes in the I_off density than the bottom inner spacer. Therefore, S_Ioff,T and S_Ioff,M are higher than S_Ioff,B for the NSFETs with T_SD = 0 nm. By contrast, S_Ioff,B was the highest when the T_SD was 5 nm. Figure 4b shows the I_off density profiles for NFETs with different T_IS,B in the case of T_SD = 5 nm. As T_IS,B increased, the off-state I_pt (I_pt,off) was not suppressed, resulting in a significant increase in I_off, as shown in Figure 2. The I_off density varied according to ΔT_IS,B in the bottom NS and PTS regions but varied to a significantly larger extent in the PTS region. Specifically, the T_SD variation significantly enhanced the effects of tr_pbt on I_off, and the change in I_pt,off was a dominant factor in the S_Ioff,B increment. This is because the PTS region was only controlled by the bottom gate. Therefore, the bottom gate could not effectively control the PTS region far from the bottom gate. As a result, worse short-channel effects (SCEs) were observed in the PTS region than in the NS channel.

Figure 5a shows the conduction band energy (E_c) diagrams of the source–PTS–drain in the NFETs, which were extracted under the off-state bias condition. As the T_SD increased from 0 to 5 nm, the significant reduction in the energy barrier height (Φ_b) from 478 to 402 mV was caused by the larger amount of S/D dopant diffusion into the PTS region at a T_SD of 5 nm. In NFETs with T_SD = 0 nm, the Φ_b of the PTS region was sufficiently high to control I_pt,off regardless of ΔT_IS,B (Figure 5b). Therefore, I_off can be effectively controlled even with ΔT_IS,B. However, if Φ_b is not sufficiently high, the additional Φ_b reduction due to ΔT_IS,B can be a critical factor in inducing I_pt,off. An additional Φ_b reduction was observed when T_IS,B increased, and the change in Φ_b by ΔT_IS,B significantly contributed to the I_pt,off variation (Figure 3 and Figure 5c). Therefore, the bottom L_G of tr_pbt, which is related to T_IS,B, is important for suppressing SCEs in the PTS region. According to these results, S_Ioff,B is significantly affected by T_SD. Thus, minimizing ΔT_IS,B is more crucial when an over-etched S/D recess occurs.

Figure 6 shows the relationship between the on-state current (I_on) and ΔT_IS, and the slope indicates the I_on sensitivity (S_Ion). For the NFETs, the S_Ion,T and S_Ion,M are slightly higher than the S_Ion,B regardless of the T_SD. By contrast, for the PFETs, the S_Ion,B varied significantly with respect to the T_SD, leading to an increase in S_Ion,B by a factor of 1.9. Thus, an increase in ΔT_IS,B can cause severe I_on variations when the T_SD is not precisely controlled. The reason for the differences in the S_Ion is explained in Figure 7.

The R_sd sensitivity (S_Rsd) and on-state I_pt (I_pt,on)-density variations to the ΔT_IS account for the differences in T/M/B S_Ion (Figure 7). R_sd was extracted using Y-function techniques, as described in [31]. Two main factors determine S_Ion: R_sd and inversion charges in the PTS region. Additionally, the major factors affecting S_Ion depend on the T_SD. For both the NFETs and PFETs with T_SD = 0 nm, S_Ion was mainly affected by the change in R_sd, which consisted of the series S/D epi resistance (R_epi) and extension resistance (R_ext). R_epi did not change with respect to ΔT_IS, but R_ext did. Because S_Rsd varied proportionally to the number of NS channels adjacent to the inner spacer where ΔT_IS occurred (Figure 7a), S_Ion,T and S_Ion,M were greater than S_Ion,B. However, the inversion charges in the PTS region significantly affected S_Ion when T_SD was 5 nm. As the deep T_SD caused a substantial current to flow through tr_pbt, the I_on contribution of the PTS region was no longer small. The inversion charges in the PTS region should also be considered (Figure 7b). For the NFETs, the I_pt,on density in tr_pbt decreased slightly as T_IS,B increased, whereas the large decrease in I_pt,on was observed for the PFETs. This is because higher SCEs and V_th reductions were observed in the NFETs, as the large amounts of diffused S/D dopants reduced Φ_b (Figure 2b and Figure 5a). Therefore, in the NFETs, the V_th reduction of tr_pbt lowered the effects of the increase in R_sd, which was the dominant factor determining S_Ion,B. By contrast, in the PFETs, the V_th reduction of tr_pbt was small; thus, I_pt,on decreased significantly owing to the increase in the R_sd of tr_pbt. Consequently, S_Ion,B was the smallest for the NFETs, but for the PFETs, the T_SD variation caused I_on to be most sensitive to ΔT_IS,B.

Based on these results, we can provide two guidelines for controlling the DC performance variation, which depends on T_SD. In the case of T_SD = 0, precisely controlling T_IS,T and T_IS,M rather than T_IS,B is effective for minimizing the variations in I_off and I_on, as shown in Figure 3 and Figure 6. However, considering the T_SD variation, it is necessary to focus on the bottom inner spacer, because a precisely controlled T_IS,B, can considerably reduce the performance variation. Otherwise, the effects of tr_pbt on the DC performance become large as T_IS,B increases, resulting in the worst case with the highest I_off and lowest I_on in PFETs, which significantly diminishes the performance advantages of NSFETs.

The gate capacitance (C_gg) with respect to ΔT_IS for NSFETs (T_SD = 0) is shown in Figure 8, and C_gg is decomposed into the intrinsic capacitance (C_int) and parasitic capacitance (C_para). C_para was extracted under the off-state bias, and C_int was calculated by subtracting C_para from C_gg under the on-state bias. As shown in Figure 8a, the differences in the C_gg sensitivity to T/M/B ΔT_IS (S_Cgg) were small. However, the changes in C_int and C_para for each ΔT_IS did not have the same sensitivity. C_para, which was determined by the fringing field between the gate and S/D, was affected by the T_IS. Therefore, the sensitivity of C_para to ΔT_IS was almost identical among the T/M/B ΔT_IS (Figure 8b). However, the sensitivity of C_int to ΔT_IS,B was lower than those of ΔT_IS,T and ΔT_IS,M (Figure 8c). Although the inversion charge variations caused by ΔT_IS,B mainly occurred in the bottom NS and PTS regions, the charge variations in the PTS region were smaller than those in the NS channels, leading to different AC sensitivities to the T/M/B ΔT_IS. However, because the differences in the C_int sensitivity to the T/M/B ΔT_IS were not large, it can be concluded that the overall performance sensitivity difference induced by each ΔT_IS has greater effects on DC (I_off, I_on) rather than the AC performance.

4. Conclusions

The sensitivities of the DC/AC performance to the T/M/B ΔT_IS in sub-3-nm node NSFETs were quantitatively investigated using a fully calibrated TCAD simulation. The DC performance sensitivities (I_off, I_on) to the T/M/B ΔT_IS differed. However, there were no significant differences in the AC sensitivities. One of the notable results was that ΔT_IS, which varied the performance the most, was different according to the T_SD variations. In NSFETs with T_SD = 0 nm, S_Ioff,B was lower than S_Ioff,T and S_Ioff,M because the effects of ΔT_IS,B were primarily observed in the bottom NS channel. However, tr_pbt was no longer negligible when the T_SD was 5 nm. Thus, if the T_SD variation is not controlled, NFETs (PFETs) have higher S_Ioff,B (S_Ion,B) because of the effects of tr_pbt. It can be concluded that the bottom inner spacer is the element with the most significant effect on the DC/AC performance. Hence, reducing ΔT_IS,B is important for yield enhancement.