Evaluation of V_TH and R_ON Drifts during Switch-Mode Operation in Packaged SiC MOSFETs

Abstract

In this paper, we investigate the evolution of threshold voltage (V_TH) and on-resistance (R_ON) drifts in the silicon carbide (SiC) power metal-oxide-semiconductor field-effect transistors (MOSFETs) during the switch-mode operation. A novel measurement setup for performing the required on-the-fly characterization is presented and the experimental results, obtained on commercially available TO-247 packaged SiC devices, are reported. Measurements were performed for 1000 s, during which negative V_TH shifts (i.e., V_TH decrease) and negative R_ON drifts (i.e., R_ON decrease) were observed. To better understand the origin of these parameter drifts and their possible correlation, measurements were performed for different (i) gate-driving voltage (V_GH) and (ii) off-state drain voltage (V_PH). We found that V_TH reduction leads to a current increase, thus yielding R_ON to decrease. This correlation was explained by the R_ON dependence on the overdrive voltage (V_GS–V_TH). We also found that gate-related effects dominate the parameter drifts at low V_PH with no observable recovery, due to the repeated switching of the gate signal required for the parameter monitoring. Conversely, the drain-induced instabilities caused by high V_PH are completely recoverable within 1000 s from the V_PH removal. These results show that the measurement setup is able to discern the gate/drain contributions, clarifying the origin of the observed V_TH and R_ON drifts.

1. Introduction

Silicon carbide (SiC) is a common technology option for replacing silicon (Si) in power-switching applications that require low switching and conduction losses [1]. Unfortunately, the degradation of key electrical parameters in SiC power devices under repetitive switching stress reduces both device performance and reliability well below specifications [2]. In this scenario, stability issues like threshold voltage (V_TH) and dynamic on-resistance (R_ON) drifts are often encountered [3], severely impacting device lifetime and performance. For instance, a positive R_ON drift (i.e., increase) affects the conduction losses within power-switching converters, yielding a considerable efficiency reduction. Similarly, a positive V_TH shift results in a lower current level for a given driving gate voltage (V_GS) [4,5], whereas negative V_TH variations could impede fully turning off the device, causing unwanted conduction at a large drain bias [6].

Generally, Bias Temperature Instability (BTI) experiments are employed to reveal the mechanisms underlying these issues in SiC technology [7,8,9]. However, BTI tests can only be used to investigate the effects related to gate bias, neglecting the effects related to the drain bias. To get a more complete picture of the detrimental effects produced by repetitive switching stress [2,10], it is necessary to evaluate the V_TH and R_ON evolution when the device is driven in realistic operating conditions, i.e., with both gate and drain potential repeatedly switched on and off. To this end, test circuits should be designed to mimic conventional switching conditions in terms of frequency, voltage, and current level. At the same time, these circuits should also extract the parameters of interest (e.g., V_TH and R_ON) without affecting device operation. Accordingly, a fast stress measurement approach is needed, in order to cope with switching frequencies in the kHz range [11] and also to limit the delay between the stress and readout [12,13,14] phases, thus avoiding ambiguous parameter drifts and/or wrong data interpretation. Nevertheless, achieving these goals is challenging for conventional parameter analyzers, especially when characterizing packaged devices with large parasitic capacitances [15]. The development of custom, ad-hoc systems is thus essential to investigate the stability and performance of commercially available state-of-the-art devices.

In this work, we present a novel measurement setup that allows the simultaneous monitoring of both V_TH and R_ON during the conventional switch-mode operation for packaged SiC metal-oxide-semiconductor field-effect transistors (MOSFETs). The measurement is carried out by means of double-pulsed on-the-fly (OTF) characterization, in which the Device Under Test (DUT) is repeatedly switched between a high voltage off-state condition and a low voltage on-state one in the kHz frequency range. To this end, soft-switching conditions are considered (i.e., turn ON and turn OFF transitions are performed at zero current). During OTF measurements, the device V_TH and R_ON are evaluated in order to monitor their drifts over time with a digital sampling oscilloscope (DSO). Since the parameter instabilities could manifest either after a few or several operating cycles [16], it is important to monitor the parameters of interest over several time decades to capture the whole dynamics. Accordingly, the DSO acquisition was triggered at logarithmically spaced time instants in order to avoid memory saturation and loss of accuracy [17]. By applying the proposed measurement method on commercially available devices (i.e., TO–247 vertical SiC MOSFETs), it was possible to test the effectiveness of the setup and to provide a qualitative interpretation of the physical mechanisms leading to the observed V_TH and R_ON drifts. Particularly, negative drifts (i.e., decrease) were observed for both V_TH and R_ON, that can be ascribed to the presence of traps at the SiC/SiO₂ interface [18,19,20].

The paper is organized as follows. Section 2 describes the custom measurement setup and the adopted design strategies to improve the measurement accuracy. In Section 3, the data collected for tested SiC MOSFETs are presented, highlighting the drift effects on the devices’ trans-characteristics. Particularly, we investigated the effect of the bias conditions on the observed drifts, emphasizing the effect of the gate-driving voltage applied in on-state (V_GH) and of the drain voltage applied during off-state stress (V_PH). Finally, Section 4 draws the conclusions of the paper.

2. Measurement Setup

The simplified schematic of the custom measurement setup is shown in Figure 1. The system was developed starting from the design first presented in [17], with several important modifications as discussed in the following.

The gate driver circuit is responsible for repeatedly switching the DUT ON and OFF and is devoted to the generation of the ramp signal required for the extraction of the V_TH and R_ON values. For performing on-wafer measurements, the usage of a simple waveform generator would be sufficient, thanks to the small parasitic capacitances of the DUTs. However, this solution is not viable for characterizing packaged devices due to the gate-to-source capacitances (C_GS) in the order of few nF [15]. For this reason, a custom gate driver circuit is required to prevent any distortion of the ramp signal, thus ensuring a fast and accurate V_TH extraction [14].

In off-state conditions, the DUT is stressed with a large drain voltage (V_PH), provided by a DC power supply, inducing both lateral and vertical trapping [21], while the on-state drain bias voltage (V_PL) is provided through an isolated DC/DC converter. The drain voltage is pulsed by means of a couple of NMOS (M_PH and M_PL in Figure 1) arranged in a push–pull configuration, with an additional NMOS device (M_PLL) inserted for reducing the series resistance during DUT turn-on. A 0.1 Ω resistor (R_SENSE) is connected to the DUT’s source terminal in order to extract the drain current (I_DS) while a clamping circuit (M₁, R₁, D₁) is connected to the drain terminal of the DUT for improving the measurement accuracy at low voltages. An additional NMOS (M_DSC) was placed between the DUT’s drain terminal and GND in order to force the drain voltage to 0 V. This condition is required for monitoring the parameter recovery after the V_PH removal. The whole setup is controlled by a MicroController Unit (MCU) used for triggering the DSO acquisition with logarithmically spaced time steps [17] and for generating the necessary synchronization signals. Figure 2 illustrates a typical bias scheme for the circuit. Figure 3 shows the time sequence of the trigger signal used to activate the DSO acquisition.

The DSO used in this work was a four-channel PicoScope 5000 Series with 14-bit resolution and a 200 MHz maximum bandwidth. In this study, the rapid block mode was used for data acquisition in order to allow the log-like sampling required for monitoring the drifts over a large time interval.

Measurements were carried out with a 120 µs switching period and 10% Duty Cycle, i.e., by applying a gate bias rising from −5 V to 20 V in 6 µs, and staying at 20 V for the further 6 µs during the low-(drain)-voltage on-state time interval (see Figure 2a). In off-state conditions, a V_PH stress voltage is applied to the DUT, whereas in the on-state V_PL it is set to 3 V (see Figure 2b). V_GL is typically set to −5 V in order to prevent a false turn-on and ensure the safe operation against voltage spikes on the gate [6]. During the 6 µs rising ramp, the I_DS–V_GS characteristic is reconstructed, allowing the extraction of the device V_TH using the extrapolation in the linear regime method [7,22]. To perform a correct R_ON extraction, at the end of the gate ramp, a stable V_GH level is held for 6 µs to compute R_ON as the ratio between the measured V_D1 and I_DS averaged over the 6 µs range.

The chosen I_DS–V_GS sweep rate represents the best compromise between speed and accuracy, since the short time required for the V_TH and R_ON measurement minimizes the fast recovery between stress phases but still provides enough samples for a correct I_DS–V_GS acquisition.

The DUTs were commercially available TO−247 packaged SiC MOSFETs based on a vertical structure for which a good measurement repeatability was found. Accordingly, we discuss the results obtained on a single device without loss of generality. The fresh I_DS-V_GS characteristic acquired with the custom setup is shown in Figure 4.

3. Results

In this section, we discuss the results obtained with the OTF characterization system presented in Section 2. The results are shown in terms of V_TH and R_ON drifts.

A sequence of no-stress acquisitions (i.e., V_PH = 0 V) is performed on fresh devices at the beginning of each characterization and the corresponding I_DS–V_DS curves were acquired to set a reference value (V_TH0 and R_ON0) from which the relative drifts are evaluated. Then, the parameter evolution is monitored for 1000 s. ∆V_TH is simply calculated as (V_TH–V_TH0), whereas the acquired R_ON values are normalized with respect to the fresh value (R_ON0).

3.1. V_TH and R_ON Drifts

The data obtained during the OTF characterization are shown in Figure 5. As we can see in Figure 5a, a significant negative V_TH drift was observed only after several stress cycles (e.g., −0.55 V at 1000 s). The R_ON parameter evolution is shown in Figure 5b, in which a small benign negative shift of ≈−3.5% was observed after 1000 s stress.

To gain further insights on the origin of these behaviors, we investigated the trans-characteristics (I_DS–V_GS) evolution during stress. Accordingly, in Figure 6, we report three transfer curves measured at some relevant time instants. That is, the green solid curves, referring to the fresh devices, are used as reference, while the black dotted and red dashed curves correspond to the first (≈110 µs) and to the last (1000 s) stress period, respectively.

The parameter drifts shown in Figure 5 find consistent correspondence with the trans-characteristics drifts of Figure 6. No appreciable drifts were observed after the first stress period on both V_TH and R_ON, whereas non-negligible variations appeared after 1000 s of stress. A considerable triode-current variation (i.e., R_ON drift) is present in correspondence with the last stress cycle, in which a slight I_DS increase (see inset of Figure 6b) is a signature of decreased R_ON. The negative V_TH shift observed in Figure 5a is consistent with the I_DS curve shift in Figure 6b after 1000 s. These negative drifts could be potentially explained by the presence of traps at the SiC/SiO₂ interface [18,19,20] and the long transients observed could be a signature of charge emission dynamics.

3.2. Effects of Measurement Conditions on the Parameter Drifts

In order to better understand the mechanism involved in the observed drifts, it is important to know the influence of the measurement conditions on the parameter drifts. To this end, the effects associated to (i) the gate-driving voltage provided in on-state (V_GH) and (ii) off-state drain voltage (V_PH) were investigated. With the aim of pursuing a deeper investigation, after 1000 s stress, an additional 1000 s measurement phase was inserted for monitoring the parameter recovery after the V_PH removal. During this additional phase, the V_PH bias is no longer applied to the DUT and the drain voltage in the off-state condition is set to 0 V. On the other hand, the same gate ramp (V_GL; V_GH) and low drain voltage (V_PL) are provided to the DUT for extracting V_TH and measuring R_ON in the triode region.

To highlight the V_GH effect on the observed drifts, the characterization was performed by ramping the gate voltage from −5 V to three different V_GH levels (15 V, 17.5 V, and 20 V), whereas the V_PH voltage was fixed to 100 V. The results obtained for the V_TH and R_ON parameters are shown in Figure 7 and Figure 8, respectively.

The transients observed for both V_TH and R_ON during the stress phase present similar time constants, suggesting a possible correlation between the two phenomena. Particularly, the observed negative V_TH drift should lead to an increase in device conductivity (at a fixed driving V_GH), thus yielding a R_ON reduction. The observed R_ON transient (Figure 8a) could thus be a directly correlated to the V_TH ones (Figure 7a), indicating the presence of a single underlying mechanism.

However, a different V_GH effect was observed for V_TH and R_ON transients during the stress phase. As shown in Figure 7a, the V_TH transients are not affected by the applied V_GH, while a reduction in the R_ON drift is observed for higher V_GH. This can actually be ascribed to the fact that at higher V_GH, the device transconductance (g_m) degrades [23], yielding a negligible impact on the overdrive voltage (i.e., V_GS–V_TH) variations on the device current and, consequently, on R_ON. On the other hand, at lower V_GH, variations in the V_TH affect the device current (i.e., R_ON), due to a less degraded g_m [23]. Accordingly, the R_ON variation increases with decreasing V_GH from 20 V to 15 V (see Figure 8a), even though the associated V_TH transients present negligible differences (i.e., the V_TH drift is the same). Concerning the recovery phase (see Figure 7b and Figure 8b), both V_TH and R_ON drifts are unrecoverable in the considered time interval (i.e., 1000 s), independently on the applied V_GH level. This observation can be explained in two ways. (i) The recovery transients could present time constants longer than 1000 s, thus making the employed time window insufficient for observing them; (ii) the applied V_PH stress (i.e., 100 V) does not affect the parameter drifts, and the observed instabilities can be totally ascribed to the gate switching applied during the OTF measurement. In fact, monitoring the device parameters in the recovery phase requires the gate voltage to be repeatedly switched from negative to positive and vice versa. As a consequence, the corresponding stress cannot be removed, making the second hypothesis more likely. To prove this point, the drain bias should be completely removed from the stress phase (V_PH = 0 V), thus monitoring the DUT behavior when just the V_GS stress is applied. Clearly, the results obtained with V_PH = 0 V do not mimic a real operative condition but are nonetheless useful to clarify the origin of the observed drifts.

The results obtained with V_PH = 0 V are shown in Figure 9, in which the transients measured during the stress phase are compared with those obtained for V_PH = 100 V.

The results shown in Figure 9 confirm our hypothesis, since no appreciable variation between the drifts measured with V_PH = 0 V and V_PH = 100 V was found, yielding nicely overlapped transients. Accordingly, the observed drifts can be totally ascribed to the driving V_GS, at least for relatively low V_PH (i.e., 100 V). This result is consistent with the vertical structure presented by tested devices. In fact, the influence of the drain voltage on interface states is limited by the physical distance between the oxide and the drain contact, while the gate bias plays a major role on the V_TH stability [7,8,9]. However, thanks to the large breakdown voltage of SiC devices, the drain voltage applied in the off-state could be significantly higher than 100 V during a typical switching operation; thus, the complete absence of drain-induced instabilities cannot be ruled out. Accordingly, the V_PH role has to be studied for sufficiently high stress voltages to observe the corresponding effect.

We now investigate the V_TH and R_ON drifts at higher stress voltages (V_PH). To this end, it is important to keep the driving V_GL and V_GH constant in order to discern the gate/drain contributions. Accordingly, a gate voltage between −5 V and 20 V was applied to the DUT, consistently with the waveforms reported in Figure 2, while three different V_PH levels were considered (100 V, 250 V, and 500 V). A non-negligible V_PH effect is observed on the V_TH transients (Figure 10), whereas the corresponding R_ON drifts present a weak dependence on the applied V_PH (see Figure 11).

Negligible differences were observed on the V_TH transients measured at 100 V and 250 V, whereas the negative V_TH shift is more pronounced at V_PH = 500 V (Figure 10a), indicating that the off-state stress voltage plays a role to some extent. Interestingly, this additional drift is recoverable within 1000 s from the V_PH removal (see Figure 10b), indicating that negative BTI (NBTI) effects are non-permanent and are enhanced by high V_PH values. The fact that stress and recovery transients have similar time constants suggests that both mechanisms are governed by two similar and opposite slow processes. Moreover, no recovery was observed for V_PH = 100 V and V_PH = 250 V, confirming that lower off-state stress voltages do not produce any additional instability with respect to that induced by the gate potential. On the other hand, as shown in Figure 11, the slow R_ON transients observed in the range between 1 s and 1000 s present negligible V_PH dependence and just a weak recovery appears at V_PH = 500 V (at least within 1000 s from the stress removal, as discussed in Section 3.1). This result is consistent with the V_GH dependence previously investigated, indicating that the large gate bias applied in this phase (i.e., V_GH = 20 V) makes the device current less sensitive to the V_TH variations. In fact, the maximum R_ON dynamics was observed at V_GH = 15 V (see Figure 7a), indicating that this condition is optimal to highlight the V_PH effect even on the R_ON parameter. Accordingly, a new set of measurements was taken for a gate voltage ranging between V_GL = −5 V and V_GH = 15 V, exploring the same V_PH levels used previously (100 V, 250 V, and 500 V). The corresponding V_TH and R_ON drifts are reported in Figure 12 and Figure 13, respectively.

Once again, the negative V_TH shift observed at V_PH = 500 V is stronger with respect to that measured at lower V_PH (Figure 12a). At the same time, the R_ON drift clearly changes from −10% to −17% while passing from 250 V to 500 V, showing the same V_PH dependence observed on V_TH (compare Figure 12a and Figure 13a). The fact that similar trends were observed on both V_TH and R_ON degradation confirms that the observed instabilities share the same origin. Particularly, the R_ON drift is a direct consequence of the V_TH one, since at V_GH = 15 V, the less degraded g_m [23] makes the device current (i.e., R_ON) highly sensitive on the overdrive voltage (i.e., V_GH–V_TH). Accordingly, the significant impact of the drain stress voltage observed on V_TH yields an additional R_ON drift at V_PH = 500 V, whereas a negligible effect is observed at 100 V and 250 V.

Further evidence of the V_PH role is given by the partial recovery observed after 500 V stress. Almost no recovery was observed after the stress performed at 100 V and 250 V, whereas the recovery transients appear for both R_ON and V_TH at 500 V. In fact, after the V_PH removal, the drain-induced instabilities can be recovered, whereas the gate-induced ones are still present, yielding a residual drift in V_TH and R_ON. Accordingly, the recovery monitoring can be used to isolate the drain-induced instabilities from the gate-related ones, whereas the effect of the gate-driving voltage can be observed by reducing (or by possibly removing) V_PH.

4. Conclusions and Recommendations

The developed measurement technique is able to highlight V_TH and R_ON drifts in packaged SiC power devices. The observed slow negative V_TH shift was associated with the presence of traps at the SiC–SiO₂ interface. A direct correlation between V_TH and R_ON drifts was first speculated and then verified. To this end, the impacts of the gate-driving voltage (V_GH) and of the off-state stress drain voltage (V_PH) were separately investigated. At a relatively low V_PH (i.e., 100 V), the drifts can be totally ascribed to the repeated switching of the gate signal, whereas the V_PH influence could be observed only at 500 V. This result is consistent with the vertical structure of tested devices, for which the gate potential is expected to mainly affect the dynamics of traps at the oxide–semiconductor interface. In order to observe drain-related effects in vertical devices, it is thus recommended to apply a large off-state stress voltage (V_PH), which was limited to 500 V in this study. The outcomes obtained with the developed system are instrumental to reveal the mechanisms limiting device stability and performance, by discerning the gate/drain contribution on the parameter degradation. To get a better insight into gate-related effects, in future works, we will investigate other bias combinations, and we will study the effect of the negative gate voltage applied in the off-state (V_GL). Moreover, the capabilities of the designed setup will be further enhanced by including hard-switching characterization, which will be used to highlight the effect of the transitions when SiC devices are driven in more severe switching conditions.