A Fast and Cost-Effective Calibration Strategy of Inter-Stage Residual Amplification Errors for Cyclic-Pipelined ADCs ^†

Abstract

Due to nonideal residue amplification, the limited resolution of pipelined analog-to-digital converters (ADCs) has become a popular research topic for ADC designers. High-gain and high-speed amplifiers usually consume too much power for a decent ADC. Hence, this paper proposes a fast and cost-effective foreground calibration strategy for cyclic-pipelined ADCs. The calibration strategy compensates for the gain error due to inter-stage residual amplification, which alleviates the DC gain requirement for internal amplifiers. Unlike other digital calibrations, the proposed scheme is implemented with a cyclic-pipelined structure, and only one parameter needs to be calibrated, whose value can be feasibly calculated by the Fix-Point Iteration algorithm. The proposed calibration scheme is implemented in an area-efficient 16-bit, 2 MS/s cyclic-pipelined ADC, fabricated in 180 nm CMOS technology. The ADC is designed and realized by cycling a 6-bit sub-ADC four times with 1-bit redundancy each time. The calibration algorithm manages to recover the sampled data to 93.85 dB spurious free dynamic range (SFDR) even with a 57.8 dB-DC-gain amplifier. The total power consumption of ADC is 17.92 mW and it occupies an active area of 1.8 mm².

1. Introduction

In addition to the ever-growing demand for conversion speed, low power dissipation and compatibility with deep-sub-micron technology become other essential criteria in state-of-the-art designs [1,2]. Pipelined analog-to-digital converters (ADCs) implemented with switched-capacitors techniques have been growing popular due to their relative high-speed and high-resolution performances. However, the design of pipelined ADCs has become more challenging in deep-sub-micron technology nodes due to a severe nonlinearity caused by internal digital-to-analog converters (DACs) and inter-stage gain errors.

One of the primary bottlenecks of high-performance pipelined ADCs is the capacitor mismatches. The mismatches between the binary-weighted capacitors could cause deviations in the ADC transfer curve [3]. Worse, such deviations would accumulate during the conversion and result in additional distortion. The conventional approach is to increase the capacitance values at the price of a larger area and high power consumption.

Another challenge of high-performance pipelined ADCs is the residue amplifier. The residual amplification should be realized with high-speed, low-noise, and high-linearity requirements. However, designing such operational amplifiers (Op-Amps) is a nontrivial task. The limited supply headroom and low intrinsic device gain may lead to a power increase in future deep-sub-micron processes. Furthermore, the multi-stage design would perform worse in transient response than the single-stage with the same power consumption [4]. However, the single-stage design would significantly impact the overall performance of the ADC due to the need for closed-loop gain accuracy.

Digital calibration techniques are widely used to improve the resolution and linearity of ADCs, and they can release the stringent requirements for capacitor matching accuracy and the high DC gain of residue amplifiers. The primary calibration techniques could be divided into background and foreground. Background calibration could correct the conversion errors without disrupting typical A/D conversion. Thus, it has the advantage of being immune to temperature changes, voltage supply variations, device aging, etc. On the contrary, foreground calibration schemes do not rely on the statistical distribution of input signals, which makes them applicable to almost all data conversion scenarios.

The foreground calibrations discussed in [5,6,7] achieve more than 13-bit linearity, while they require a particular set of input signals to provide the calibration information. Based on the dithering technology presented in [8,9,10], the background calibrations used additional dithering or pseudo-random sequences to extract errors and track environment changes. However, they suffer from slow convergence speed, and their calibration accuracy is limited by the dithering magnitude, which wastes more redundancy. Previous work [11] shaped the amplification errors like the noise, which make errors cause a negligible impact on the in-band signal-to-noise-and-distortion ratio (SNDR), but it requires supplementary oversampling technology. The LMS (least mean square)-based background calibration proposed in [12] could speed up the convergence, but it also requires an extra-slow and more accurate ADC to estimate the conversion errors of sub-stage ADCs. Other calibration methods, such as [13], require an extra clock and achieve all calibration in the analog domain with higher power consumption.

In this work, we propose a cyclic-pipelined structure with a foreground calibration scheme to correct the gain errors of residue amplification with little cost. Due to the identical hardware implementation, the gains of all residue amplification between sub-stages are constant throughout the pipeline processing. This feature makes our calibration algorithm much more manageable and feasibly achieves high resolution. With corresponding off-chip digital post-processing, the actual gain of amplifiers can be estimated and used to eliminate the gain errors. Unlike the previous work regarding applying codes for DAC in [14,15], our calibration solution has remarkable advantages in convergence speed and storage requirements. The self-calibrated structure in [14] requires 2048 sampling points for convergence, and it employs a multi-level calibration strategy, which introduces uncertainty in accuracy when the number of levels increases. The self-estimation technique in [15] needs a 4 kB on-chip ROM for parameters, which could not be realized in time against PVT variation. Therefore, due to its remarkable convergence speed, our work is highly adaptable and can withstand process, voltage, and temperature variations. It is also accommodating to process scaling.

The paper is organized as follows: Section 2 theoretically illustrates the relation between the DC gain of the amplifier and voltage deviation, followed by the principle of the calibration procedures as well as details of the proposed architecture in Section 3. Section 5 presents the measurement results, and we finally conclude the work in Section 6.

2. Inter-Stage Gain Calibration

2.1. Principle of Cyclic-Pipelined ADCs

The basic architecture of a cyclic-pipelined ADC with 1-bit redundancy is illustrated in Figure 1. As shown, the input signal is sampled and held by sampling capacitors and then is A/D converted by an N-bit sub-ADC (SADC). Due to the limited word length of digital signals, differences between input signals and quantization levels are inevitable, and these differences are named quantization errors or residual errors. In order to improve the conversion accuracy, these residual errors also need to be eliminated, and one possible solution is to amplify these errors, followed by another round of A/D conversion. The residual amplification factor is set to $2^{N-1}$ to provide 1-bit redundancy in the pipeline structure. It can tolerate offset of the comparator and other nonideal inside the sub-ADC, and reduce the requirement of output range of residual amplifier. This “subtraction-amplification-A/D Conversion” strategy can be iterated several times for accuracy requirements.

Regarding implementation, residual errors can be obtained via a combination of an SADC, a DAC, and a subtractor, while amplifiers can execute residual amplifications. The digital codes converted at each sub-stage will be processed to calculate the final A/D output, and the process can be implemented either on-chip or off-chip. The main feature of the cyclic-pipelined ADC shown in Figure 1 is that all of its residual amplification shares the same hardware, including the same capacitor array, which leads to an identical amplification value for each sub-stage. We will demonstrate the significance of this merit in the following sections.

2.2. Requirement of Residual Amplifier without Calibration

As for the ideal amplifier, the result of amplification at each sub-stage with 1-bit redundancy can be expressed as $V_{out,i}=2^{N-1}·V_{res,i}$, where N is the bit number of sub-ADC and i stands for the ith stage. Compared to an ideal amplifier, a practical one has a finite open-loop gain $A_{vol}$, causing actual amplification results to be consistently lower than the desired values. As the reasoning goes, the actual amplification result for a practical amplifier should be derived as follows:

$$V_{out,i}^{\prime }=\frac{A_{vol}·2^{N-1}}{A_{vol}+2^{N-1}+1}·V_{res,i}=G_A·V_{res,i}$$

(1)

where $G_A$ means the closed-loop gain of the residual amplifier. Hence, the output deviation of each residual amplification due to the finite DC gain can be derived as follows:

$$\Delta V_{out,i}=V_{out,i}-V_{out,i}^{\prime }=\frac{\left(2^{N-1}+1\right)·2^{N-1}}{A_{vol}+2^{N-1}+1}·V_{res,i}$$

(2)

Because residual errors occur at every time of amplification, there would be M-1 times amplification in an M-stage cyclic-pipelined ADC. The ith amplification error would be divided by $2^{i(N-1)}$ for the final output calculation in digital code alignment without any intervention, which means that it is the first amplification error that dominates the overall performance. Hence, the total voltage deviation could be derived as follows:

$$\Delta V_{out,adc}=\sum _{i=1}^{M-1}\Delta V_{out,i}/2^{i(N-1)}\approx \frac{\Delta V_{out,1}}{2^{N-1}}$$

(3)

It is reasonable to assume that the input of the first residual amplifier $V_{res,1}=V_{in}-V_{dac,1}$ follows a uniform distribution as $V_{res,1}$∼$U(0,V_{SLSB})$, where $V_{SLSB}$ is the least significant bit of SADC, i.e., $V_{SLSB}=V_{ref}/2^N$. Then the output deviation should also follow the same distribution pattern as $\Delta V_{out,adc}$∼$U(0,Q)$, where the coefficient Q is

$$Q=\frac{2^{N-1}+1}{A_{vol}+2^{N-1}+1}·\frac{V_{ref}}{2^N}$$

(4)

and the root mean square (RMS) of $\Delta V_{out,adc,rms}$ is

$$\Delta V_{out,adc,rms}=\frac{Q}{\sqrt{12}}$$

(5)

Like the concept of signal-to-quantization-noise ratio (SQNR), we could also characterize the influence of this amplification error by signal-to-amplification-noise ratio (SANR), and if the full-scale input amplitude equals the reference voltage, the SANR can be derived as follows:

$$\mathrm{SANR}=\frac{V_{ref,rms}}{\Delta V_{out,adc,rms}}=\frac{V_{ref}/\sqrt{2}}{Q/\sqrt{12}}=\sqrt{6}·\frac{2^N\left(A_{vol}+2^{N-1}+1\right)}{2^{N-1}+1}$$

(6)

In actuality, when the DC gain of the residual amplifier is relatively large (much larger than $2^{N-1}$), the SANR is approximately linearly related to the DC gain. For example, if we set the resolution of sub-ADC to be 5 bits, then the relation between SANR and DC gain can be expressed as follows:

$$\mathrm{SANR}\left(\mathrm{dB}\right)\approx A_{vol}\left(\mathrm{dB}\right)+20{log}_{10}\left(\sqrt{6}·\frac{2^{N-1}}{2^{N-1}-1}\right)={\left.A_{vol}\left(\mathrm{dB}\right)+8.34\left(\mathrm{dB}\right)\right|}_{N=5}$$

(7)

Since the amplification error and the quantization noise will together limit the whole system’s performance, and they are statistically independent, the SNDR of the whole ADC could be derived as follows:

$$\mathrm{SNDR}=20{log}_{10}\left(\frac{V_{ref,rms}}{\sqrt{\Delta V_{out,adc,rms}^2+V_{q,rms}^2}}\right)$$

(8)

where $V_{q,rms}$ is the RMS of the quantization noise of the whole ADC system.

The above discussion explains that for the circumstance whereby DC gain is insufficient, the amplification error will overwhelm the quantization noise, causing the SNDR of the whole ADC to be limited by the SANR expressed in (7). As shown in Figure 2a, the high agreement between the behavioral simulation results and the calculated results proves the correctness of the model and delivers the exact relationship between the inter-stage amplifiers required for the accuracy of the pipelined ADC.

3. Calibration Strategy

3.1. Basic Calibration Scheme

Fortunately, pursuing the high DC gain of amplifiers is unnecessary to minimize amplification errors. Alternatively, the amplification errors could be corrected in the digital domain with extra hardware costs or an off-chip process.

Since we are not further designing ideal-alike amplifiers, actual residual amplification under limited open-loop gain should be taken into account. If we define the actual gains at each sub-stage as all equal to “$G_A$” because they all share the same hardware, the final result of the A/D conversion should be corrected with $G_A$ rather than $2^{N-1}$, as follows:

$$V_{out,adc,cali}=\frac{V_{ref}}{2^N}\sum _{i=1}^M\left(\frac{D_i}{G_A^{i-1}}\right)$$

(9)

where $V_{out,adc,cali}$ is the calibrated output voltage of the entire ADC, and $D_i$ is N-bit digital codes produced by each SADC. It is worth noting that the digital codes here are all in decimal representation in the following analysis.

Also shown as the blue line in Figure 2b, we find that an amplifier with DC gain as low as 40 dB could still achieve 16-bit resolution with four times cycling as long as the closed-loop gain $G_A$ is taken into account for calibration based on (9).

In other words, if we apply the digital codes and their corresponding gain at each sub-stage to calculate the final output, limited gains of residual amplifiers will no longer be a bothering issue. It is noteworthy that the amplification “$G_A$” between two A/D conversions equivalently brings “${log}_2{G}_A$” bits extra resolution. Taking our design as an example (cycle times M = 4, resolution of sub-ADC N = 5), the theoretical effective-number-of-bit (ENOB) could be calculated as follows:

$$ENOB=N+(M-1)·{log}_2\left(G_A\right)$$

(10)

Behavioral simulation results in Figure 2b prove that the distortion caused by residual amplification is due to the “mismatch” of gain between ideal value $2^{N-1}$ and practical value $G_A$, not the insufficient gain. In other words, the ADC accuracy degradation brought about by insufficient gain is shown in (10), but is far from comparable to the gain mismatch. Therefore, the remaining problem lies in accurately estimating the actual closed-loop gain of the residual amplifier.

3.2. Estimation of Inter-Stage Gain

Considering that the applied cyclic structure is not intuitive for analysis, we expand the data flow and analyze it as a conventional structure, as shown in Figure 3. The whole system is divided into two parts: the first stage of the pipeline and a back-end ADC (BADC).

The first stage generates a residual voltage $V_{res,1}$ after its A/D conversion, and this voltage will be amplified by a gain of $G_1$. The BADC performs an extra A/D conversion to quantify the amplified residual voltage $G_1·V_{res,1}$. Because of the hardware reusing strategy, the BADC is also realized via the iteration of residue subtraction, amplification, and conversion process, and its conversion result is a set of digital codes from each sub-stage $D_2,D_3,D_4$, which will be used to perform the weighted accumulation to build up the back-end digital code $D_{BE}$. Although the inter-stage gains $G_1,G_2,G_3$ are equal, we keep the suffix-number to clarify the explanation.

A multiplexer (MUX) with some auxiliary control logic is added between the SADC and DAC at the first stage so that a “residual” signal can be generated at node $V_{res,1}$.

The steps for the gain estimation are shown in Figure 4. We set the input signal $V_{in}$ to be a constant and then drive two different control codes to the MUX, obtaining two residual signals, respectively. Then, these two signals would be amplified by $G_1$ and quantified by the BADC subsequently:

$$D_{BE}=-\frac{2^{N_{BE}}}{V_{ref}}·G_1\left(V_{in}-\frac{Code}{2^N}{V}_{ref}\right)$$

(11)

where $N_{BE}$ means the the ENOB of back-end ADC. We could control the system to avoid voltage variations at the input by skipping the sampling behavior during the calibration procedure, and control codes should be carefully selected to ensure that the amplified residual voltage $G_1·V_{res,i}$ does not exceed the full-scale range of BADC at any time. Based on this principle, we set $Code=\pm 1$ and make a difference between two quantization results. According to (11), we obtain

$$\frac{\Delta D_{BE}}{2^{N_{BE}}}=\frac{G_1\times \Delta Code}{2^N}=\frac{G_1}{2^{N-1}}=\frac{G}{2^{N-1}}$$

(12)

As we know, the BADC is not an ideal ADC either, where the gains of its inter-stage amplification $G_2,G_3$ are smaller than $2^{N-1}$. Hence, the back-end digital output code $D_{BE}$ should also be calibrated with the gain G. For the purpose of calculating the digital output code precisely, we need to apply the A/D conversion results from each stage as follows:

$$\begin{array}{c}\hfill \frac{\Delta D_{BE}}{2^{N_{BE}}}=\frac{1}{2^N}\left(\Delta D_2+\frac{\Delta D_3}{G}+\frac{\Delta D_4}{G^2}\right)\end{array}$$

(13)

Combining the above two Equations (12) and (13), we obtain

$$G=\frac{1}{2}\left(\Delta D_2+\frac{\Delta D_3}{G}+\frac{\Delta D_4}{G^2}\right)$$

(14)

The gain $G_A$ estimation theoretically requires only two calibrations, that is, two times the conversion time of the ADC system, which has a significant advantage over other background or foreground calibrations in terms of convergence speed. Considering the system noise, repeating the calibration and averaging the gain is not too much of a burden on the convergence time of the system.

3.3. Calibration Accuracy

The accuracy of the calibration scheme depends on the accuracy of the inter-stage gain estimation, which can be hampered by two types of errors: the principled error from the back-end ADC and the computational error from calibration processing.

The cubic Equation (14) can be solved by specific iteration methods such as Fixed Point Iteration or Newton–Raphson Iteration [16], as shown in Figure 5. The proof of convergence has been provided in Appendix A. $G_A$ denotes the actual inter-stage gain, $G_E$ indicates the limit value calculated by iteration, and $G_k$ means the calculation result from the $k_{th}$ cycles. Based on that, $\delta$ results from the computational error, and $\Delta G$ comes from the principled error, which could not be corrected by any processing.

In this subsection, we will analyze how the deviation of the calculated value, including principled error and computational error, affects the final resolution, and we then illustrate that six times iteration is enough for a decent result, which means that the extra cost of our calibration scheme is well accepted.

At this point, we assume that the calculation of the loop iteration is error-free and that there remains the principled error, as shown in the following equation:

$$G_E=G_A\pm \Delta G=G_A\left(1\pm \eta \right)$$

(15)

where coefficient $\eta$ means the relative error of the gain as $\eta =\Delta G/G_A$. Based on (4), if we rewrite the expression in terms of the closed-loop gain:

$$Q=\frac{G_A-G_E}{G_A}·V_{SLSB}$$

(16)

Therefore, according to (5), (10), and (16), the RMS of the output deviation and quantization noise of the entire ADC system could be rewritten into

$$\begin{array}{c}\hfill \Delta V_{out,adc,rms}=\frac{1}{\sqrt{12}}\left[\frac{\eta }{(1\pm \eta )}·\frac{V_{ref}}{2^N}\right]\end{array}$$

(17)

$$V_{q,rms}=\frac{1}{\sqrt{12}}\left(\frac{V_{ref}}{2^N·G_A^{M-1}}\right)$$

(18)

And the damage to SNDR could be derived as

$$\left|\Delta SNDR\right|=10{log}_{10}\left(\frac{\Delta V_{out,adc,rms}^2+V_{\mathrm{q},\mathrm{rms}}^2}{V_{\mathrm{q},\mathrm{rms}}^2}\right)=10{log}_{10}\left({\alpha }^2+1\right)$$

(19)

where we set the coefficient $\alpha$ as the relative RMS value of the output deviation and quantization noise. By combining (17) and (18), we obtain

$$\begin{array}{cc}\hfill \alpha & =\frac{\Delta V_{out,adc,rms}}{V_{q,rms}}=\left(\frac{\eta }{1\pm \eta }\right)·G_A^{M-1}\approx \eta ·G_A^{M-1}\hfill \end{array}$$

(20)

The above two equations provide a way to estimate the damage to the accuracy of the whole ADC system, which reveals that a larger relative error $\eta$ of the closed-loop gain would cause more damage when the absolute value of the actual gain $G_A$ remains constant.

Due to the limited resolution of the BADC, there is an inevitable deviation between $G_A$ and $G_E$ via the calibration strategy, and the deviation $\Delta G$ due to the BADC could be estimated according to (11):

$$\Delta G\in \left[0,\frac{2^N}{2^{N_{BE}}}\right]$$

(21)

which could also be considered as the quantization error of the calibration strategy. In addition, the maximum deviation could be simplified as

$$\Delta G_{max}=\frac{2^N}{2^{N_{BE}}}=\frac{2^N}{2^{N+\left(M-2\right){log}_2{G}_A}}=\frac{1}{G_A^{M-2}}$$

(22)

The maximum deviation $\Delta G_{max}$ reveals the factor that the output digital word would remain unchanged even if a deviation of gain smaller than $\Delta G_{max}$ exists, resulting in the descent of SNDR. Fortunately, according to (19) and (20), the coefficient $\alpha$ equals 1 in this case, and the descent of SNDR is approximately 3 dB in the worst situation.

However, we ignored an issue: the iterative algorithm gradually converges to $G_E$ instead of $G_A$, and the calculated value $G_k$ would fall in the range $\left[G_{E}to\delta ,G_E+\delta \right]$ after k iterations, as shown in Figure 5. Therefore, taking the iteration error into consideration, the maximum deviation of the closed-loop gain should add $\delta$ on the basis of the previous value in the worst situation and the descent of SNDR could be calculated as followed:

$$\begin{array}{cc}\hfill \left|\Delta SNDR\right|& =10{log}_{10}\left({\overline{\delta }}^2+1\right)\hfill \end{array}$$

(23)

where $\overline{\delta }$ means the normalized computational error $\delta /\Delta G_{max}$ and the simulated results are presented in Figure 6. This indicates that it is not necessary to iterate over and over again to eliminate the iteration error because there is an unavoidable 3 dB descent of SNDR due to the limited resolution of the BADC.

Considering the calibration accuracy and the power consumption comprehensively, we finally chose to iterate six times to solve Equation (14), and under this condition, the descent of SNDR is approximately 3.6 dB, which is well accepted.

4. Cyclic-Pipelined ADC Architecture

4.1. Architecture of Proposed ADC

The architecture of the proposed cyclic-pipelined ADC is shown in Figure 7a. It consists of a 5-bit binary weighted capacitor array, a residue amplifier, a 6-bit signed Flash ADC and corresponding control logic. The principle of signal processing of this ADC is similar to other cyclic ADCs that were proposed in [17,18,19]. For a more convenient explanation, let us assume that the residue amplifier is ideal, and then the operation of the A/D conversion can be explained as follows:

1.

The 5-bit capacitor array samples the input $V_{in}$ via control signal $S\&H_{vin}$ and $S\&H_{ena}$.

2.

The Flash ADC converts the sampled voltage into digital code, which will be applied to the capacitor array to produce the residual error.

3.

The residue amplifier magnifies the residual error by a factor of 16, which contains 1 bit redundancy compared to the resolution of the capacitor array (16 times magnification is achievable only with ideal amplifiers, and it has to be calibrated in reality).

4.

The amplified residual error $V_{residu}$ is sampled by the capacitor array again via control signal $S\&H_{residu}$ and $S\&H_{ena}$.

5.

Repeat the steps mentioned above from 2 to 4 three times.

The 5-bit capacitor array is implemented in a conventional binary weighting structure with a reference multiplexing scheme, as also shown in Figure 7a. In this design, a total of four cycles are performed, which converts the analogue signal into 18-bit digital signals (1 bit from polarity, 4 × 3 = 12 bits from the first three cycles, and 5 bits from the last cycle). However, considering the impact of gain calibration, we eventually set the design target to 16-bit accuracy. Although the Flash ADC could sustain 5-bit resolution, the first three cycles only generate 4-bit data each time. This is because we have the 1-bit redundancy design to tolerate the offset of the comparator and other nonideals inside the Flash ADC, as shown in Figure 8.

As long as the signal path shown in Figure 8 qualifies to be a linear time-invariant system, this 1-bit redundancy design could cancel off one LSB conversion error from the first stage and attenuate that from the second stage by a factor of $2^{-(N-1)}$, making it negligible compared to other design concerns, highlighted in green in Figure 8. Furthermore, this analysis can be expanded to a multi-stage pipelined ADC, and the final impact of Flash-ADC-induced conversion error will be attenuated by $(M-1)·2^{N-1}$ times, where M represents the number of pipelined stages in the ADC.

Of course, as we analyzed in the previous section, an amplification of 16 is not achievable due to the finite gain of the amplifier, and the inter-stage gain calibration scheme is proposed to overcome this problem.

4.2. Timing Requirement

To realize a high-precision ADC with this architecture, except that $S\&H_{ena}$ should not be off first during the sampling and re-sampling phase, and the Flash ADC should be enabled after the capacitor array finishes sampling to void kick-back noise, switches have to be specially controlled during the residue amplification and re-sampling period (step 3 and step 4 mentioned in the previous sub-section). There are three rules to be followed:

1.

Firstly, feedback capacitors have to be reset every time before amplification to eliminate remaining charges, requiring switch ${\varphi }_2$ to not overlap switch ${\varphi }_1$.

2.

Secondly, switch ${\varphi }_1$ has to cut off the connection between the capacitor array and the amplifier before sampling. Otherwise, the to-be-sampled signal $V_{res,a}$ and changes of control logic $Ctr{l}_{p,c,n}[5:0]$ will affect the input of the amplifier and consequently deteriorate the loop.

3.

Thirdly, switch ${\varphi }_2$ should be turned on only after the converting process of Flash ADC to ensure that $V_{res,a}$ is precisely sampled and converted.

To meet all the rules above, we arranged the timing of switches as shown in Figure 7b, where important time points are marked by the red line and the rules’ number. The timing consumption of one A/D conversion is illustrated in Figure 9. It is worth mentioning that multiple clocks are used for the Sample-and-Hold and Residue Amp phase to provide sufficient settling time. The circuit used to generate all those switch-control signals is not explained specifically here since they are conventional delay cells and SR latches.

4.3. Residue Amplifier

Since the limited gain of amplifiers can be calibrated, and a high-speed amplifier could improve the sampling rate of the entire ADC system, the single-stage amplifier has considerable advantages over its multi-stage counterparts in this respect. As we explained before in Section 3, this amplifier should support three different modes: (1) reset the feedback capacitors; (2) amplify the residual errors; and (3) hold the amplified voltage for next-stage sampling. One possible implementation is shown in Figure 10.

The separation of different working modes actually alleviates the trade-off in amplifier designs: during the amplification period, the closed-loop gain of the amplifier is relatively larger (around 14 for example), but the capacitive loads can be small, which is the sum of feedback capacitors $C_{fb}$, the parasitic capacitors of switches $C_{sw}$, and the input capacitor of Flash ADC $C_{in}$. On the contrary, during the sampling period, the load capacitance $C_{array}$ is much larger, but the amplifier is connected in unity gain configuration, so the amplifier will not work in a high-gain-and-heavy-load scenario. Additionally, unlike multi-stage amplifiers, where the dominant pole is determined by internal compensation capacitors, single-stage amplifiers have dominant poles at the output nodes and, hence, are capable of adjusting the gain-bandwidth-product dynamically when necessary, achieving faster steady-state responses.

Therefore, the schematic of a high-speed single-stage fully differential amplifier is designed, as shown in Figure 11. The amplifier, based on a P-type folded cascade structure, divides the conventional differential pair into two parts [20]. The bias current is replicated from an external input current through a low-voltage cascode current mirror, which is not marked in the figure. The local common-mode feedback (LCMFB) allows a further increase of the dynamical currents without scaling static currents. LCMFB could also increase small-signal performances due to the small-signal current gain provided by the LCMFB resistors. Two DC level shifters have been cross-coupled to the differential pair transistors, implemented by the flipped voltage followers (FVFs). Under quiescent conditions, the input differential pair transistors are biased by the DC level shift $V_b$ and share the same static current $I_b$ regardless of process, supply voltage, or temperature (PVT) variations. When a nonzero input signal arrives, the dynamic currents of the input differential pair would not be limited by $I_b$. Meanwhile, an increment in trans-conductance by a factor of 2 is achieved without FVF. The simulation results of the amplifier are shown in

Table 1. Simulation results of the amplifier.

Parameters	This Work
Technology [nm]	180
Supply Voltage [V]	1.8
Capacitive load [pF]	38.7
SR+ [V/μs]	168.5
SR− [V/μs]	168.5
Pos. Settling @ 0.001% [ns]	38.4
Neg. Settling @ 0.001% [ns]	38.4
DC gain [dB]	57.8
PM [°]	70.5
GBW [MHz]	197.4
${\mathrm{I}}_{\mathrm{tot}}$ [mA]	9.4
Area [${\mathrm{mm}}^2$]	0.06

.

4.4. Flash ADC

The architecture of flash ADC is shown in Figure 12, where the timing diagram and the structure of the comparator are also shown. In this architecture, integrated nonlinearity (INL) is mostly caused by the input-referred offset of the comparator. Thanks to the 1-bit redundancy, INL less than 1 LSB can be tolerated. Therefore, the linearity of the Flash ADC is of minor consideration, and power efficiency becomes a more important aspect. To reduce power consumption, the floating inverter amplifier (FIA) [21] is adopted as the pre-amplifier followed by a StrongARM latch, as illustrated in the blue part in Figure 12. FIA will be launched as soon as the comparison begins, and the latch will be launched after the input signal is amplified. By properly sizing transistors, the input-referred offset can be controlled, and low power consumption can be maintained as well.

5. Measurement Setup and Results

5.1. Measurement Setup

The proposed ADC is fabricated in 0.18 $\mathsf{\mu }$m 1.8V CMOS technology and occupies an area of 1.8 mm², as shown in Figure 13. The measurement setups are demonstrated in Figure 14: the low-frequency testing adopts a high-precision audio source (DS360) with differential outputs and two single-ended unity-gain buffers driving the ADC, and the high-frequency testing applies a single-ended-to-differential structure to drive the ADC, which deteriorates the signal linearity to some extent. Both setups adopt passive filter networks before and after the buffers, and these filters are carefully tuned for a descent trade-off between “noise” and “settling time” for both testing scenarios.

5.2. Measurement Results

5.2.1. Calibration Performance

To evaluate the performance of our proposed calibration strategy, we compared the estimated inter-stage gain with the optimum value, $G_{opt}$. The estimated gain is 15.276 (marked in the Figure 15a), which is very close to the optimum value when we sweep the gain from 15 to 16. In addition, the proposed ADC is more robust against the parameter variation compared with previous work [15], as shown in Figure 15b. If we take the 3 dB loss of SNDR as a restriction, the proposed ADC can tolerate 0.4% variation, but the previous work requires than 0.05% variation.

Unlike other pipelined SAR ADCs and their corresponding calibration schemes, there is only one parameter that needs to be calculated, leading to a significant advantage in calculation convergence. Although the equivalent input noise of the op-amp is only 90 dB, which is very small and insignificant to the LSB of sub-ADC, it still has a certain impact on the accuracy of gain estimation. We can use the averaged measurements to eliminate the effect of noise, and the tested results are shown in Figure 16. The sample sizes for the statistics were all 500 points, using 1, 10, 50, and 100 times averaging. What stands out in this figure is the rapid decrease in the standard deviation of SNDR with the increase in calibration average times. The statistical results also demonstrate that the measured SNDR result is acceptable even without averaging, and only $10\times$ averaging is needed to obtain a more convergent result according to the box plot.

5.2.2. Measured ADC Performance

The ADC achieves a peak SNDR of 82 dB at a full-scale 4.6875 kHz input, as presented in Figure 17a. It is worth noting that the total distortion (THD) performance of ADC improves by approximately 20 dB with the gain calibration scheme, and SNDR is limited by the noise floor of the signal source and the INL. As the input amplitude decreases, the SNDR of the overall system decreases linearly, as shown in Figure 18a.

The deviation between the tested results and the fitting curve at the relatively large amplitude (>−40 dBFS) side is mainly due to the INL and the poor noise performance of the signal source as well (the noise floors jump a lot when the signal amplitude is beyond certain thresholds according to the datasheet of the signal source). A dynamic range of 90.8 dB was measured with 4.6875 kHz input signals. High-frequency testing results are shown in Figure 17b, where a full-scale 761 kHz input signal was driven into the ADC, and 76.93 dB SNDR was achieved. In terms of the static performance, the proposed ADC achieves an INL of ±4.8 LSB, as shown in Figure 18b. The large INL is achieved by the mismatch of the binary-weighted CDAC, which is not calibrated.

Although the residue amplifier was optimized for speed and power efficiency, it still consumes 91% of the overall power and becomes the bottleneck for a low-power system. The main reason behind this is that relatively large sampling capacitors (38.72 pF) were used to reduce the thermal noise at the sampling stage.

5.2.3. ADC Performance over Temperature Sweep

Amplifier open-loop gain shifts with voltages and temperatures, causing a potential performance drop of the entire ADC. Therefore, a temperature sweeping measurement was conducted to evaluate this challenge. Ten points of measurements were taken from 30 to 120 degrees Celsius, and the calibrated SNDR was compared with the optimum values obtained by sweeping the gain parameter at that temperature. Due to the flooring effect caused by ADC quantization, the estimated closed-loop gain is slightly lower than the ideal value during calibration at room temperature. However, this characteristic also brings the estimated gain closer to the desired value at high temperatures, thereby reducing the impact of temperature, which is demonstrated in Figure 19. Consequently, the calibrated SNDR even improved when the temperature increased to around 85 °C and only dropped 2 dB at 120 °C, as shown in Figure 19.

6. Conclusions and Discussion

This paper proposes a foreground gain calibration technique that could correct linear errors from the inter-stage amplifiers in cyclic-pipelined ADCs. The calibration scheme could consequently alleviate the DC gain requirement for amplifiers. Due to the cyclic structure, the actual gains of each amplification are identical. Hence, their values can be calculated by the Fix-Point Iteration algorithm. The feasibility and efficiency of the proposed calibration strategy were verified via a 16-bit ADC implemented in 0.18 $\mathsf{\mu }$m technology. Measurement results show that the SFDR can achieve 93.85 dB even with a 57.8 dB-DC-gain amplifier.

This cyclic structure, however, also limits the speed and power consumption performance of the overall ADC system due to its unnecessary large load capacitance in the back-end sub-ADC. Therefore, the ${\mathrm{FoM}}_{\mathrm{w}}$ and the ${\mathrm{FoM}}_{\mathrm{s}}$ of the proposed ADC does not catch that of the state-of-the-art works, as shown in

Table 2. Performance summary and comparison.

	This Work	JSSC 2008 [9]	VLSI 2014 [22]	VLSI 2014 [23]	ISSCC 2014 [24]	JSSC 2018 [25]
Technology [nm]	180	180	180	40	65	55
Architecture	Cyclic-Pipelined	Pipeline	Pipelined SAR	Pipelined SAR	Pipeline	SAR
Supply [V]	1.8	1.8	1.8	1.1	3.3/2.5/1.2	3.3/1.2
Sampling Rate [Hz]	2 M	20 M	5 M	160 M	1 G	16 M
Area [${\mathrm{mm}}^2$]	1.8	3.9	5.7	0.042	18	0.55
Power [W]	17.9 m †	285 m	30.5 m	4.9 m	1.2	16.3 m
SNDR [dB]	82.3	73	99	65.3	69	78
ENOB [bit]	13.37	11.83	16.15	10.55	11.17	12.66
SFDR [dB]	93.8	98	100.2	86.9	86	98
DR [dB]	90.8	-	100.2	-	-	-
${\mathrm{FoM}}_{\mathrm{w}}$ [fJ/c-s]	846.3	3982.7	30.6	83.9	520.8	156.9
${\mathrm{FoM}}_{\mathrm{s}1}$ [dB]	159.8	148.4	178.1	167.3	155.2	164.9
${\mathrm{FoM}}_{\mathrm{s}2}$ [dB]	168.3	-	179.3	-	-	-
Calibration Cost	off-chip 2 samples	on-chip $2^{26}$ samples	off-chip with massive on-chip storage	17 million samples	81 uniformly distributed dither levels as calibration signal	not given in detail

${\mathrm{FoM}}_{\mathrm{w}}=\mathrm{Power}/\left(2^{\mathrm{ENOB}}·2\mathrm{BW}\right)$; ${\mathrm{FoM}}_{\mathrm{s}1}=\mathrm{SNDR}+10{log}_{10}\left(\mathrm{BW}/\mathrm{Power}\right)$; ${\mathrm{FoM}}_{\mathrm{s}2}=\mathrm{DR}+10{log}_{10}\left(\mathrm{BW}/\mathrm{Power}\right)$; ^† Amplifier consumes 16.38 mW, Flash ADC 1.13 mW, and others 0.41 mW.

. A potential improvement approach in the future would be separating the front-end and back-end ADCs and trading the calibration feasibility to some extent for power efficiency.