Synchronization and Sampling Time Analysis of Feedback Loop for FPGA-Based PMSM Drive System
Round 1
Reviewer 1 Report
Line 69 Sentence "Moreover ..." does not make sense to me.
Line 107 P usually stands for power thus its usage as number of pole pairs can be confusing.
Line 158 Figure 3 - The last PI controller output should be vq not vd.
Line 163, 169, 170 These equations are not correct. Why do you multiply Kp gain with difference of current error and error in previous step (k-1) ?
Line 187 The sentence "If the counter count is higher than the switching frequency ..." is not correct as you compare the counter count with required period of PWM in system ticks.
Line 199-202 Sentences "The encoder ... Figure.5." are missing some verbs.
I am missing information of system clock frequency which is essential to calculate delays of each computational step.
How did you calculate time delays 0.5us and 3us ?
Can you please add experiments with start-run-stop or speed reversal behavior of the motor ?
It seems to me that PI controllers are very slow. Normally, change of load should not almost stop the motor. How did you calculate Kp and Ki constants ? And are they the same for all cases and sampling frequencies ?
Are the compare values for PWM generation updated immediately or in top or/and bottom of PWM carrier ?
Please add information about switching frequency to Chapters 4.1 and 4.2.
Can you please specify sampling period of speed encoder ?
If I calculate overall delay, i.e. 5*3.5us + 1us (according to Figure 9), it leads to delay of control loop of 18.5us. Then you can not achieve proper results for sampling frequencies higher than 27kHz. If I consider the better case, i.e. 3*3.5us + 1us then you can not use sampling frequency higher than 43.5 kHz. Please explain this problem to me.
Author Response
Dear respected reviewer 1,
The authors are grateful and would like to thank you for the comments and suggestions that really helped in modifying the paper. The responses corresponding to the comments and suggestions are attached to a word file.
Thank you for your consideration of this manuscript.
Sincerely,
Ipsita Mishra
Ravi Nath Tripathi
Tsuyoshi Hanamoto
Author Response File: 
Author Response.pdf
Reviewer 2 Report
Submitted manuscript deals with the synchronization analysis for FPGA-based real-time implementation of field oriented control for PMSM. Although there is some level of scientific soundness in the manuscript, I am very sorry to conclude, that in my opinion, the overall quality of the manuscript does not meet the requirements for journal publication. Here are my reasons:
- The reader just do know know what is the problem you are solving in the manuscript. Just to say “the impact of the sampling frequencies is yet not analyzed categorically” is not enough. The problem description should be the result of the literature review. But the literature review has been done to be average (at most) so the detailed problem description is quite missing.
- Almost 50% of the article is dedicated to general description of standard algorithm used in field oriented control (PMSM equations, coordinate transform, speed an current control, etc). These are in general well-known facts for all the experts and the equations are the same regardless of DSP of FPGA implementation. Chapter 2 should be considerably shortened.
Here, it would be much more appropriate to deal in detail specific FPGA implementation issues and requirements and to expand Chapter 3.
- Developed algorithm of time synchronization, presented by authors, is described only in one subchapter 3.2 (total 1,5 page) and it is provided with very few details so it is hard for reader to understand it. I would kindly suggest to expand subchapter 3.2 and provide more details. I would recommend more detailed explanation here. Figure 8 is crucial for understanding, but it is obscure (what is x1 inside the blocks?).
- It is very hard to distinguish between sampling frequency of the speed and current controllers. Was the sampling frequency of the speed controller the same or was it different than the sampling frequency of the current controllers?
- It is not clear if the parameters of the speed PI controller were the same for each experiment. What are the values of the speed PI controller? The sampling time of the speed controller loop has influence on the discretised version of PI controller what can result in different settling times (when changing sampling time in speed control loop). This issue needs to be thoroughly described and explained in the paper.
Author Response
Dear respected reviewer 2,
The authors are grateful and would like to thank you for the comments and suggestions that really helped in modifying the paper. The responses corresponding to the comments and suggestions are attached to a word file.
Thank you for your consideration of this manuscript.
Sincerely,
Ipsita Mishra
Ravi Nath Tripathi
Tsuyoshi Hanamoto
Author Response File: Author Response.pdf
Round 2
Reviewer 1 Report
Thank you for your improvements, but I still found some flaws in your paper.
Line 305: The signal enable1 is triggered after 8,5us, therefore after the signal enable2 ?
Line 314: Figure 9 is very confusing. Please replace Sig.x with proper name - enable, enable1, enable2. Maybe redraw each part of Figure to fit exactly according case (i.e. omit unused signals).
Line 324 and 327: "The sampling time
for the speed control loop and current control loop is consider to be the same for all the cases." And on the line 327 there is a sentence: "However, considering the different sampling frequency ... "
Please add information when PWM compare values are applied.
Line 439: Table VIII: Is the first column really switching frequency of power devices of inverter ? Or it is PWM carrier frequency ? If yours sampling/control loop frequency is higher than PWM carrier frequency and you have immediate update of PWM compare value then real switching can have higher frequency than PWM carrier
Line 454: ... sampling ...
Line 453: ... the effect of the sampling time on the THD is interesting ... Can you please add some opinion why higher sampling frequency improves THD even on low PWM carrier frequency ?
Line 458: You claim that time-synchronization methodology can improve THD but you experimented just with switching frequency and sampling frequency in chapter 4.4.
Author Response
Dear respected reviewer,
The authors are grateful and would like to thank you for the comments and suggestions that really helped in modifying the paper.
The responses corresponding to the comments and suggestions are attached in a word file.
Author Response File: Author Response.pdf
Reviewer 2 Report
149- 51: wrong formatting of equations
336: Fig. 11: y-axe is missing zero value – put it there.
344-345: 5kHz is switching frequency of PWM? If so, please add this information to the sentence.
454: sapling -- > sampling
Conclusion is a little bit confusing. Please, add to the Conclusion some more sentences summarizing the results of your research. Something like following:
“We found that best overall performance has been obtained by (Case I or Case II or Case III) settings with the sampling time XX and switching frequency XX”.
It will help the reader to quickly find and identify best FPGA and drive settings for your case.
Author Response
Dear respected reviewer,
The authors are grateful and would like to thank you for the comments and suggestions that really helped in modifying the paper.
The responses corresponding to the comments and suggestions are enclosed in a word file.
Author Response File: Author Response.pdf
Round 3
Reviewer 1 Report
Line 419: Please add information about which case was used to perform measurements of THD (Case I or II or III).
Line 355: Consider adding information why Case-II and Case-III was not measured with 100kHz sampling frequency.
Author Response
Dear respected reviewer,
The authors are grateful and would like to thank you for the comments and suggestions that really helped in modifying the paper. The changes that are done in the manuscript are attached in a word file.
With best regards,
Ipsita Mishra
Ravi Nath Tripathi
Hanamoto Tsuyoshi
Author Response File: Author Response.pdf
