Energy-Aware Neuromorphic Hardware

A special issue of Journal of Low Power Electronics and Applications (ISSN 2079-9268).

Deadline for manuscript submissions: closed (20 June 2018) | Viewed by 10242

Special Issue Editors

College of Engineering and Computer Science, California State University, Fullerton, CA 90032, USA
Interests: artificial intelligence (AI); embedded hardware; neuromorphic computing; nano-scale computing system with novel silicon and post-silicon devices, and low-power digital and mixed-signal CMOS circuit design
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Guest Editor
Department of Electrical and Computer Engineering, University of Central Florida, Orlando, FL, USA
Interests: computer architecture with emphasis on reconfigurable logic devices, evolvable hardware, and emerging devices
Department of Electronic and Computer Engineering, Ritsumeikan University, Kusatsu, Japan
Interests: processor architecture; high-performance computing; AI-based IoT; underwater drones; cultural heritage preservation and protection
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Guest Editor
College of Computer Science and Electronic Engineering, Hunan University, Changsha 410012, China
Interests: hardware/hardware-assisted security; artificial intelligence security; integrated circuit design; post-quantum cryptographic acceleration
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Special Issue Information

Dear Colleagues,

During recent years, researchers throughout academia and industry have been advancing the theory, operation, and applications of neuromorphic computing systems. Recent interest in neuromorphic computing systems stems from its superior and rapidly advancing performance at tasks such as image recognition, learning of complex intelligent behaviors, and large-scale information retrieval problems such as intelligent web search. However, to attain the benefits of neuromorphic computing, high computational and energy-consumption demands of the underlying processing, interconnect, and memory devices on which software-based neuromorphic computing executes has become an intense focus of government, industry, and academic research. Innovative hardware implementations are sought to attain throughput goals within area, security, and energy constraints for orders of magnitude improvements via innovations across the hardware stack. This Special Issue of the JLPEA is dedicated to advances in all aspects of Energy and Secured-Aware Neuromorphic Hardware. We invite original submissions advancing device, circuits, and hardware architectures of neuromorphic computing systems. Topics of interest include (but are not limited to) the following:

  • (a) Emerging low-power technologies and circuits for neuromorphic computing, including post-CMOS devices;
  • (b) Comparison studies between neuromorphic hardware architectures, spanning use of emerging devices, GPUs, TPUs, ASICs, etc.;
  • (c) Hardware microarchitectures and implementations for neuromorphic computing;
  • (d) Modeling, optimizations, and retraining neuromorphic systems in hardware;
  • (e) Hardware implementations targeting constrained environments, such as edge computing and IoT;
  • (f) Secure neuromorphic applications on FPGAs and ASICs;
  • (g) Applications of neuromorphic-enabled hardware, such as communications systems, big data processing, smart cities, and medical applications;
  • (h) Neuromorphic inspired hardware security.

Dr. Yu Bai
Dr. Ronald F. DeMara
Dr. Meng Lin
Dr. Jiliang Zhang
Guest Editors

Manuscript Submission Information

Manuscripts should be submitted online at www.mdpi.com by registering and logging in to this website. Once you are registered, click here to go to the submission form. Manuscripts can be submitted until the deadline. All submissions that pass pre-check are peer-reviewed. Accepted papers will be published continuously in the journal (as soon as accepted) and will be listed together on the special issue website. Research articles, review articles as well as short communications are invited. For planned papers, a title and short abstract (about 100 words) can be sent to the Editorial Office for announcement on this website.

Submitted manuscripts should not have been published previously, nor be under consideration for publication elsewhere (except conference proceedings papers). All manuscripts are thoroughly refereed through a single-blind peer-review process. A guide for authors and other relevant information for submission of manuscripts is available on the Instructions for Authors page. Journal of Low Power Electronics and Applications is an international peer-reviewed open access quarterly journal published by MDPI.

Please visit the Instructions for Authors page before submitting a manuscript. The Article Processing Charge (APC) for publication in this open access journal is 1800 CHF (Swiss Francs). Submitted papers should be well formatted and use good English. Authors may use MDPI's English editing service prior to publication or during author revisions.

Keywords

  • Low power neuromorphic systems in hardware
  • Post-CMOS device neuromorphic systems
  • Security of neuromorphic systems
  • Applications of Neuromorphic systems in hardware
  • EDA tools and algorithms for neuromorphic systems
  • Neuromorphic inspired hardware security

Published Papers (1 paper)

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Research

27 pages, 1744 KiB  
Article
MB-CNN: Memristive Binary Convolutional Neural Networks for Embedded Mobile Devices
by Arjun Pal Chowdhury, Pranav Kulkarni and Mahdi Nazm Bojnordi
J. Low Power Electron. Appl. 2018, 8(4), 38; https://0-doi-org.brum.beds.ac.uk/10.3390/jlpea8040038 - 13 Oct 2018
Cited by 14 | Viewed by 9826
Abstract
Applications of neural networks have gained significant importance in embedded mobile devices and Internet of Things (IoT) nodes. In particular, convolutional neural networks have emerged as one of the most powerful techniques in computer vision, speech recognition, and AI applications that can improve [...] Read more.
Applications of neural networks have gained significant importance in embedded mobile devices and Internet of Things (IoT) nodes. In particular, convolutional neural networks have emerged as one of the most powerful techniques in computer vision, speech recognition, and AI applications that can improve the mobile user experience. However, satisfying all power and performance requirements of such low power devices is a significant challenge. Recent work has shown that binarizing a neural network can significantly improve the memory requirements of mobile devices at the cost of minor loss in accuracy. This paper proposes MB-CNN, a memristive accelerator for binary convolutional neural networks that perform XNOR convolution in-situ novel 2R memristive data blocks to improve power, performance, and memory requirements of embedded mobile devices. The proposed accelerator achieves at least 13.26 × , 5.91 × , and 3.18 × improvements in the system energy efficiency (computed by energy × delay) over the state-of-the-art software, GPU, and PIM architectures, respectively. The solution architecture which integrates CPU, GPU and MB-CNN outperforms every other configuration in terms of system energy and execution time. Full article
(This article belongs to the Special Issue Energy-Aware Neuromorphic Hardware)
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