Compact Modeling of a 3.3 kV SiC MOSFET Power Module for Detailed Circuit-Level Electrothermal Simulations Including Parasitics

Abstract

In this paper, an advanced electrothermal simulation strategy is applied to a 3.3 kV silicon carbide MOSFET power module. The approach is based on a full circuital representation of the module, where use is made of the thermal equivalent of the Ohm’s law. The individual transistors are described with subcircuits, while the dynamic power-temperature feedback is accounted for through an equivalent thermal network enriched with controlled sources enabling nonlinear thermal effects. A synchronous step-up DC-DC converter and a single-phase inverter, both incorporating the aforementioned power module, are simulated. Good accuracy was ensured by considering electromagnetic effects due to parasitics, which were experimentally extracted in a preliminary stage. Low CPU times are needed, and no convergence issues are encountered in spite of the high switching frequencies. The impact of some key parameters is effortlessly quantified. The analysis witnesses the efficiency and versatility of the approach, and suggests its adoption for design, analysis, and synthesis of high-frequency power converters in wide-band-gap semiconductor technology.

1. Introduction

The power electronics market is driving an exploding increase in demand for high-performance power circuits pervading fields like automotive [1], avionics [2], and renewable energies [3]. An increasing attention is attracted by wide-band-gap power devices, e.g., silicon carbide (SiC) MOSFETs, by virtue of their enhanced ratings in terms of switching speeds and frequencies, as well as higher operational temperature capability, as compared with e.g., silicon (Si) IGBTs [4,5]. In this scenario, most of the designers’ efforts have been oriented to develop advanced packaging techniques to follow the device-level progress [6]. This has led to the successful fabrication of multichip power modules (PMs) based on SiC MOSFETs, an example being presented in [7] for 3.3 kV VDMOS transistors; for this voltage class, the applications of which are the railway traction and wind power conversion, the replacement of Si with SiC is expected to have relevant benefits that allow justifying the higher technology cost. SiC PMs represent a breakthrough with respect to PCB-integrated power circuits [8] and are prone to be incorporated in any kind of converter topology; on the other hand, they require a careful design to efficiently handle (i) the considerable power density dissipated by devices and (ii) their high switching frequency [9]. Consequently, PM designers should pay attention to electrothermal (ET) effects and impact of parasitics [10,11].

In order to investigate the ET behavior of electronic devices/circuits, various approaches have been proposed in literature. Commonly-adopted strategies rely on the coupling of a SPICE-like circuit simulator and a 3-D thermal-only numerical software package (e.g., COMSOL Multiphysics, ANSYS) in a relaxation procedure [12,13,14]; however, this solution is onerous in terms of CPU time and memory storage, as well as prone to convergence problems. TCAD simulation tools (e.g., Sentaurus, ATLAS) allow simultaneously solving the semiconductor and heat flow equations within the same framework [15,16]; the huge computational burden required, however, makes their adoption only suitable for static device-level simulations [17].

As an alternative to methods based on numerical tools, we have developed an in-house approach based on a fully circuital representation of the whole device/circuit for self-consistent static and dynamic ET simulations with SPICE-like programs; considerable efficiency is gained with respect to [12,13,14] since the thermal problem is modeled with an equivalent thermal network derived through an advanced model-order reduction algorithm. The approach has been successfully used for devices/circuits in large variety of technologies, like an IGBT-based boost converter [18], a multicellular SiC power MOSFET operating under harsh conditions [19], and InGaP/GaAs HBT arrays for power amplifiers [20].

In [21], we have applied this advanced simulation strategy also to a 30 kW synchronous step-up DC-DC converter incorporating the 3.3 kV SiC MOSFET PM presented in [7]. Nonlinear thermal effects dictated by the high-power densities were accounted for; moreover, improved accuracy was ensured by the inclusion of parasitics, which were experimentally estimated through an electromagnetic characterization of the assembly. The circuit behavior was successfully described in spite of the high switching frequencies. In the light of the above considerations, this approach has the ambition of proposing itself as a valuable aid in the design flow of SiC-based PMs.

This paper is aimed to extend [21] in a four-fold way: (i) a deeper insight into the PM technology under analysis is presented; (ii) the architecture of the electrical subcircuit modeling the individual VDMOS transistor is explained, with emphasis on the temperature-dependent parameters; (iii) the inclusion of nonlinear thermal effects is thoroughly described; (iv) the suitability of the approach even for AC ET simulations is proven by applying it to a high-power inverter incorporating the PM under investigation.

The remainder of the paper is outlined as follows. In Section 2, the technology for the fabrication of the PM is described. Section 3 probes into the methodology adopted for the ET modeling and experimental characterization of the assembly; more specifically, details about (i) the parasitics extraction, (ii) the SPICE-compatible VDMOS electrical model with temperature-dependent parameters, and (iii) the thermal modeling of the assembly including nonlinear thermal effects are provided. In Section 4, the presented approach is applied to a step-up converter and a single-phase inverter, both embedding the PM under investigation. Simulation times, convergence capability, and suitability to parametric analyses are discussed. Conclusions are then drawn in Section 5.

2. Power Module under Investigation

The general-purpose approach presented in this work is applied to a state-of-the-art PM characterized by two couples of SiC-based VDMOS transistors capable of withstanding up to 3.3 kV/50 A. Although the four devices can be used to realize a full H-bridge, here they are arranged in a half-bridge configuration with a doubled current rating. The assembly—compatible with standard PCB mounting processes [22]—is shown in Figure 1, while its schematic cross-section is represented in Figure 2. Each die is 7.2 × 7.2 mm²-large and 0.4 mm-thick and contains one transistor; the two VDMOS couples lie on two separate 40 × 40 mm²-large and 1.34 mm-thick direct-bonded copper (DBC) substrates. The DBC consists in a sandwich-like structure made of an electrical insulator sheet in between two copper (Cu) foils [23]. Many ceramic materials can in principle be adopted in the DBC manufacturing process. As shown in [23], the choice of the DBC technology has to be based on the application. For the PM under investigation, aluminum nitride (AlN) was chosen by virtue of its relatively high thermal conductivity and electrical resistivity. Concerning the Cu foils, the bottom one is kept plain to ensure a good thermal contact with the 3 mm-thick baseplate underneath (also made of Cu), while the layout of the top one is composed by metal islands in order to realize the circuit topology. The baseplate (i) provides mechanical stability to the assembly and (ii) improves the heat exchange between the devices and the cooling system placed underneath [9]. Electrical interconnections between Cu islands and devices are granted by aluminum (Al) wire bonds. An insulating gel is poured over the entire top surface in order (i) to increase the dielectric integrity and (ii) to avoid undesirable effects such as partial discharge and dielectric breakdown [24]. For the PM under analysis, a 5 mm-high silicon gel produced by Sylgard was considered [25]. Since the module PADs are covered by the insulating gel, Al vertical connectors are required to make them accessible.

3. Methodology

The simulation approach relies on the construction of a SPICE-compatible macrocircuit that models and fully couples the thermal and electrical behaviors of the PM under analysis. Such a macrocircuit also includes experimentally extracted parasitics. The individual VDMOS transistors are described with a behavioral subcircuit, the temperature-sensitive parameters of which are allowed to vary during the simulation run. The power-temperature feedback is accounted for with an equivalent thermal network extracted with low computational burden by means of a model-order reduction technique.

3.1. Parasitics Characterization of the Power Module

A preliminary study was devoted to the electromagnetic characterization of the PM parasitics. It consisted in the experimental evaluation of stray inductances, distributed resistances, and parasitic capacitances by varying frequency. To this aim, a Hioki IM3570 impedance analyzer [26] equipped with Hioki L2000 probes was exploited to measure the total loop parasitic inductance and resistance, as well as the common-mode capacitance. Results are shown in

Table 1. Values of the experimentally extracted parasitics at the frequencies of interest.

	fSW = 32 kHz	fSW = 64 kHz	fSW = 100 kHz
Total loop parasitic resistance	~5.4 mΩ	~5.2 mΩ	~4 mΩ
Total loop parasitic inductance	~130 nH	~30 nH	~120 nH
Common-mode capacitance	~121 pF	~118 pF	~118 pF

, which summarizes the values of the parasitics at the devices switching frequencies (f_SW) of interest for the case-studies investigated in Section 4. It is worth noting that, during the parasitics measurements, the devices were fully-on (V_GS = 20 V) and the total loop parasitic resistance was evaluated by subtracting the devices on-state resistance (~62 mΩ) from the measured value. The parasitic extraction did not take into account the coupling between inductance loops since the PM was designed so as to make such a mutual effect negligible [7].

3.2. Electrical Model of SiC VDMOS Transistors

The compact electrical model adopted in this work for the individual VDMOS, reported in Figure 3, is a variant of the original version presented in [27,28], improved to enjoy higher efficiency and superior convergence properties [29]; these benefits are obtained by mainly using standard SPICE primitives instead of behavioral nonlinear voltage/current sources.

In addition to the three electrical terminals (gate, source, drain) there is an input thermal node ΔT = T − T₀, where T and T₀ are the temperature (assumed uniform) of the VDMOS and a reference temperature equal to 300 K, and an output node carrying the dissipated power P_D.

The basic component is a standard MOSFET instance described with the SPICE LEVEL 3 model, which is used to emulate the channel region. The presented model makes also use of a primitive JFET component aimed at accounting for the nonlinear voltage-dependent resistance of the JFET region of the device. The use of the primitive represents the main improvement with respect to the model shown in our former paper [28], in which a temperature- and bias-dependent resistor was adopted. Replacing such a resistor with a SPICE primitive (i.e., the JFET component) provides better convergence and a more standard modeling platform. The JFET component is placed in series to the drain of the MOS and the gate connected to MOS source. A resistor located on the drain contact (R_EPI) to account for the epilayer ohmic behavior. The anode of the body diode (D_BODY) is connected to the source terminal via a body resistor (R_BODY), while the cathode coincides with the end of the JFET region. Given the very small reverse recovery time of SiC diodes, a standard diode model was used.

The dynamic behavior of the VDMOS is governed by the LEVEL 3 gate-to-source capacitance C_GS, the voltage-dependent junction capacitance C_J of the drain-body diode D_BODY, and the gate-to-drain capacitance C_GD, the V_GD dependence of which is described with [28]

$${\mathrm{C}}_{\mathrm{GD}}({\mathrm{V}}_{\mathrm{GD}})=({\mathrm{C}}_{\mathrm{GD}}{}_0-C_{\mathrm{GDmin}})\left[1+\frac{2}{\mathsf{\pi }}\arctan \left(\frac{{\mathrm{V}}_{\mathrm{GD}}}{{\mathrm{V}}_{\mathrm{GD}}^{*}}\right)\right]+{\mathrm{C}}_{\mathrm{GDmin}}$$

(1)

The temperature dependence of all the relevant parameters is accounted for by using the macromodeling technique, i.e., enriching the standard SPICE elements with controlled sources based on the thermal equivalent of the Ohm’s law (TEOL) [20,27,28,29,30]. The temperature sensitivity of the threshold voltage of both the MOSFET (the channel) and JFET is enabled by connecting a voltage source in series with their gate, which implements the following equation [27]

$${\mathrm{V}}_{\mathrm{T}\mathrm{H}}(\mathrm{T})={\mathrm{V}}_{\mathrm{T}\mathrm{H}}{}_0-{\alpha }_{\mathrm{T}}\cdot \Delta \mathrm{T}$$

(2)

where α_T is a temperature coefficient. Different values of V_TH0 and α_T are associated to the MOSFET and JFET. The linear V_TH dependence on temperature provides fairly accurate results for simulations well within the safe operating area; if a very high temperature rise is expected, a more complex formulation can be enabled [20,28].

The channel mobility temperature dependence is accounted for through a nonlinear current source paralleled to the MOSFET, which implements the following power law [20,27,28]

$${\mathsf{\mu }}_{\mathrm{C}\mathrm{H}}(\mathrm{T})={\mathsf{\mu }}_{\mathrm{C}\mathrm{H}}{}_0{\left(\frac{\mathrm{T}}{{\mathrm{T}}_0}\right)}^{-{\alpha }_{\mathrm{MOSFET}}\left(\mathrm{T}\right)}$$

(3)

where

$${\alpha }_{\mathrm{MOSFET}}\left(\mathrm{T}\right)=-{\mathrm{a}}_{\mathrm{m}}+\left({\mathrm{a}}_{\mathrm{m}}+{\mathrm{b}}_{\mathrm{m}}\right)\left[1-{\mathrm{c}}_{\mathrm{m}}\exp \left(-{\mathrm{d}}_{\mathrm{m}}\frac{\mathrm{T}}{{\mathrm{T}}_0}\right)\right]$$

(4)

a_m, b_m, c_m, d_m being fitting parameters.

A similar strategy is used to model the JFET transconductance (β_JFET), which is allowed to vary according to

$${\mathsf{\beta }}_{\mathrm{JFET}}(\mathrm{T})={\mathsf{\beta }}_{\mathrm{JFET}}{}_0{\left(\frac{\mathrm{T}}{{\mathrm{T}}_0}\right)}^{-{\alpha }_{\mathrm{JFET}}}$$

(5)

α_JFET being a constant power factor, while the R_EPI temperature dependence is included by means of a nonlinear resistor along with a current-controlled voltage source as follows:

$${\mathrm{V}}_{\mathrm{EPI}}(\mathrm{T})={\mathrm{I}}_{\mathrm{MOS}}\cdot {\mathrm{R}}_{\mathrm{EPI}0}{\left(\frac{\mathrm{T}}{{\mathrm{T}}_0}\right)}^{-{\alpha }_{{\mathrm{R}}_{\mathrm{EPI}}}}$$

(6)

Impact ionization current can also be activated following the guidelines reported in [27,28]. To enable the ET feedback, an additional controlled current source was adopted to compute the power dissipated by the device (Figure 3), the value of which being given by the product between the drain current (I_D) and the external drain-source voltage drop (V_DS).

It must be noted that only few nonlinear behavioral sources are used to model the device under investigation when it is working within its safe operating area and in switching circuits. However, the proposed model is suitable to be extended with further controlled voltage and/or current sources in order to account for additional physical phenomena occurring in VDMOS devices. Among the physical effects disregarded in this work, the sub-threshold current and the temperature-dependent breakdown voltage could in principle be modeled according to the approaches shown in [31] and [20], respectively.

The proposed model is scalable and can easily be tuned on VDMOS transistors with different current and/or voltage ratings.

3.3. FANTASTIC-Based Thermal Modeling Including Nonlinear Effects

The power-temperature feedback is implemented by a thermal feedback block (TFB) comprising a linear equivalent network automatically extracted by FANTASTIC [32,33]. Differently from approaches based on Foster-like thermal networks [34], FANTASTIC relies on a model-order reduction technique and it does not require to perform thermal simulations in 3-D FEM software packages; it can be also adopted in multi-source thermal problems, typically making use of matrix-based approaches to account for the thermal coupling between devices [35]. It must be remarked that nonlinear thermal effects play a relevant role in typical applications of SiC devices [36]. While other techniques allow building thermal networks accounting for the temperature dependence of the thermal conductivity [37], in this work a nonlinear correction applied through the Kirchhoff’s transformation [38] was required. By exploiting the TEOL, the TFB can be employed in circuit simulators to enable the ET feedback. More specifically, the power nodes of the transistor subcircuits represent the TFB input currents, while the thermal ones are connected to its output voltages. The resulting macrocircuit (which completely describes the coupled electrical-thermal problem) can be solved by any SPICE-like program (like PSPICE, LTSPICE, Eldo, ADS, SIMetriX) in relatively short times without occurrence of convergence issues; in this work, the SIMetriX framework [39] was exploited.

The linear equivalent network extraction procedure is briefly explained in the following. First, an exceptionally detailed 3-D geometry is created from PM structural data in the finite-element method (FEM) environment of COMSOL Multiphysics [40], as shown in Figure 4; the building process is entirely automated by the in-house routine presented in [41], which relies on the livelink between COMSOL and MATLAB. Then, the domain is discretized into a tetrahedral grid; a smart meshing approach was conceived in order to make the grid finer in the surroundings of the dies (Figure 4). The mesh is in turn fed to FANTASTIC, which automatically builds a reduced-order model and extracts the corresponding equivalent network. Such a network associates the powers P_D dissipated by the heat sources of the four VDMOS devices (inputs) to their temperature rises ΔT_lin averaged on the channel regions located on the top surface (outputs) under linear thermal conditions.

The thermal problem was set as follows. Four heat sources (one for each device) were considered to coincide with the active region of the transistors located on the top surface of the dies. Adiabatic boundary conditions were defined on all external surfaces except for the bottom baseplate one, on which a convective heat transfer coefficient h = 3 × 10⁶ W/m²K was chosen to emulate the presence of a thermochuck (cold plate) [9]; it must be remarked that any h value can in principle be adopted to model the effect of different cooling solutions.

Nonlinear thermal effects are accounted for by means of the Kirchhoff’s transformation [34]

$$\Delta \mathrm{T}={\mathrm{T}}_0\cdot {\left[{\mathrm{m}}_{\mathrm{k}}+\left(1-{\mathrm{m}}_{\mathrm{k}}\right)\cdot \frac{\Delta {\mathrm{T}}_{\mathrm{lin}}+{\mathrm{T}}_0}{{\mathrm{T}}_0}\right]}^{\frac{1}{1-{\mathrm{m}}_{\mathrm{k}}}}-{\mathrm{T}}_0$$

(7)

where ΔT represents the nonlinear-corrected temperature increment and m_k is a fitting parameter, strongly depending on (i) the geometry and materials of the assembly and (ii) the boundary conditions of the thermal problem. The calibration of m_k was made through the following procedure. First, the self-heating thermal resistance (R_TH) of an individual VDMOS transistor under linear conditions was evaluated in COMSOL as ΔT_lin/P_D. The temperature dependence of the thermal conductivities was then activated, and many COMSOL simulations were carried out with P_D logarithmically spanning the wide 1.8–1800 W range; hence, the nonlinear temperature rise averaged on the channel region was obtained as a function of P_D. As a final step, parameter m_k was calibrated through a least-squares algorithm to achieve the best agreement between the temperature rises ΔT obtained through Equation (7) from ΔT_lin = R_TH × P_D and those simulated by COMSOL under nonlinear conditions. Figure 5 shows the results of the fitting procedure, which demonstrate that the choice of the parameter m_k = 0.9443 allows achieving an excellent agreement over a broad range of ΔT values (0–700 K).

4. Results

4.1. Case-Study #1: DC-DC Step-Up Converter

As a first case-study, the proposed simulation approach was applied to a 30 kW synchronous step-up DC-DC converter including the PM under analysis. Figure 6 illustrates the schematic with emphasis on device subcircuits and parasitics. The connections are designed to realize the circuit configuration with two parallel devices at the high side (HS) and two parallel devices at the low side (LS); the gate signals V_G and V_G’ were generated to control the LS and HS devices, respectively. A switching frequency f_SW = 100 kHz was considered. A sketch of the TFB is depicted in Figure 7.

Table 2. Values of the DC-DC converter circuit parameters adopted in SIMetriX.

Parameter	Value
VIN	800 V
Rgen	0.1 Ω
L1	5 mH
RL1	0.1 Ω
POUT	29 kW
RG	4 Ω
COUT	10 µF
ROUT	120 Ω
Lσ	30 nH
Rσ	4 mΩ
LWB	1 nH
CM	118 pF
fSW	100 kHz
TON	5.5 µs

summarizes the circuit parameters adopted in the ET simulations, chosen so as to respect the specifications on the output power. The parasitics were accounted for through the lumped elements R_σ, L_σ, and C_M, the values of which at f_SW = 100 kHz were obtained by elaborating the experimentally extracted total loop parasitic inductance and resistance, and common-mode capacitance shown in Table 1.

The efficiency of the step-up converter was computed to be η = 94.35% by elaborating the ET simulation results. Figure 8 shows the P_D values of the four devices at the limit cycle, while their operating temperatures averaged on the channel regions are reported in Figure 9. The circuit configuration makes the LS devices dissipate much more power with respect to the HS ones, which results in a significant temperature difference between them (Figure 9). The small temperature ripple (~1%) is due to the slow thermal dynamic behavior induced by the large thermal capacitance associated with the thick Cu baseplate. After the dynamic ET simulation run, FANTASTIC, aided by a code to account for the Kirchhoff’s transformation, enables the reconstruction of the whole spatial temperature field in the PM at chosen time instants with negligible computational cost (e.g., [20]). This is a key option offered to designers, as the inspection of selected thermal maps represents a valuable support to estimate the PM reliability. Figure 10 depicts the PM temperature field extracted at t = 800 ms; an interesting finding it that the maximum temperature of the LS devices (~190 °C) is ~30 °C higher than the average one (Figure 9).

As proof of the suitability of the proposed approach in parametric analyses, additional exemplificative simulations were performed to quantify the converter performances by modifying circuit parameters. To this aim, the gate resistance R_G and the switching frequency f_SW were varied in the ranges 2–6 Ω and 90–105 kHz, respectively. While the R_G range was chosen according to values typically adopted for SiC-based VDMOS, f_SW values were selected in a narrow range to ensure the circuit working in continuous current mode given the passive components values (i.e., L₁ = 5 mH and C_OUT = 10 µF); in principle, any value of f_SW and R_G can be adopted. As a figure of merit of the circuit, η was evaluated and reported in

Table 3. Outcome of the parametric analysis conducted on the DC-DC converter: the efficiency (η) evaluated at different R_G and f_SW values.

RG	2 Ω	4 Ω	6 Ω
η	95.17%	94.35%	93.55%
fSW	105 kHz	100 kHz	90 kHz
η	93.49%	94.35%	95.59%

, while Figure 9 also shows the lower temperatures of the LS transistors obtained by reducing the gate resistance R_G from 4 Ω down to 2 Ω.

The main findings can be summarized as follows:

• higher R_G values increase η; however, designers should also consider the detrimental effects on di/dt.
• by reducing f_SW, the losses due to the reactive components and PM parasitics are mitigated, thus leading to higher η values.

The six simulations performed for this analysis allowed offering further evidence of the excellent convergence properties and the low CPU time requirements (~2 h for a time window of 800 ms on a PC equipped by a single i7-4710HQ CPU and a 16 GB RAM).

4.2. Case-Study #2: Single-Phase Inverter

ET simulations of a single-phase inverter were also performed; the approach was applied to the macrocircuit schematically depicted in Figure 11. The 50 Hz-400 V RMS inverter was designed to achieve a high efficiency value (~92%) providing a P_LOAD = 4.5 kW RMS to R_LOAD; such electrical rates respect European AC standards and are compatible with wind- and solar-energy conversion [42,43]. Furthermore, the circuit can be easily modified into a double-pulse tester, which is widely adopted in parametric switching characterization of transistors [44]. The circuit required the use of an inverter control unit (ICU). As the load current is detected by means of a current sensing, the ICU generates ad-hoc voltage signals (V_{G_LS} and V_{G_HS}) to be fed to the gate drivers of the transistors. The control is based on a duty-cycle modulation technique. While the SIMetriX macrocircuit includes the same lumped parasitic components used for the DC-DC converter simulations, their values were varied according to f_SW (i.e., 64 kHz for the case study). Concerning the power-temperature feedback, the same approach shown in Section 4.1 was adopted (Figure 7). The parameters used in the inverter simulations are summarized in

Table 4. Values of the inverter parameters adopted in SIMetriX.

Parameter	Value
VDC	1800 V
LLOAD	5.8 mH
RLOAD	40 Ω
POUT,RMS	4.5 kW
RG	2 Ω
Lσ	7.5 nH
Rσ	5.2 mΩ
LWB	1 nH
CM	118 pF
fSW	64 kHz

.

An ET simulation of 1 s required ~1 h on a standard PC. The efficiency of the inverter was evaluated to be η = 91.39%. The current and voltage waveforms on the resistive load are shown in Figure 12 over a 20 ms-wide time window at the limit cycle. The duty-cycle modulation technique leads the HS (LS) devices to dissipate more power in the first (second) half of the period. This is also confirmed by Figure 13 and Figure 14, which depict the average temperature of the HS and LS devices, respectively. It must be underlined that (i) the high efficiency, (ii) the good boundary conditions applied to the bottom of the Cu baseplate, and (iii) the high R_LOAD value contribute to achieve low temperature increments (~30 °C) with respect to T₀. As a main difference with the DC-DC converter, in which the LS devices turned out to be hotter than the HS ones, here the device temperatures are more evenly distributed. Again, the post-processing feature of FANTASTIC was exploited to extract the nonlinear-corrected temperature maps on the PM at the time instants t = 987.0 ms (Figure 15a) and t = 996.5 ms (Figure 15b).

As a last analysis, a parametric investigation (similar to the one carried out on the DC-DC converter) was conducted on the single-phase inverter.

Table 5. Outcome of the parametric analysis conducted on the inverter: efficiency (η) evaluated at different R_G and f_SW values.

η	RG = 2 Ω	RG = 4.7 Ω
fSW = 32 kHz	95.32%	92.88%
fSW = 64 kHz	91.39%	87.32%

shows the inverter efficiency η as a function of f_SW and R_G. The influence of such parameters was evaluated in a fast, yet trustworthy, simulation session that lasted ~4 h and proved the suitability of the approach even in parametric analyses of AC circuits.

5. Conclusions

An efficient and versatile strategy for fast and accurate dynamic electrothermal simulations has been applied to a state-of-the-art multichip power module including four 3.3 kV SiC VDMOS transistors arranged in a half-bridge configuration. The approach relies on a fully circuital representation of the whole module based on the thermal equivalent of the Ohm’s law. The individual devices are described with subcircuits implementing a behavioral model, the temperature-sensitive parameters of which are allowed to vary during the simulation run. The power-temperature feedback is included with an equivalent thermal network automatically extracted by FANTASTIC with an advanced model-order reduction technique applied to a 3-D COMSOL mesh representing a very accurate replica of the real module; such a network is in turn equipped with a numerically calibrated Kirchhoff’s transformation to account for nonlinear thermal effects.

The strategy has been exploited to simulate a synchronous step-up DC-DC converter and a single-phase inverter embedding the aforementioned power module. In both cases, circuit parasitics have been included, the values of which were calibrated on the basis of the total loop parasitic resistance/inductance and common-mode parasitic capacitance experimentally extracted in a preliminary stage. The SIMetriX software has been selected to perform electrothermal simulations of the converter and inverter macrocircuits, although any other SPICE-like circuit software packages could in principle be used. Despite the complexity of the problem, the high switching frequency, the high temperatures reached, and the long-time range analyzed, the simulations have been carried out in a relatively short time on a standard PC without convergence issues; more specifically, 1 h and 2 h were required to perform the 800 ms-long DC-DC converter and 1 s-long AC inverter ET simulations, respectively. This allowed for effortlessly conducting an illustrative study on the impact of key parameters on the circuits performance (i.e., in terms of efficiency). The analysis has shown that the proposed approach can be fruitfully used for the analysis and design of power conversion architectures in strategic domains of societal infrastructure, such as railway traction and renewable energy conversion.