Neutral-Point Voltage Balancing Method for Three-Phase Three-Level Dual-Active-Bridge Converters

Abstract

Three-phase three-level dual-active-bridge (3L-DAB3) converters are a potential topology for high-voltage and high-power applications. Neutral-point voltage balancing is a complex and important issue for three-level (3L) circuits. Compared with the single-phase 3L dual-active-bridge converter, the self-balancing capability of the 3L-DAB3 is limited. To guarantee the reliability of the converter, a neutral-point voltage balancing method for the 3L-DAB3 is proposed in this paper. First, the neutral-point voltage balancing principle of the 3L-DAB3 is analyzed. Then, the relationship between the duty ratio adjustment and injected neutral-point charge is described. In order to guarantee accurate neutral-point voltage balance, the proposed balancing method adopts a sign-hysteresis control with a dead zone. The dead zone is responsible for whether the duty ratio adjustment is activated, and the sign-hysteresis control guarantees a correct adjustment direction. The proposed neutral-point voltage balancing method only needs to sample the capacitor voltages, thus avoiding a complex parameter design and making it easy to implement. The transmission power of the converter is not affected during the adjustment process. The proposed balancing method has a rapid response speed and does not have problems with respect to stability. Finally, experiments were conducted on a 3.6 kW laboratory prototype. The validity and performance of the proposed neutral-point voltage balancing method were verified on the basis of the simulation and experimental results.

1. Introduction

Isolated DC–DC converters have been widely used in high-power applications, such as solid-state transformers, hybrid electric vehicles, energy storage systems and DC distribution systems [1,2,3,4,5]. Most of these applications require a bidirectional power flow, a high efficiency, and a high-power density. As a promising isolated DC–DC converter topology, the dual-active-bridge (DAB) converter has been extensively used in recent years due to its easy realization of soft-switching, electrical isolation, and its modular and symmetric structure [6,7,8].

Compared with the conventional single-phase DAB (DAB1), the three-phase DAB (DAB3), first proposed in [9], exhibits advantages of a reduced filter volume, a higher efficiency, and a higher power density [10,11,12,13,14,15]. Therefore, the DAB3 is suitable for high-power applications. Phase shift control is the most common modulation strategy for the two-level DAB3. Under symmetric modulation, the duty ratios of the two bridges are fixed at 50%, and the phase shift between the primary and secondary sides is the only control degree of freedom. However, it is easy to lose zero-voltage switching (ZVS) at light-load or non-unity voltage ratios. To extend the ZVS range and improve the light-load efficiency, many optimization strategies have been proposed, such as negative-sequence modulation [16], asymmetrical duty-cycle control [17,18], single-phase operation [19], and simultaneous pulse-width modulation control [20].

Introducing three-level (3L) circuits into the DAB3 is a possible way of improving their performance. The three-phase three-level DAB (3L-DAB3) converter, introduced in [21,22], is able to provide a wide ZVS range with symmetrical voltage and current waveforms, and has three control degrees of freedom for the optimization of its performance [23,24]. Additionally, the 3L-DAB3 makes it possible to use lower voltage-rated power devices with better performance features, and reduces switching and conduction losses [25].

The neutral-point voltage balancing of 3L circuits is a complex and important issue [26,27]. The offset of neutral-point voltage leads to overvoltage on a portion of the switches, which affects the reliability of the converter. The 3L half-bridge DAB1 (3LHB-DAB1) has a strong neutral-point voltage self-balancing capability, and thus the neutral-point voltage balancing algorithm is not required. In the 3L full-bridge DAB1 (3LFB-DAB1), neutral-point voltage balancing can be realized by introducing an additional LC branch [28], alternately using complementary switching modes [29], or adjusting the duty ratio of the switching state [30,31].

However, the 3L-DAB3 cannot be regarded as a simple superposition of three 3LHB-DAB1. It has a specific neutral-point voltage balancing principle, which is different from that of the DAB1. The existing neutral-point voltage balancing methods for the DAB1 cannot be directly applied. An active neutral-point voltage control was discussed for the 3L-DAB3 in bipolar operation in [32], but the lookup tables that were used are complicated. The active control lacks the necessary theoretical analysis of the neutral-point voltage balancing principle of the 3L-DAB3. Moreover, it is only applicable in a specific operating mode, with all operating modes of the converter not having been verified. To date, the theoretical analysis of the neutral-point voltage offset and the balancing principle of the 3L-DAB3 have not been described in the existing research. Therefore, a practical neutral-point voltage balancing method for all 3L-DAB3 operating conditions is needed.

This paper focuses on the neutral-point voltage balancing principle and proposes a neutral-point voltage balancing method for the 3L-DAB3. First, the effective charging intervals of neutral points are indicated in all operating modes. The inner duty ratio is the main factor of the charging intervals, and it can be modulated. Then, with the adjustment of the duty ratio, it is possible to derive the introduced neutral-point charge. The relationship between the sign of the duty ratio adjustment and the sign of the introduced neutral-point charge is clear, and it provides theoretical support for the design of the hysteresis control. The sign-hysteresis control can be used to guarantee that the correct direction of adjustment is employed, and a dead zone is additionally applied to control the neutral-point voltage to within the region close to the balanced value, avoiding changes in the duty ratio during each switching period. Finally, the neutral-point voltage balancing method, consisting of the sign-hysteresis control with a dead zone, is obtained to maintain the neutral-point voltage balancing of the 3L-DAB3. More importantly, the theoretical analysis and proposed method of the neutral-point voltage balancing is applicable to all 3L-DAB3.

The rest of this paper is organized as follows. In Section 2, the topology and operating principle of the 3L-DAB3 are introduced. In Section 3, the neutral-point voltage balancing principle is presented. In Section 4, the control principle of the neutral-point voltage balancing is described, and a balancing method consisting of a sign-hysteresis control with a dead zone is proposed. Simulation and experimental verifications, performed using a 3.6 kW laboratory prototype, are provided in Section 5, and conclusions are drawn in Section 6.

2. Topology and Operating Principle of the 3L-DAB3

2.1. Topology of the 3L-DAB3

The circuit schematic of the 3L-DAB3 was introduced in [21,22]. Figure 1 shows the circuit schematic of the 3L-DAB3 that is discussed in this paper, in which two three-phase active neutral-point-clamped (ANPC) bridges are connected by a three-phase high-frequency transformer. According to the winding configuration of the three-phase transformer, the 3L-DAB3 has four magnetic structure types, with Y-Y, Y-∆, ∆-Y, and ∆-∆ configurations. Compared with the other types, the Y-Y winding configuration is able to effectively reduce the unbalanced phase current of the three-phase transformer and prevent high circulating currents under no-load conditions [33]. Therefore, in this paper, a 3L-DAB3 with a Y-Y winding configuration is discussed.

The three 3L ANPC bridges on the primary side are denoted as B_A1, B_B1, and B_C1, and the three bridges on the secondary side are denoted as B_A2, B_B2, and B_C2. The six switches of the 3L ANPC bridges are denoted as S_ij1–S_ij6, where the subscript i (i = A, B, C) represents the phases A, B, and C, and the subscript j (j = 1, 2) represents the primary side and the secondary side, respectively. The output terminals of the three-phase 3L ANPC bridges are denoted as A_j, B_j, and C_j, respectively. The V_P and V_S are the DC voltages. The C_P1, C_P2, C_S1, and C_S2 are the filter capacitors on the DC side, and the capacitor voltages are v_CP1, v_CP2, v_CS2, and v_CS2 and satisfy the constraints v_CP1 + v_CP2 = V_P and v_CS1 + v_CS2 = V_S. The equivalent inductor L_i includes the transformer leakage inductor and the external series inductor. The phase current that flows through L_i is denoted as i_Li, and the terminal voltages of L_i are denoted as v_Lij. The three-phase high-frequency transformer T has a turns-ratio of n_k:1, and thus the voltage conversion ratio k of the converter is expressed as n_kV_S/V_P. The voltage drop across L_i is denoted as v_Li and is equal to v_Li1 − n_kv_Li2. The neutral points of two active bridges and the Y-Y winding are O₁ and O₂ and m₁ and m₂, respectively.

The equivalent circuit of the 3L-DAB3 is presented in Figure 2. The active bridges are equivalent to step-wave AC voltage sources with a Y configuration, connected through the series inductors. In the 3L-DAB3, the three 3L ANPC bridges on each side are modulated with a phase shift of 2π/3. Under the assumption that the parameters of each phase are symmetric, phase A is taken as an example for analysis in this paper.

2.2. Operating Principle of the 3L-DAB3

Each 3L ANPC bridge can output three voltage levels, V_dc/2, 0, and −V_dc/2 (V_dc is the DC-bus voltage), denoted as the P, O, and N states, respectively. The switching strategy for 3L ANPC bridges that is proposed in [34] is used in this paper to improve the performance.

In Figure 3a, the durations of the P and N states in v_i1O1 are the same, and they are modulated as d₁T_hs. d₁ is the inner duty ratio of the primary side and satisfies the constraint 0 ≤ d₁ ≤ 1. T_hs is half of the switching period, and T_s is the switching period. The switching frequency is denoted as f_s, and ω is the angular frequency. The v_LA1 is obtained, and has one control degree of freedom, d₁. On the secondary side, the v_LA2 can be generated in the same way, with one control degree of freedom, d₂, which is the inner duty ratio of the secondary side and satisfies the constraint 0 ≤ d₂ ≤ 1. For the power transmission of the 3L-DAB3, the outer duty ratio d is added into the modulation to form a phase shift between v_LA1 and v_LA2, as shown in Figure 3b.

The v_m1O1 and v_m2O2 are the neutral-point voltages of m₁ and m₂ and they refer to O₁ and O₂, respectively [35], which are given by (1). The v_AjOj, v_BjOj, and v_CjOj are the AC side voltages of the 3L ANPC bridge B_Aj, B_Bj, and B_Cj refer to O_j, respectively. The primary and secondary terminal voltages v_Lij of the inductor L_i are expressed by (2).

$$\begin{array}{cc}{v}_{\mathrm{mjOj}}=\frac{1}{3}\left(v_{\mathrm{A}\mathrm{j}\mathrm{O}\mathrm{j}}+v_{\mathrm{B}\mathrm{j}\mathrm{O}\mathrm{j}}+v_{\mathrm{C}\mathrm{j}\mathrm{O}\mathrm{j}}\right)& \mathrm{j}=1,2\end{array}$$

(1)

$$\begin{array}{cc}\{\begin{array}{c}{v}_{\mathrm{LAj}}=\frac{1}{3}\left(2v_{\mathrm{A}\mathrm{j}\mathrm{O}\mathrm{j}}-v_{\mathrm{B}\mathrm{j}\mathrm{O}\mathrm{j}}-v_{\mathrm{C}\mathrm{j}\mathrm{O}\mathrm{j}}\right)\\ v_{\mathrm{LBj}}=\frac{1}{3}\left(2v_{\mathrm{B}\mathrm{j}\mathrm{O}\mathrm{j}}-v_{\mathrm{A}\mathrm{j}\mathrm{O}\mathrm{j}}-v_{\mathrm{C}\mathrm{j}\mathrm{O}\mathrm{j}}\right)\\ v_{\mathrm{LCj}}=\frac{1}{3}\left(2v_{\mathrm{C}\mathrm{j}\mathrm{O}\mathrm{j}}-v_{\mathrm{Aj}\mathrm{O}\mathrm{j}}-v_{\mathrm{B}\mathrm{j}\mathrm{O}\mathrm{j}}\right)\end{array}& \mathrm{j}=1,2\end{array}$$

(2)

It can be observed that the AC-side voltages of the 3L ANPC bridges are coupled under the Y-Y winding configuration. According to the ranges of d_j, v_mjOj has three operating modes, as shown in Figure 4.

(1)

Mode 1: The inner duty ratio d_j satisfies the constraint 0 ≤ d_j ≤ 1/3. The durations of the P and N states in v_mjOj are the same, and they are controlled as d_jT_hs; the voltage levels and steps of v_LAj are illustrated in Figure 4a.

(2)

Mode 2: The inner duty ratio d_j satisfies the constraint 1/3 < d_j ≤ 2/3. The durations of the P and N states in v_mjOj are the same, and they are controlled as (2/3 − d_j)T_hs; the voltage levels and steps of v_LAj are illustrated in Figure 4b.

(3)

Mode 3: The inner duty ratio d_j satisfies the constraint 2/3 < d_j ≤ 1. The durations of the P and N states in v_mjOj are the same, and they are controlled as (d_j − 2/3)T_hs; the voltage levels and steps of v_LAj are illustrated in Figure 4c.

According to Figure 3 and Figure 4, the time-domain analysis is complex in 3L-DAB3 due to the large number of voltage levels and steps. However, the phase voltages and currents are near sinusoidal in the 3L-DAB3, which makes it suitable for analysis on the basis of the fundamental harmonic approximation (FHA) method [36]. The v_A1O1 presents the odd and half-wave symmetry, and these can be transformed into (3) on the basis of the Fourier series, where the odd harmonic number n satisfies n = 1, 3, 5, 7, …

$$\begin{array}{cc}{v}_{\mathrm{A}1\mathrm{O}1}\left(t\right)={\displaystyle \sum _{n=1}^{+\infty }\frac{2V_{\mathrm{P}}}{n\pi }\sin \left(n\pi \cdot 0.5d_1\right)\cos \left(n\omega t\right)}& n=1,3,5,7,\dots \end{array}$$

(3)

According to (2), v_LA1 can be obtained and expressed by (4). Considering that the 3n^th harmonic is eliminated under the Y-Y winding configuration, the odd harmonic number n satisfies n = 1, 5, 7, 11, … in (4). Similarly, v_LA2 is expressed by (5).

$$\begin{array}{cc}{v}_{\mathrm{L}A1}\left(t\right)={\displaystyle \sum _{n=1}^{+\infty }\frac{2V_{\mathrm{P}}}{n\pi }\sin \left(n\pi \cdot 0.5d_1\right)\cos \left(n\omega t\right)}& n=1,5,7,11,\dots \end{array}$$

(4)

$$\begin{array}{cc}{v}_{\mathrm{L}A2}\left(t\right)={\displaystyle \sum _{n=1}^{+\infty }\frac{2V_{\mathrm{S}}}{n\pi }\sin \left(n\pi \cdot 0.5d_2\right)\cos \left[n\omega \left(t-d{T}_{\mathrm{hs}}\right)\right]}& n=1,5,7,11,\dots \end{array}$$

(5)

The phase current i_LA in Figure 3b can be calculated using (6), where λ denotes the time within a switching period. Due to the half-wave symmetry, i_LA(0) can be calculated. Then, substituting i_LA(0) into (6), the phase current i_LA is obtained, which can be expressed as shown in (7).

$$i_{\mathrm{LA}}\left(t\right)=i_{\mathrm{LA}}\left(0\right)+\frac{1}{L}{\displaystyle {\int }_0^t\left[v_{\mathrm{LA}1}\left(\lambda \right)-n_{\mathrm{k}}{v}_{\mathrm{LA}2}\left(\lambda \right)\right]}d\lambda$$

(6)

$$\begin{array}{c}{i}_{\mathrm{LA}}\left(t\right)={\displaystyle \sum _{n=1}^{+\infty }\frac{2V_{\mathrm{P}}}{n\pi }\sin \left(n\pi \cdot 0.5d_1\right)\sin \left(n\omega t\right)}\\ \hspace{1em}\hspace{1em}\hspace{1em}\hspace{1em}\hspace{1em}\hspace{1em}\hspace{1em}-{\displaystyle \sum _{n=1}^{+\infty }\frac{2n_{\mathrm{k}}{V}_{\mathrm{S}}}{n\pi }}\sin \left(n\pi \cdot 0.5d_2\right)\sin \left[n\omega \left(t-d{T}_{\mathrm{hs}}\right)\right]\end{array}$$

(7)

Only taking the fundamental component (n = 1) into account, the fundamental component v_A1O1,1 can be expressed as in (8), and i_LA,1 can be derived using (9).

$$v_{\mathrm{A}1\mathrm{O}1,1}\left(t\right)=\frac{2V_{\mathrm{P}}}{\pi }\sin \left(\pi \cdot 0.5d_1\right)\cos \left(\omega t\right)$$

(8)

$$i_{\mathrm{LA},1}\left(t\right)=\frac{2V_{\mathrm{P}}}{\pi }\left\{\sin \left(\pi \cdot 0.5d_1\right)\sin \left(\omega t\right)-k\sin \left(\pi \cdot 0.5d_2\right)\sin \left[\omega \left(t-d{T}_{\mathrm{hs}}\right)\right]\right\}$$

(9)

Further, the active transmission power P and the reactive transmission power Q of the 3L-DAB3 can be calculated using (10) and (11), respectively [20,36].

$$P=3P_{\mathrm{A}}=\frac{3k{V}_{\mathrm{P}}^2}{{\pi }^3{f}_{\mathrm{s}}L}\sin \left(\pi \cdot 0.5d_1\right)\sin \left(\pi \cdot 0.5d_2\right)\sin \left(\pi d\right)$$

(10)

$$Q=3Q_{\mathrm{A}}=\frac{3k{V}_{\mathrm{P}}^2}{{\pi }^3{f}_{\mathrm{s}}L}\sin \left(\pi \cdot 0.5d_1\right)\sin \left(\pi \cdot 0.5d_2\right)\left[\cos \left(\pi d\right)-k\right]$$

(11)

3. Neutral-Point Voltage Balancing Principle

The neutral-point voltage is affected by the flow direction of the neutral-point instantaneous current i_NPj. The current that is being drawn from the neutral point is defined as i_NPj > 0, which is discharged at the neutral point O_j. Thus, the neutral-point potential decreases. Otherwise, i_NPj charges the neutral point O_j, and the neutral-point potential increases when i_NPj < 0. Therefore, the neutral-point average current I_NPj reflects the total charge that is injected into or drawn from the neutral point O_j in a given switching period. In order to maintain the neutral-point voltage balance, it is necessary to guarantee I_NPj = 0 within a switching period.

3.1. Neutral-Point Voltage Self-Balancing of the 3LHB-DAB1

The current paths under the P and N states for the 3LHB-DAB1 are shown in Figure 5. The phase current that is drawn from the output terminal A₁ is defined as i_LA > 0. Since i_LA flows directly back to the neutral point O₁ through the primary winding of the transformer, i_NP1 = −i_LA. The neutral point instantaneous current i_NP1 in the 3L-DAB3 can be expressed as shown in (12), where d_m is the duration ratio of the P or N state, and the subscript m (m = P, N) represents the P and N states, respectively. Under normal operation, the durations of the P and N states are equal, and therefore d_P = d_N. With the half-wave symmetry of i_LA, I_NP1 = 0. The neutral-point voltage remains balanced.

$$i_{\mathrm{NP}1}={\displaystyle \sum _{\mathrm{m}=\mathrm{P},\mathrm{N}}{d}_{\mathrm{m}}\cdot \left(-i_{\mathrm{Li}}\right)}$$

(12)

Assuming that v_CP2 is lower than V_dc/2, the forward DC bias is generated in the primary winding of the transformer and the current i_LA. According to (12), I_NP1 < 0. Since i_LA flows directly back to the O₁ in the 3LHB-DAB1, the neutral point is charged directly and increases back to the balanced value, eliminating the forward DC bias. Therefore, the 3LHB-DAB1 has a strong neutral-point voltage self-balancing capability.

However, the 3L-DAB3 cannot be seen as a simple superposition of three 3LHB-DAB1, and neutral-point voltage balancing cannot be treated in the same way. Under the Y-Y winding configuration, i_Li does not flow directly back to the neutral point O_j, as shown in Figure 1. It is difficult to maintain neutral-point voltage self-balancing. Therefore, it is necessary to analyze the neutral-point balancing principle and propose a neutral-point voltage balancing method for the 3L-DAB3. The neutral point O₁ of the primary side is taken as an example that will be analyzed in the following sections.

3.2. Neutral-Point Balancing Principle of the 3L-DAB3

Similar to the 3L three-phase inverter [37], the neutral-point instantaneous current i_NP1 in the 3L-DAB3 can be expressed as shown in (13). Unless any one or two of the v_i1O1 output the O state, the corresponding current i_Li will not affect the neutral point O₁. The v_m1O1 has three operating modes, so i_NP1 also has three charging and discharging modes, as shown in Figure 6.

$$i_{\mathrm{NP}1}={\displaystyle \sum _{\mathrm{i}=\mathrm{A},\mathrm{B},\mathrm{C}}\left[1-abs\left(v_{\mathrm{i}1\mathrm{O}1}\right)\right]\cdot i_{\mathrm{Li}}}$$

(13)

The neutral-point current charging and discharging principles for the different modes can be described as follows:

(1)

Mode 1: When one bridge outputs the P or N state, i_Li charges the neutral point O₁ in the six yellow operating intervals, as shown in the shaded areas in Figure 6a. In these six intervals, i_NP1 = −i_Li. In the other six intervals, three 3L ANPC bridges output the O states and i_NP1 = i_LA + i_LB + i_LC = 0, which does not charge the neutral point O₁. As an example, the current paths in Interval 1 of phase A are shown in Figure 7a.

(2)

Mode 2: The i_NP1 in 12 operating intervals charges the neutral point O₁, as shown in the shaded areas in Figure 6b. Generally, there are two different cases: in Intervals 2, 4, 6, 8, 10, and 12, i_NP1 = −i_Li; in Intervals 1, 3, 5, 7, 9, and 11, i_NP1 = i_Li. As an example, the current paths in Interval 8 of phase A are shown in Figure 7b.

(3)

Mode 3: When one bridge outputs the O state, i_NP1 charges the neutral point O₁ in the six yellow operating intervals, as shown in the shaded areas in Figure 6c. In these six intervals, i_NP1 = i_Li. In the other six intervals, three 3L ANPC bridges output the P or N states, i_NP1 = 0, which does not charge the neutral point O₁. As an example, the current paths in Interval 3 of phase A are shown are Figure 7c.

Figure 7. Current path diagram of the neutral-point current charging and discharging intervals. (a) Interval 1 of Mode 1; (b) Interval 8 of Mode 2; (c) Interval 3 of Mode 3.

Figure 7. Current path diagram of the neutral-point current charging and discharging intervals. (a) Interval 1 of Mode 1; (b) Interval 8 of Mode 2; (c) Interval 3 of Mode 3.

In Mode 1, assuming that v_CP2 is lower than V_dc/2, the neutral-point charge generated by i_LA in Intervals 1 and 4 is positive within a switching period, and it is same as that of the bridges B_B1 and B_C1. Therefore, the total charge that is injected into the neutral point O₁ is positive, and therefore it charges the O₁. The v_CP2 increases to close to V_dc/2, and the neutral-point voltage tends to be self-balancing. In other operating modes, the self-balancing of the 3L-DAB3 is also valid, using the same means of analysis. The simulation waveforms of the capacitor voltages are illustrated in Figure 8. The neutral-point voltages of both sides exhibit this self-balancing trend, as shown in Figure 8a. However, the voltage oscillations over a long time are not acceptable, and they would lead to damage to the 3L-DAB3.

In practical systems, there are several factors that may affect neutral-point voltage balancing, such as asymmetric hardware parameters, and small differences in driving circuits and power devices, which cannot be avoided. On the other hand, the actual drive waveforms of switches include the dead time. Therefore, even if the dead time is considered, the charging intervals of the neutral points remain symmetric. The total neutral-point charge is zero within a switching period. The dead time of the switches does not affect the neutral-point voltage balancing or its control principle for the 3L-DAB3. Combined with the above analysis, when the durations of the P and N states are unequal, I_NPj ≠ 0, the neutral-point voltages will deviate from the balanced voltages, as shown in Figure 8b. Permanent neutral-point voltage imbalance would occur in such scenarios and it could even result in power devices in the converter being destroyed. Therefore, it is necessary to propose a neutral-point voltage balancing method that guarantees the reliability of the 3L-DAB3.

4. Neutral-Point Voltage Balancing Method

4.1. Control Principle of the Neutral-Point Voltage Balancing Method

When the offset of the neutral-point voltage appears, one intuitive method for restoring balance is to adjust the duty ratio while not introducing a DC bias into the transformer. That is, when a voltage imbalance appears, the inner duty ratio d_j should be modified to d_j + Δd_j, introducing a nonzero charge ΔQ_NPj, injected into or drawn from the neutral point O_j. The duty ratio Δd_j is usually taken as −0.04~0.04, which is small, and thus does not affect the transmission power [27].

As can be seen from (9), the fundamental component of phase current i_Li,1 can be regarded as a function of three control degrees of freedom (d, d₁, and d₂), and the voltage conversion ratio k, and i_Li,1 can be expressed as shown in (14). Neutral-point voltage balancing can be achieved by regulating the charge that is injected into the neutral point by means of the duty ratio adjustment, and the introduced charge ΔQ_NPj can be derived using (15), where t_c is the efficient charging time under the duty ratio adjustment.

$$i_{\mathrm{Li},1}=F_1\left(d_1,d_2,d,k\right)$$

(14)

$$\Delta Q_{\mathrm{NPj}}={\displaystyle \sum _{\mathrm{i}=\mathrm{A},\mathrm{B},\mathrm{C}}{\displaystyle {\int }_0^{t_{\mathrm{c}}}{i}_{\mathrm{Li},1}\left(t\right)dt}}=F_2\left(d_1,d_2,d,k,t_{\mathrm{c}}\right)$$

(15)

ΔQ_NPj is related to the operating conditions, which determine the voltage conversion ratio k and the three control degrees of freedom under basic modulation. The control parameter design needs to derive the relationship between Δd_j and ΔQ_NPj. According to Figure 6, the efficient time t_c can be easily deduced using the duty ratio adjustment, but ΔQ_NPj also depends on different operating conditions. Therefore, it is difficult to obtain the exact direction and quantity of ΔQ_NPj using (15), and the parameter design of the balancing control is complex.

A neutral-point voltage balancing method is proposed below, that consists of a sign-hysteresis control with a dead zone. Although the exact value of ΔQ_NPj with the specific Δd_j is hard to calculate, the following analysis shows that the sign of ΔQ_NPj can change inversely with changes in the sign of Δd_j. This provides the theoretical basis for the sign-hysteresis design. Furthermore, in order to avoid changes in the duty ratio during each switching period, a dead zone can be set. The neutral-point voltage is adjusted by a small change during a switching period that does not affect the normal modulation or transmission power of the converter. The proposed neutral-point voltage balancing method only needs to sample the capacitor voltages, and has a rapid response speed, without being subject to stability problems. In contrast to the methods that are described in previous work, this proposed method is applicable in all operating modes of the 3L-DAB3. The complexity of the control parameter design is avoided, making it easy to implement. The following derivation takes phase A as an example.

First, i_LA,1 can be decoupled into the component i_p,LA,1, which is in phase with v_A1O1,1, and the component i_q,LA,1, which is in quadrature with v_A1O1,1. The i_LA,1 can be expressed as shown in (16), where I_p,LA,1 and I_q,LA,1 are the average currents of i_p,LA,1 and i_q,LA,1 in a switching period, respectively.

$$i_{\mathrm{LA},1}=i_{\mathrm{p},\mathrm{LA},1}+i_{\mathrm{q},\mathrm{LA},1}=I_{\mathrm{p},\mathrm{LA},1}\cdot \sin \left(\omega t\right)+I_{\mathrm{q},\mathrm{LA},1}\cdot \cos \left(\omega t\right)$$

(16)

The relationship between i_p,LA,1, i_q,LA,1, and v_A1O1 is shown in Figure 9. On the basis of (13) and Figure 6, it is possible to obtain the neutral-point charge in each interval of phase A. The yellow shaded areas in Figure 9 represent the charge that is injected into (charging area ‘+’) or drawn from (discharging area ‘−’) the neutral point O₁ by i_LA,1. Due to the odd and half-wave symmetry of v_A1O1, the total charge that is injected into O₁ of phase A is zero in a switching period. The neutral-point voltage maintains balanced.

When small perturbations in the neutral-point voltage appear, a duty ratio adjustment should be performed to introduce a nonzero charge ΔQ_z to balance the neutral-point voltage. The changes in the operating intervals (brown, dotted lines) and introduced charge ΔQ_zn (brown striped areas) are depicted in Figure 10, in which the inner duty ratio of v_A1O1 is adjusted to d₁ + Δd₁ (Δd₁ < 0). The total charge ΔQ_z is the sum of ΔQ_zn, where the subscript z (z = 1, 2, 3) represents operating modes 1, 2, and 3, and the subscript n represents different parts of the charge, respectively.

In Mode 2, i_p,LA,1 does not change the total charge that is injected into the neutral-point before and after the duty ratio adjustment. As shown in Figure 10b, the introduced charge ΔQ₂₁ = −ΔQ₂₄ and ΔQ₂₂ = −ΔQ₂₃, and the sum of them is zero due to the odd and half-wave symmetry of v_A1O1 and i_p,LA,1. For i_q,LA,1, ΔQ₂₆ and ΔQ₂₇ are positive, and ΔQ₂₅ and ΔQ₂₈ are negative. The total introduced charge ΔQ₂ is negative in a switching period. Similarly, the total introduced charge ΔQ₁ in Mode 1 and ΔQ₃ in Mode 3 are negative, too. When Δd₁ > 0, the total introduced charge ΔQ_z will be positive in a switching period, which is the opposite of Δd₁ < 0. The sign of ΔQ_z changes inversely with the change in the sign of Δd₁.

4.2. Realization of the Proposed Balancing Method

When a large perturbation of the neutral-point voltage appears, the voltages and currents will deviate greatly from the balanced value, and the control principle that is discussed above may not be valid. However, the sign of the ΔQ_NPj still changes inversely with the change in the sign of Δd_j. Therefore, a sign-hysteresis band can be used to regulate the sign of Δd_j in such a scenario, and a dead zone can be set to decide whether to implement the duty ratio adjustment. The dead zone controls the neutral-point voltage to a value that is close to the balanced value, thus avoiding duty ratio changes in each switching period. Finally, a neutral-point voltage balancing method consisting of a sign-hysteresis control with a dead zone is proposed, as shown in Figure 11.

On the basis of the sampled capacitor voltage v_CP1 and v_CS1 and the reference voltage V_ref, the determination as to whether to implement Δd_j can be made. V_ref is the reference value of the neutral-point voltage and is expressed as V_ref = V_dc/2. The dead zone (V_ref − h_d, V_ref + h_d) is set to implement Δd_j, and the dead zone characteristic DZ(∙) can be described as shown in (17), where e_vc is the voltage error and is expressed as e_vc = V_C1 − V_ref. S_dz is the enabling signal of the duty ratio adjustment. When S_dz = 0, the duty ratio adjustment is not implemented and Δd_j = 0. When S_dz = 1, the initial Δd_j is set, and the sign-hysteresis control is activated. In order to guarantee the accurate sign of Δd_j, a sign-hysteresis band (V_ref − H, V_ref + H) is set, and the sign-hysteresis characteristic H(∙) is described as shown in (18).

$$S_{\mathrm{dz}}=\mathrm{DZ}(e_{\mathrm{vc}})=\{\begin{array}{cc}0,& \mathrm{if} \left|e_{\mathrm{vc}}\right|\le h_{\mathrm{d}}\\ 1,& \mathrm{if} \left|e_{\mathrm{vc}}\right|>h_{\mathrm{d}}\end{array}$$

(17)

$$\Delta d_{\mathrm{j}}=\mathrm{H}(e_{\mathrm{vc}})=\{\begin{array}{cc}\Delta d_{\mathrm{j}},& \mathrm{if} \left|e_{\mathrm{vc}}\right|\le H\\ -\Delta d_{\mathrm{j}},& \mathrm{if} \left|e_{\mathrm{vc}}\right|>H\end{array}$$

(18)

The output Δd_j of the neutral-point voltage balancing method is selected by the enabling the switch K, as shown in Figure 11. When S_dz = 0, K switches to Point 0, and Δd_j = 0. When S_dz = 1, K switches to Point 1, and Δd_j is determined by the sign-hysteresis control.

Furthermore, the phase current i_Li has opposite effects on the neutral points of both sides. When i_Li flows out of the neutral point O₁, it flows relatively to the neutral point O₂. Therefore, the duty ratio adjustment of the two sides should satisfy the constraint Δd₂ = −Δd₁ [38]. On the basis of the above analysis, it can be seen that h_d is related to the ripple requirement of the capacitor voltages in steady state, and H can be set according to the maximum allowable ripple that satisfies the operating requirements of the 3L-DAB3. The proposed balancing method only needs to sample capacitor voltages and has a simple, logical judgement mechanism. The control algorithm and design are simple and easy to implement. Compared with the conventional algorithm, the complexity of the control parameter design is avoided, and there are no problems with respect to stability. The theoretical analysis method of the neutral-point voltage balancing principle is applicable to all 3L-DAB3, and the proposed balancing method can also be used in all 3L-DAB3.

5. Simulation Results and Experimental Verification

In this section, the simulation and experimental results are presented, verifying the effectiveness of the proposed balancing method. The experiments were conducted on a laboratory prototype of the 3L-DAB3 with the parameters that are listed in

Table 1. Simulation and prototype parameters of the 3L-DAB3.

Parameter	Value	Parameter	Value
Input voltage VP	400 V	Turns ratio of T nk	1
Output voltage VS	300 V	Switching frequency fs	20 kHz
Rated power	3.6 kW	Dead zone hd	1
Input/output capacitors	150 μF	Sign-hysteresis parameter H	10
Series inductor Li	125 μH	Duty ratio |∆dj|	0.03
Power devices	ON semiconductor—FGH50T65SQD (650 V/50 A)

. Using the optimization strategies that are proposed in [34,36] and the closed-loop control that is proposed in [39], a digital controller, shown in Figure 12, was implemented using a TMS320F28335 DSP from TI and a Spartan6XC6SLX25 FPGA from Xilinx. p denotes the normalized power with a value of P_base = 3n_kV_PV_S/(π³f_sL_i), and V_Sref is the reference voltage of the secondary side. G_ij1–G_ij6 are the drive waveforms of the switches on the primary and secondary sides, respectively. The laboratory prototype is presented in Figure 13.

5.1. Simulation Results

The 3L-DAB3 with the proposed neutral-point voltage balancing method was simulated using MATLAB/Simulink software. A 3.6 kW 3L-DAB3 with the parameters that are listed in Table 1 was established to verify the performance of the proposed method.

The converter operates with an output voltage reference V_Sref = 300 V. The steady-state waveforms are illustrated in Figure 14. When the reference transmission power was set as 900 W, the resistance load was set to 100 Ω; the operating waveforms are presented in Figure 14a. The terminal voltage v_LA1 operated in Mode 2 and v_LA2 operated in Mode 3 with the neutral-point voltage balancing. When the reference transmission power was set at the rated power of 3.6 kW, the resistance load was set to 25 Ω; the operating waveforms are presented in Figure 14b. The v_LA1 and v_LA2 operated in Mode 3, and the phase current i_LA became more sinusoidal with increasing transmission power. As shown in Figure 14c, with the close-loop control, the neutral-point voltage maintained balanced, and the output voltage responded quickly. The output voltage V_S = 300 V, and the capacitor voltages v_CP1 = v_CP2 = 200 V and v_CS1 = v_CS2 = 150 V in the steady state. The FFT analysis results of the system are presented in Figure 15. With the applied filter capacitor C_S1 = C_S2 = 150 μF, the THD results of the system were controlled to 0.04% and 0.02% under 900 W and 3.6 kW, respectively.

Simulation waveforms with small perturbations in the drive waveforms are shown in Figure 16, in which the neutral-point voltage balancing method was not activated. The duty ratio of the drive waveform G_i21 in the simulation was set to be shorter by 0.04, as shown in Figure 16a, and the waveforms of the voltages and phase current are presented in Figure 16b,c, respectively. With the perturbations in the drive waveforms, the capacitor voltages deviate from the balanced values, and oscillate for a long time. As shown in Figure 16c, the worst deviations of the capacitor voltages were v_CP1 = 226 V, v_CP2 = 174 V, v_CS1 = 189.4 V, and v_CS2 = 110.6 V at a constant output voltage V_S = 300 V. Meanwhile, compared with it being under steady-state conditions, as shown in Figure 14b, the i_LA also deviates from that found under steady-state conditions.

Furthermore, the performance of the proposed neutral-point voltage balancing method is shown in Figure 17. As shown in Figure 17a, the proposed neutral-point voltage balancing method was implemented at t₀ = 0.2 s. The values of v_CP1 and v_CS1 were outside the dead zone, and the duty ratio adjustment was activated. After several switching periods, the v_CP1 was higher than 210 V at t₁ = 0.215 s. The sign-hysteresis control worked, and Δd₁ = −Δd₁. The v_CS1 was within the sign-hysteresis band, and Δd₂ = Δd₂. With the pre-set dead zone h_d = 1 V, the capacitor voltages were controlled to within the dead zone band, as shown in Figure 17a. Finally, the neutral-point voltages of the primary and secondary sides achieved balance at t₂ = 0.24 s and t₃ = 0.25 s, respectively. The proposed method can effectively guarantee neutral-point voltage balance. To verify the dynamic performance of the proposed balancing method, the transmission power was suddenly changed from 900 W to 3.6 kW at t₄ = 0.5 s, as shown in Figure 17b. It can be seen that the neutral-point voltage balancing was preserved before and after the load change by means of the proposed balancing method, with a rapid response speed.

5.2. Experimental Verification

Waveforms with a neutral-point voltage imbalance are illustrated in Figure 18a, and the drive waveforms of S_B21 are depicted in Figure 18b. G_B21 is the ideal drive waveform, and G’_B21 is the actual waveform measured from S_B21, when the rising edge and falling edge of G’_B21 were about 0.7 μs later. As a result, the duration of the P state changed. The neutral-point voltages deviated greatly from the balanced value under the open-loop control, where the input voltage was V_P = 100 V, and the capacitor voltages were v_CP1 = 82 V, v_CP2 = 18 V, v_CS1 = 63 V, and v_CS2 = 27 V. This factor affected the neutral-point charge and led to neutral-point voltage imbalance, which is consistent with the theoretical analysis. With small perturbations in the drive waveforms, the nonideal voltage of phase B interfered with the probe measurement of the v_A2O2 in phase A. There was a voltage spike in v_A2O2, as can be seen in Figure 18a, which could have been eliminated by replacing the probe or the oscilloscope. However, this measurement interference did not affect the experimental verification of the proposed method.

The steady-state waveforms with the proposed balancing method are shown in Figure 19 and Figure 20. From the positive and negative voltage levels of v_A1O1 and v_A2O2 in Figure 19a and Figure 20a, it can be seen that the capacitor voltages approximately satisfied v_CP1 = v_CP2 = 200 V and v_CS1 = v_CS2 = 150 V within the pre-set dead zone band. The neutral-point voltages of both sides were able to be stabilized at values that were close to the balanced values under 900 W and 3.6 kW. With the close-loop control, the V_S was controlled to a value that was close to the reference value of 300 V. The primary terminal voltage v_LA1 of L_A operated in Mode 2 under 900 W, as shown in Figure 19b, and operated in Mode 3 under 3.6 kW, as shown in Figure 20b, which is consistent with the theoretical analysis. It can also be observed that v_LA1, v_LA2, and i_LA are nearly sinusoidal in the 3L-DAB3. To verify that the neutral-point voltage balance can be maintained under steady-state conditions for a long time, the capacitor voltages v_CP1 and v_CS1 are shown in Figure 21. Under 3.6 kW, v_CP1 and v_CS1 can be constantly controlled to values close to 200 V and 150 V, respectively, and the voltage ripples were restricted to within 1 V by means of the pre-set dead zone band, as shown in Figure 21b. The neutral-point voltage balance transient process is shown in Figure 22. Due to the topological symmetry of the converter, the same balancing modulation is used on both sides. Thus, the balance transient process of v_CS1 and v_CS2 is given, and the transient process of v_CP1 and v_CP2 is similar. After activating the proposed neutral-point balancing method, the capacitor voltages of v_CS1 and v_CS2 become approximately equal in 15 ms. The experimental results are consistent with the analysis and simulation, thus verifying the effectiveness of the proposed balancing method.

With the proposed balancing method and the closed-loop control, the dynamic performance of the 3L-DAB3 was verified by applying load steps from 900 W to 3.6 kW, as shown in Figure 23. V_P was maintained at 400 V, and V_S was regulated at 300 V, with a small voltage overshoot by the closed-loop control. v_CP1 was regulated at 200 V and v_CS1 was regulated at 150 V, with a small voltage overshoot by the closed-loop control, on the basis of which it can also be concluded that the neutral-point voltages of both sides remained balanced before and after the change in load. The proposed balancing method has a good dynamic response. The efficiency curve varied with the transmission power as shown in Figure 24. It can be seen that the 3L-DAB3 was able to achieve high efficiency throughout the whole load range when using the optimization strategies that were proposed in [36].

6. Conclusions

Three-phase three-level dual-active-bridge (3L-DAB3) converters can achieve high power density and high efficiency. To guarantee the reliability of 3L-DAB3s, this paper focused on the neutral-point voltage balancing principle. A neutral-point voltage balancing method consisting of a sign-hysteresis control with a dead zone was proposed. With a Y-Y winding configuration, the 3L-DAB3 has three operating modes, and an analysis of the balancing principle was conducted for the three modes. The effective charging and discharging intervals of the neutral point were indicated, and the charge that was introduced by the adjustment of the duty ratio was obtained. The sign of ΔQ_NPj changes inversely with the change in the sign of Δd_j. As a result, a sign-hysteresis band was applied to guarantee an accurate direction of adjustment. Furthermore, a dead zone was set to decide whether to activate the duty ratio adjustment. The dead zone is able to control the neutral-point voltage to a value that is close to the balanced value, thus avoiding changes in the duty ratio during each switching period. The proposed balancing method avoids the complexity of control parameter design and it does not affect the normal modulation of the converter during the adjustment process. As a result of only sampling the capacitor voltages, the implementation of the algorithm is simple. The proposed method is valid for all operating modes of the 3L-DAB3, and has a rapid response speed, and does not suffer from any problems with respect to stability. Finally, the performance of the 3L-DAB3 using the proposed balancing method were verified by the experimental results. The neutral-point voltage balancing can be guaranteed under steady-state conditions as well as under dynamic testing.