Design and Investigation of a Dual Material Gate Arsenic Alloy Heterostructure Junctionless TFET with a Lightly Doped Source

Abstract

This paper designs and investigates a novel structure of dual material gate-engineered heterostructure junctionless tunnel field-effect transistor (DMGE-HJLTFET) with a lightly doped source. Similar to the conventional HJLTFET, the proposed structure still adopts an InAs/GaAs_0.1Sb_0.9 heterojunction at source and channel interface and employs a polarization electric field at the arsenic heterojunction induced by the lattice mismatch in the InAs and GaAs_0.1Sb_0.9 zinc blende crystal to improve band to band tunneling (BTBT) current. However, the gate electrode is divided into three parts in DMGE-HJLTFET namely the auxiliary gate (M1), control gate (M2) and tunnel gate (M3) with workfunctions Φ_M1, Φ_M2 and Φ_M3, where Φ_M1 = Φ_M3 < Φ_M2, which not only improves ON-state current but also decreases the OFF-state current. In addition, a lightly doped source is used to further decrease the OFF-state current of this device. Simulation results indicate that DMGE-HJLTFET provides superior metrics in terms of logic and analog/radio frequency (RF) performance as compared with conventional HJLTFET, the maximum ON-state current and transconductance of the DMGE-HJLTFET increases up to 5.46 × 10⁻⁴ A/μm and 1.51 × 10⁻³ S/μm at 1.0 V drain-to-source voltage (Vds). Moreover, average subthreshold swing (SSave) of DMGE-HJLTFET is as low as 15.4 mV/Dec at low drain voltages. Also, DMGE-HJLTFET could achieve a maximum cut-off frequency (f_T) of 423 GHz at 0.92 V gate-to-source voltage (Vgs) and a maximum gain bandwidth (GBW) of 82 GHz at Vgs = 0.88 V, respectively. Therefore, it has great potential in future ultra-low power integrated circuit applications.

1. Introduction

Advancement in the semiconductor industry has increased the demand for nanoscale devices for analog/ radio frequency (RF) and high switching speed applications, but, power consumption and reliability issues are the major concerns in integrated circuits (ICs), so compactness in devices is an urgent problem to be solved in nanoscale systems. According to Moore’s law, drastic reduction in volume and cost of the devices will occur. However, as the conventional metal oxide semiconductor field effect transistors (MOSFETs) scale down continuously, the OFF-state current dramatically increases and short channel effects (SCE) are severely aggravated, and a limitation of 60 mV/Dec subthreshold swing (SS) cannot be broken. In addition, low switch ratio (Ion/Ioff) ratio and drain induced barrier lowering (DIBL) effect are also arising. In order to avoid these issues, a lot of novel structures have been proposed and investigated in recent years, among them, tunnel field effect transistor (TFET) [1,2] is a selective candidate for future ultra-low power applications, where carrier injection from source to channel is modulated by a gate-controlled band to band tunneling (BTBT) mechanism. The structure of a conventional TFET consists of a gated p type region/ intrinsic region /n type region (p–i–n) diode operating under a reverse bias condition and the gate bias determines the quantum tunneling barrier width at the source–channel interface. Benefitting from innovation of structure and mechanism, TFETs are compatible with conventional complementary metal oxide semiconductor (CMOS) process and can break the SS limit of 60 mV/Dec. Additionally, it is not influenced by the short channel effects (SCE) and the leakage current of conventional TFETs is small under the OFF-state condition [3,4]. However, small ON-state current and large Miller capacitance are still inherent disadvantages in TFETs. To improve the ON-state current, a lot of novel structures of TFETs are proposed, for example, the L-shaped channel TFET (LTFET) [5,6,7], U-shaped channel TFET (UTFET) [8,9], symmetric TFET (S-TFET) [10,11], U-shaped channel with dual sources TFET (DS-UTFET) [12], covered source–channel TFETs (CSC-TFETs) [13], hetero junction TFET with T-shaped gate (HTG-TFET) [14], 2D materials channel TFET and hetero-bilayer TFETs [15,16]. As a whole, TFETs reported in recent years adopt abrupt junction at tunneling interface, which leads to a complex fabrication processes and a high thermal budget. In addition, a heavily doped concentration in the channel and active region are also challenging during the fabrication process and it is easy to be influenced by random dopant fluctuations (RDFs) [17,18,19,20,21].

To avoid complex fabrication processes and high thermal budgets in TFETs, the junctionless tunneling field effect transistor (JLTFET) [22,23,24,25,26,27,28,29,30] has been studied extensively in recent years, which uses uniformly high-doping concentration in the source, channel and drain regions so that the doping concentration and type of channel region are consistent with source region and drain region. Due to uniform doping, the JLTFET is immune to random dopant fluctuations (RDFs) and overcomes complex fabrication processes in manufacturing, meanwhile, source and drain region are formed by the charge plasma concept which further avoids high thermal budgets in the JLTFET. Whereas, low ON-state current still remains the most serious problem in junctionless TFETs due to the presence of barrier between source and channel.

In this paper, a novel structure of dual material gate-engineered heterostructure junctionless tunnel field-effect transistor (DMGE-HJLTFET) with a lightly doped source was proposed to improve the performance of a conventional HJLTFET [31,32], where the corresponding heavily p type doping region / intrinsic region / heavily n type doping region (P⁺–I–N⁺)structure can be realized by the charge plasma concept with appropriate workfunction for the polar gate (PG) and control gate (CG). The PG is located at the source region and has a larger work function than CG for inducing a P⁺ source while CG is located at the middle for inducing the intrinsic channel. We used a InAs/GaAs_0.1Sb_0.9 heterostructure at the source–channel interface to improve band to band tunneling (BTBT) current through the heterostructure of InAs/GaAs_0.1Sb_0.9 and a polarization electric field at the arsenic heterojunction induced by the lattice mismatch in the arsenic alloy zinc blende crystal. Moreover, the gate electrode was divided into three parts namely auxiliary gate (M1), control gate (M2) and tunnel gate (M3) with workfunctions Φ_M1, Φ_M2 and Φ_M3, respectively, where Φ_M1 = Φ_M3 < Φ_M2. Appropriate workfunctions for the gate electrodes can further improve ON-state current and suppress OFF-state current. Consequently, the DMGE-HJLTFET provides superior metrics in terms of logic and analog/RF performance as compared with conventional a HJLTFET, that is to say, it can generate higher ON-state current, higher transconductance, higher output transconductance and higher f_T and GBW. Therefore, it will have great potential in future ultra-low power and high frequency integrated circuit applications [33,34,35,36,37].

The paper is organized as follows: Section 2 describes the initial device parameters and essential simulation models. Section 3 introduces the properties of the structure and the optimization process. Section 4 shows the conclusions.

2. Methods

Figure 1a shows the device structure of a conventional HJLTFET, in which the PG is located at the source region and has a larger workfunction than CG for inducing a P⁺ source while CG is located at the middle for inducing an intrinsic channel, InAs/GaAs_0.1Sb_0.9 heterostructure is introduced at the source–channel interface and a heavy doping is considered in the silicon body with concentration of 1 × 10¹⁹ cm⁻³, resulting in a junctionless P⁺-I-N⁺ structure with appropriate workfunctions for PG and CG by the charge plasma concept. Compared with a conventional HJLTFET, a DMGE-HJLTFET still uses InAs/GaAs_0.1Sb_0.9 at the source–channel interface and introduces a lightly doped source, moreover, the gate electrode is divided into three parts namely auxiliary gate (M1), control gate (M2) and tunnel gate (M3) with workfunctions Φ_M1, Φ_M2 and Φ_M3, respectively, where Φ_M1 = Φ_M3 < Φ_M2, as shown in Figure 1b. As a result, the DMGE-HJLTFET has larger ON-state current and lower OFF-state current than HJLTFET, so it will have great potential to be applied in future ultra-low power integrated circuit.

The detailed parameters of the conventional HJLTFET and DMGE-HJLTFET used in the simulation were as follows: the length of source region (L_S), the length of channel region (L_CH) and the length of drain region (L_D) were all 20 nm; the gap length (L_SG) between source and channel was 5 nm; the thickness of HfO₂ (T_OX) was 2 nm, the thickness of the body (Tb) was 5 nm; the length of auxiliary gate (L1) was 7 nm, the length of control gate (L2) was 10 nm, the length of tunnel gate (L3) was 3 nm; the workfunction of polarity gate (Φ_PG) was 5.9 eV, the workfunction of control gate (Φ_CG) was 4.4 eV, the workfunction of auxiliary gate (Φ_M1) and the work function of tunnel gate (Φ_M3) were 4.1 eV. In addition, the N-type doping concentration of the channel region and drain region were all 1 × 10¹⁹ cm⁻³ in the HJLTFET and DMGE-HJLTFET; whereas the N-type doping concentration of source region in the HJLTFET and DMGE-HJLTFET were 1 × 10¹⁹ cm⁻³ and 5 × 10¹⁷ cm⁻³, respectively.

All the simulations were performed using ATLAS Silvaco TCAD version 5.20.2.R (Silvaco International, Santa Clara, CA, USA). To consider the band to band tunneling phenomenon in the case of TFET and the spatial variation of the energy bands, the nonlocal BTBT model (BBT.NONLOCAL) was used. The presence of a highly doped channel meant that the Shockley–Read–Hall related to concentration (CONSRH) was activated to account for the minority carrier recombination effects. In addition to this, Fermi statistics (FERMI) and band gap narrowing (BGN) model were also activated. Moreover, a quantum confinement model given by Hansch (HANSCHQM) was also used to take into account quantum confinement effects due to the increased doping levels and thinner gate oxide in the channel. Furthermore, the Schenk model for trap-assisted tunneling (SCHENK.TUNN) was also involved to include the tunneling of electrons from the valence band to the conduction band through trap or defect states and phonon-assisted tunneling effects.

3. Results and Discussion

3.1. The Physical Mechanism of dual material gate-engineered heterostructure junctionless tunnel field-effect transistor (DMGE-HJLTFET)

The physical mechanism of the DMGE-HJLTFET is shown in Figure 2a–d. Figure 2a shows the nonlocal BTBT tunneling rate of electrons and Figure 2b shows the nonlocal BTBT tunneling rate of holes of the DMGE-HJLTFET when Vds = 1 V and Vgs = 1.2 V. It was obvious to observe that BTBT mainly occurred at the source and channel interface, and the rate of BTBT increased significantly due to the heterojunction between source and channel. In Figure 2c, the electric field distribution of DMGE-HJLTFET at Vds = 1 V and Vgs = 1.2 V is illustrated, it is not difficult to find from this figure that value of electric field was markedly improved near the hetero junction and hetero dielectric, so the ON-state current significantly increased. In addition, the total current density of DMGE-HJLTFET was researched in order to well understand the physical mechanism, as shown in Figure 2d.

Figure 3a shows the energy band diagram of the HJLTFET and DMGE-HJLTFET in ON-state (Vds = 1 V, Vgs = 1 V), where it was noticed that the conduction band and valance band of DMGE-HJLTFET at the source–channel interface were very close to each other and the tunneling distance of DMGE-HJLTFET was much smaller than the HJLTFET, i.e., tunneling width and effective tunneling area of DMGE-HJLTFET were obviously improved by appropriate workfunctions for the divided gate electrode as compared with HJLTFET, resulting in enhancement on electron probability to tunnel from the source to channel junction in the DMGE-HJLTFET. Figure 3b indicates the energy band diagram of HJLTFET and DMGE-HJLTFET in OFF-state (Vds = 1 V, Vgs = 0 V), and from this figure it is not difficult to find that the distance of conduction band and valance band in source/channel interface of the DMGE-HJLTFET was much larger than HJLTFET. In addition, an extra barrier height occurred in the channel region for DMGE-HJLTFET. This is because the gate electrode was divided into three parts in the DMGE-HJLTFET namely the auxiliary gate (M1), control gate (M2) and tunnel gate (M3), and the auxiliary gate (M1) produced the extra barrier height in OFF-state.

3.2. The Input Characteristics

Figure 4a illustrates the transfer characteristics of HJLTFET and DMGE-HJLTFET. As can be seen clearly from this figure that the DMGE-HJLTFET can produce higher ON-state current than HJLTFET, and the ON-state current of the DMGE-HJLTFET was 5.46 × 10⁻⁴ A/μm at Vgs = 1.2 V, however, the corresponding ON-state current of the HJLTFET was only 1.05 × 10⁻⁴ A/μm. Meanwhile, the OFF-state current of DMGE-HJLTFET was 8.4 × 10⁻¹⁸ A/μm while the OFF-state current of HJLTFET was 3.1 × 10⁻¹⁷ A/μm. Consequently, compared with the conventional HJLTFET, the Ion/Ioff ratio of the DMGE-HJLTFET was increased by one order of magnitude. In addition, the DMGE-HJLTFET has a smaller average subthreshold swing (SSave) because of structural innovation, the SSave (which is extracted from Vmin to Vt; Vmin is the gate voltage where drain current equals to Ioff, and the gate voltage where the drain current becomes 1 × 10⁸ A/μm is taken as the threshold voltage Vt) values of the DMGE-HJLTFET and HJLTFET were 15.4 mV/Dec and 24.5 mV/Dec, respectively.

The transconductance (g_m) is an important parameter to evaluate the analog performance of devices, which is defined as the first derivative of drain current (Ids) with respect to V_GS, the formula of g_m is given by Equation (1):

$${\mathrm{g}}_{\mathrm{m}}=\raisebox{1ex}{$\mathrm{d}{\mathrm{I}}_{\mathrm{d}\mathrm{s}}$}\!\left/ \!\raisebox{-1ex}{$\mathrm{d}{\mathrm{V}}_{\mathrm{g}\mathrm{s}}$}\right..$$

(1)

As shown in Figure 4b, the g_m of the DMGE-HJLTFET increased observably compared with HJLTFET. The maximum g_m value of the DMGE-HJLTFET was 1.51 × 10⁻³ S/μm at Vgs = 1.14 V, while the maximum g_m value of the HJLTFET was 6.02 × 10⁻⁴ S/μm. Therefore, the maximum g_m of the DMGE-HJLTFET was almost 26 times more than the HJLTFET.

3.3. The Output Characteristics

Figure 5a indicates the output characteristics of the HJLTFET and DMGE-HJLTFET at Vgs = 1 V, it can be seen clearly that HJLTFET showed worse saturation performance when gate voltage was less than 0.5 V, meanwhile, the maximum output saturation drain current of HJLTFET was only 2.35 × 10⁻⁵ A/μm. While the DMGE-HJLTFET exhibited better saturation performance within the simulated voltage range, and the maximum output saturation drain current of DMGE-HJLTFET increased up to 2.66 × 10⁻⁴ A/μm.

As another important parameter to evaluate the analog performance of the devices, the output transconductance (g_ds) can be calculated by the first derivative of the drain current (Ids) with respect to V_DS, Equation (2) is the formula of g_ds:

$${\mathrm{g}}_{\mathrm{d}\mathrm{s}}=\raisebox{1ex}{$\mathrm{d}{\mathrm{I}}_{\mathrm{d}\mathrm{s}}$}\!\left/ \!\raisebox{-1ex}{$\mathrm{d}{\mathrm{V}}_{\mathrm{d}\mathrm{s}}$}\right..$$

(2)

The comparison of g_ds characteristics of the HJLTFET and DMGE-HJLTFET at Vgs = 1 V is shown in Figure 5b. It can be viewed that g_ds of the DMGE-HJLTFET was greater than that of HJLTFET within the simulated voltage range. The maximum output conductance of DMGE-HJLTFET was 6.06 × 10⁻⁴ S/μm when Vds = 0.56 V, however, the maximum output conductance of the HJLTFET was 9.46 × 10⁻⁵ S/μm when Vds = 0.38 V. Therefore, the maximum g_ds of the DMGE-HJLTFET was almost seven times more than HJLTFET.

3.4. Effect of Device Parameters on the Transfer Characteristics

Figure 6a shows the impact of source doping concentration on transfer characteristics. As can be seen from this figure, the ON-state current of the DMGE-HJLTFET decreased with the increase of source doping concentration, and it was easy to find that the ON-state current of the DMGE-HJLTFET went from 5.46 × 10⁻⁴ A/μm to 3.61 × 10⁻⁴ A/μm when the source doping concentration increased from 1 × 10¹⁷ cm⁻³ to 1 × 10¹⁹ cm⁻³, the reason for this was that we adopted uniform N-type doping in the source, channel and drain region, and used the charge plasma concept to form a P⁺–I–N⁺ structure with the appropriate workfunction for PG and CG. As a result, the hole concentration formed by polarization in the source region decreased with the increase of the N-type concentration of the lightly doped source. Since the tunnel process was the hole of source valance band to channel conduction band, the ON-state current decreased when we increased the source doping concentration. Moreover, the OFF-state current of DMGE-HJLTFET always remained at the order of 10⁻¹⁷ A/μm. Figure 6b presents the variation of the ON-state current and the OFF-state current with the increase of source doping concentration, it was very clear that the OFF-state current was minimal when source doping concentration was 5 × 10¹⁷ cm⁻³, as a consequence, the ratio of Ion/Ioff comes up to maximum at this doping concentration as shown in the inserted small graph at Figure 6b. Therefore, the source doping concentration was selected as 5 × 10¹⁷ cm⁻³ in order to obtain maximal Ion/Ioff value.

We mentioned above that the gate electrode was divided into three parts namely auxiliary gate (M1), control gate (M2) and tunnel gate (M3) with workfunctions Φ_M1, Φ_M2 and Φ_M3, respectively, where Φ_M1 = Φ_M3 < Φ_M2. Next, the effects of the three parameters on the transfer characteristics will be discussed.

Figure 7a shows the impact of polar gate workfunction (Φ_PG) on transfer characteristics with keeping Φ_M1 = Φ_M3 = 4.1 eV and keeping Φ_M2 = 4.4 eV. As can be seen clearly from Figure 7a, the ON-state current of the DMGE-HJLTFET increased and the OFF-state current of the DMGE-HJLTFET stayed at the order of 10⁻¹⁷ A/μm with the increase of Φ_PG, so an appropriate choice for Φ_PG was very important to achieve higher ON-state current and lower OFF-state current simultaneously. The reason for this was that Φ_PG had a large influence on the polarization charge formation in the source region, the amount of polarization charge increased with the polar gate workfunction, resulting in the variation of energy band, as illustrated in Figure 7b. Figure 7b shows the variation of energy band with different Φ_PG, the position of conduction band and valance band in source region became higher and higher when Φ_PG went up, which boosted the effective tunneling area of the channel–source interface, and the ON-state current of the DMGE-HJLTFET increased with the increase of Φ_PG. Therefore, Figure 7b further demonstrated the conclusion of Figure 7a.

Figure 8a–d indicate the impact of the control gate workfunction (Φ_M2) on transfer characteristics, electric field distribution and band diagram with keeping Φ_M1 = Φ_M3 = 4.1 eV and keeping Φ_PG = 5.9 eV. Selection of Φ_M2 was critical for obtaining higher ratio of Ion/Ioff and prominent SSave, as depicted in Figure 8a. The ON-state current of the DMGE-HJLTFET decreased with the increase of Φ_M2 and the OFF-state current of the DMGE-HJLTFET decreased with the increase of Φ_M2 when Φ_M2 ≤ 4.4 eV. In addition, the ambipolar current occurred when Φ_M2 ≥ 4.5 eV which led to very poor transfer characteristic curves in the DMGE-HJLTFET as shown in Figure 8a. In Figure 8b, it is very clear that the value of electric field under M3 decreased with the increase of Φ_M2 while the value of the electric field under M1 and M2 decreased with the increase of Φ_M2 when Φ_M2 ≤ 4.4 eV and increased with the increase of Φ_M2 when Φ_M2 ≥ 4.5 eV, which further explains the variation of the ON-state current in Figure 8a and made the energy band bend severely in this region, as shown in Figure 8c,d. Figure 8c,d depict the energy band diagram in ON-state and OFF-state, where it was observed that the tunneling barrier height increased with the increase of Φ_M2 and height of barrier in OFF-state was much higher than that of ON-state. Hence, the overall performance of the DMGE-HJLTFET was significantly affected by Φ_M2, considering all the factors, the optimal value of control gate workfunction was chosen as 4.4 eV.

Figure 9a–d illustrate the impact of the auxiliary gate workfunction (Φ_M1) and tunnel gate workfunction (Φ_M3) on transfer characteristics, surface potential, electric field and band diagram with keeping Φ_M2 = 4.4 eV and keeping Φ_PG = 5.9 eV. The transfer characteristics of the DMGE-HJLTFET at different values of Φ_M1 is shown in Figure 9a, where Φ_M1 was varied from 3.7 eV to 4.4 eV in a step of 0.1 eV. It could be found through the observation of Figure 9a that the ON-state current and the OFF-state current of the DMGE-HJLTFET decreased with the increase of Φ_M1, that is to say, appropriate selection of Φ_M1 was required to achieve higher Ion/Ioff ratio and lower SSave, therefore, Φ_M1 = 4.1 eV was selected as the optimal value for auxiliary gate workfunction. In fact, the variation of transfer characteristics depended on the changes of surface potential and electric field. Figure 9b,c show the distribution of surface potential and electric field at the device surface. It can be noticed that both of them were markedly influenced by Φ_M1 and the DMGE-HJLTFET exhibited higher surface potential and electric field at the position of M1 and M3 under small Φ_M1, in which M1 suppressed the ambipolar leakage current and reduced hot carrier effects (HCEs) by diminishing the lateral electric field at the drain–channel interface. M3 improved the ON-state current by increasing the tunneling probability at the source–channel interface. A higher tunneling rate at the source–channel interface and higher barrier height at drain–channel interface were introduced simultaneously, as shown in Figure 9d. Therefore, Φ_M1 should be small in terms of ON-state current and OFF-state current, and Φ_M1 should not be small in terms of barrier height at the drain–channel interface. All things considered, the optimal value of Φ_M1 was chosen as 4.1 eV.

3.5. Comparison in Terms of Analog/RF Performance

As we know, it is very necessary to research the frequency characteristics of the integrated circuits, which is profoundly affected by parasitic capacitances of devices. Apparently, the characteristics of Cgg (gate capacitance), Cgs (capacitance of gate to source) and Cgd (capacitance of gate to drain) is of great significance to evaluate the frequency characteristics and analog application ability of devices [38]. Figure 10a shows the capacitance of the HJLTFET versus Vgs and Figure 10b shows the capacitance of the DMGE-HJLTFET versus Vgs. As can be observed from Figure 10a,b, the trend of capacitance curve versus Vgs was similar for the HJLTFET and DMGE-HJLTFET, Cgg and Cgd both remained at a small value when Vgs < Vds and increased rapidly with the increasing Vgs when Vgs > Vds, and Cgs maintained a very small value at this condition. In addition, the curve of Cgg and Cgd was highly adjacent due to the existence of a polar gate which separated the control gate electrode far from the source electrode, as a result, coupling of the control gate electrode and source electrode was relatively slight, so, Cgg was mainly determined by Cgd.

The cut-off frequency (f_T) and gain bandwidth (GBW) are important indicators for evaluating RF performance of devices. Based on Figure 10a,b, the cut-off frequency (f_T) and the gain bandwidth (GBW) of the HJLTFET and DMGE- HJLTFET are discussed in next section.

As shown in Equation (3), cut-off frequency (f_T) can be expressed as ratio of gm to C_gg:

$$f_T=\frac{{\mathrm{g}}_{\mathrm{m}}}{2\pi {\mathrm{C}}_{\mathrm{g}\mathrm{s}}\sqrt{1+2\frac{{\mathrm{C}}_{\mathrm{g}\mathrm{d}}}{{\mathrm{C}}_{\mathrm{g}\mathrm{s}}}}}\approx \frac{{\mathrm{g}}_{\mathrm{m}}}{2\pi ({\mathrm{C}}_{\mathrm{g}\mathrm{s}}+{\mathrm{C}}_{\mathrm{g}\mathrm{d}})}=\frac{{\mathrm{g}}_{\mathrm{m}}}{2\pi {\mathrm{C}}_{\mathrm{g}\mathrm{g}}}.$$

(3)

The GBW can be expressed as a ratio of gm to Cgd for the DC gain value equal to 10, as shown in Equation (4) [39,40]:

$$\mathrm{G}\mathrm{B}\mathrm{W}=\frac{{\mathrm{g}}_{\mathrm{m}}}{2\pi 10{\mathrm{C}}_{\mathrm{g}\mathrm{d}}}.$$

(4)

Figure 11a,b respectively show the characteristic curves of f_T and GBW of the HJLTFET and DMGE-HJLTFET. Benefitting from a large transconductance induced by a lightly doped source and gate-engineered heterostructure, the DMGE-HJLTFET could achieve a maximum f_T of 423 GHz at Vgs = 0.92 V and a maximum GBW of 82 GHz at Vgs = 0.88 V, respectively. However, the maximum f_T of the HJLTFET was only 63 GHz at Vgs = 0.98 V and maximum GBW of the HJLTFET was only 72 GHz at Vgs = 1.2 V. Therefore, the DMGE-HJLTFET could be used in future low power and high frequency applications.

4. Conclusions

In this paper, a novel structure of a dual material gate-engineered heterostructure junctionless tunnel field-effect transistor (DMGE-HJLTFET) with a lightly doped source was constructed and researched to improve the performance of conventional InAs/GaAs_0.1Sb_0.9 HJLTFET. Similar to the conventional HJLTFET, the DMGE-HJLTFET still adopted a InAs/GaAs_0.1Sb_0.9 heterojunction at the source and channel interface and employed a polarization electric field at the arsenic heterojunction induced by the lattice mismatch to improve band to band tunneling (BTBT) current. In addition, based on the gate-engineered concept, the gate electrode of DMGE-HJLTFET was divided into three parts to improve the ON-state current and suppress the OFF-state current simultaneously. In this regard, a lightly doped source was used to further optimize the ON-state current and the OFF-state current of this device. In this simulation, the effects of the source doping concentration, polar gate workfunction, control gate workfunction, tunnel gate workfunction and auxiliary gate workfunction on the performance of the DMGE-HJLTFET were researched systematically to optimize the overall device performance. Simulation results indicated that the DMGE-HJLTFET provided superior metrics in terms of logic and analog/RF performance as compared with the conventional HJLTFET, the maximum ON-state current and transconductance of the DMGE-HJLTFET increased up to 5.46 × 10⁻⁴ A/μm and 1.51 × 10⁻³ S/μm at Vds = 1 V. Moreover, SSave of the DMGE-HJLTFET was as low as 15.4 mV/Dec at low drain voltages. Also, the DMGE-HJLTFET could achieve a maximum f_T of 423 GHz at Vgs = 0.92 V and a maximum GBW of 82 GHz at Vgs = 0.88 V, respectively. Therefore, the DMGE-HJLTFET could be used in future low power and high frequency applications.