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Peer-Review Record

Design and Investigation of a Dual Material Gate Arsenic Alloy Heterostructure Junctionless TFET with a Lightly Doped Source

by Haiwu Xie, Hongxia Liu *, Shupeng Chen *, Tao Han and Shulong Wang
Reviewer 1: Anonymous
Reviewer 2: Anonymous
Submission received: 9 September 2019 / Revised: 26 September 2019 / Accepted: 26 September 2019 / Published: 1 October 2019
(This article belongs to the Section Materials Science and Engineering)

Round 1

Reviewer 1 Report

Report on « Design and investigation of a dual material gate arsenic alloy heterostructure junctionless TFET with lightly doped source».

In this paper, the authors present results based on TCAD simulation of Tunnel FET devices. The results are good but before publication the authors may consider the following comments.

Comments:

In page 1 line12, you must add Tunnel FET (TFET) not only TFET In page 1 line12, please give definition of DMGE-HJLTFET? In page 6 line178, replace DM by DMGE. In page 6 line97-200, can you add some explanation why the ION current decrease when you increase the source doping concentration? Normally, when we increase the source doping concentration, we increase ON current.

Author Response

Please see the attachment.

Author Response File: Author Response.pdf

Reviewer 2 Report

The paper concerns the novel structure of dual material gate-engineered 11 InAs/GaAs0.1Sb0.9 heterostructure junctionless TFET. It is well-written and the related experiments are well organized. Therefore, I can recommend its publication after brief modification of introduction part. It can be strengthen by emphasizing the importance and effect of this work with more references. In current form, it lacks related references. Therefore, I recommend to add more references and would be happy to suggest its publication.

Author Response

Please see the attachment.

Author Response File: Author Response.pdf

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