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Computers
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3D Flash Memories
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3D Flash Memories

A special issue of Computers (ISSN 2073-431X).

Deadline for manuscript submissions: closed (30 June 2017) | Viewed by 69485

Special Issue Editors

Dr. Rino Micheloni

E-Mail Website
Guest Editor
Performance Storage Business Unit, Microsemi Corporation, 20871 Torri Bianche, Italy
Interests: flash memories; non-volatile memories; error correction code
Dr. Cristian Zambelli

E-Mail Website
Guest Editor
Dipartimento di Ingegneria, Università di Ferrara, 44121 Ferrara, Italy
Interests: electrical characterization and modeling of non-volatile memories reliability; reliability of solid-state drives
Special Issues, Collections and Topics in MDPI journals

Special Issue Information

Dear Colleagues,

Flash memory has been a disruptive technology from its inception in the early 1990s and innovation is still ongoing after more than 25 years. Thanks to its storage density, NAND Flash memories have changed our lives: USB keys have replaced floppy-disks and Flash Cards (SD, eMMC) record our pictures and movies instead of analog films. In the last four to five years, Solid State Drives (SSDs) have emerged as the new killer applications for Flash: First in the consumer space (smartphones and tablets), but now expanding to enterprise applications as well. Indeed, SSDs, because they are extremely demanding in terms of storage capacity, fueled a new wave of innovations: 3D Flash memories. Today “3D” is a common buzzword but in this specific case it means that multiple layers (up to 64, as we speak) of memory cells are manufactured within the same piece of silicon. 3D is a brand new technology, not only because of its multi-layer architecture, but also because it is based on a new type of NAND memory cell. Thus far, NAND has always been based on "floating gate", where the information is stored by injecting electrons in a piece of polysilicon completely surrounded by oxide (this is why it is called floating gate). On the contrary, most of 3D memories are based on "charge trap" cells. On top of that, there multiple ways (architectures) of building and stacking the memory layers.

In summary, we are just at the start of the 3D journey and we do expect more and more advancements in the coming years. Most of the Flash vendors are already talking about reaching up to 100 vertical layers and, for sure, this will require a lot of innovation in process technology, materials, circuit design, Flash management algorithms, Error Correction Code and, last but not least, 3D architectures.

Authors are invited to submit original contributions on the following topics:

  • 3D Flash memory architectures
  • Process technology for 3D Flash memories (layers and line widths, etching, lithography, deposition, etc.)
  • Reliability of 3D Flash memories
  • Impact of 3D Flash memories on Solid State Drives
  • Error Correction Codes for 3D Flash memories
  • 3D Flash memories with Multi-level storage (MLC, TLC)
  • Power density and thermal issues
  • Logical-to-physical translation in 3D
  • Testing, characterization, and defects
  • Flash Controllers for 3D Flash memories
  • Flash management and Flash signal processing for 3D memories

Dr. Rino Micheloni
Prof. Cristian Zambelli
Guest Editors

Manuscript Submission Information

Manuscripts should be submitted online at www.mdpi.com by registering and logging in to this website. Once you are registered, click here to go to the submission form. Manuscripts can be submitted until the deadline. All submissions that pass pre-check are peer-reviewed. Accepted papers will be published continuously in the journal (as soon as accepted) and will be listed together on the special issue website. Research articles, review articles as well as short communications are invited. For planned papers, a title and short abstract (about 100 words) can be sent to the Editorial Office for announcement on this website.

Submitted manuscripts should not have been published previously, nor be under consideration for publication elsewhere (except conference proceedings papers). All manuscripts are thoroughly refereed through a single-blind peer-review process. A guide for authors and other relevant information for submission of manuscripts is available on the Instructions for Authors page. Computers is an international peer-reviewed open access monthly journal published by MDPI.

Please visit the Instructions for Authors page before submitting a manuscript. The Article Processing Charge (APC) for publication in this open access journal is 1800 CHF (Swiss Francs). Submitted papers should be well formatted and use good English. Authors may use MDPI's English editing service prior to publication or during author revisions.

Keywords

  • 3D Flash memories
  • Floating Gate memory cell
  • Charge Trap memory cell
  • Solid State Drive
  • Error Correction Code
  • Flash controller
  • Flash Management
  • Flash Signal Processing

Published Papers (3 papers)

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Review

6252 KiB  
Review
3D NAND Flash Based on Planar Cells
by Andrea Silvagni
Computers 2017, 6(4), 28; https://0-doi-org.brum.beds.ac.uk/10.3390/computers6040028 - 24 Oct 2017
Cited by 12 | Viewed by 22638
Abstract
In this article, the transition from 2D NAND to 3D NAND is first addressed, and the various 3D NAND architectures are compared. The article carries out a comparison of 3D NAND architectures that are based on a “punch-and-plug” process—with gate-all-around (GAA) cell devices—against [...] Read more.
In this article, the transition from 2D NAND to 3D NAND is first addressed, and the various 3D NAND architectures are compared. The article carries out a comparison of 3D NAND architectures that are based on a “punch-and-plug” process—with gate-all-around (GAA) cell devices—against architectures that are based on planar cell devices. The differences and similarities between the two classes of architectures are highlighted. The differences between architectures using floating-gate (FG) and charge-trap (CT) devices are also considered. Although the current production of 3D NAND is based on GAA cell devices, it is suggested that architectures with planar cell devices could also be viable for mass production. Full article
(This article belongs to the Special Issue 3D Flash Memories)
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5718 KiB  
Review
Architectural and Integration Options for 3D NAND Flash Memories
by Rino Micheloni, Luca Crippa, Cristian Zambelli and Piero Olivo
Computers 2017, 6(3), 27; https://0-doi-org.brum.beds.ac.uk/10.3390/computers6030027 - 10 Aug 2017
Cited by 52 | Viewed by 22085
Abstract
Nowadays, NAND Flash technology is everywhere, since it is the core of the code and data storage in mobile and embedded applications; moreover, its market share is exploding with Solid-State-Drives (SSDs), which are replacing Hard Disk Drives (HDDs) in consumer and enterprise scenarios. [...] Read more.
Nowadays, NAND Flash technology is everywhere, since it is the core of the code and data storage in mobile and embedded applications; moreover, its market share is exploding with Solid-State-Drives (SSDs), which are replacing Hard Disk Drives (HDDs) in consumer and enterprise scenarios. To keep the evolutionary pace of the technology, NAND Flash must scale aggressively in terms of bit cost. When approaching ultra-scaled technologies, planar NAND is hitting a wall: both academia researchers and industry worked to cope with this issue for several decades. Then, the 3D integration approach turned out to be the definitive alternative by eventually reaching mass production. This review paper exposes several 3D NAND Flash memory technologies, along with their related integration challenges, by showing their different layouts, scaling trends and performance/reliability features. Full article
(This article belongs to the Special Issue 3D Flash Memories)
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5594 KiB  
Review
Reliability of NAND Flash Memories: Planar Cells and Emerging Issues in 3D Devices
by Alessandro S. Spinelli, Christian Monzio Compagnoni and Andrea L. Lacaita
Computers 2017, 6(2), 16; https://0-doi-org.brum.beds.ac.uk/10.3390/computers6020016 - 21 Apr 2017
Cited by 67 | Viewed by 23698
Abstract
We review the state-of-the-art in the understanding of planar NAND Flash memory reliability and discuss how the recent move to three-dimensional (3D) devices has affected this field. Particular emphasis is placed on mechanisms developing along the lifetime of the memory array, as opposed [...] Read more.
We review the state-of-the-art in the understanding of planar NAND Flash memory reliability and discuss how the recent move to three-dimensional (3D) devices has affected this field. Particular emphasis is placed on mechanisms developing along the lifetime of the memory array, as opposed to time-zero or technological issues, and the viewpoint is focused on the understanding of the root causes. The impressive amount of published work demonstrates that Flash reliability is a complex yet well-understood field, where nonetheless tighter and tighter constraints are set by device scaling. Three-dimensional NAND have offset the traditional scaling scenario, leading to an improvement in performance and reliability while raising new issues to be dealt with, determined by the newer and more complex cell and array architectures as well as operation modes. A thorough understanding of the complex phenomena involved in the operation and reliability of NAND cells remains vital for the development of future technology nodes. Full article
(This article belongs to the Special Issue 3D Flash Memories)
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