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Selected Papers from the 24th IEEE International Symposium on Asynchronous...
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Selected Papers from the 24th IEEE International Symposium on Asynchronous Circuits and Systems - ASYNC 2018

A special issue of Journal of Low Power Electronics and Applications (ISSN 2079-9268).

Deadline for manuscript submissions: closed (15 December 2018) | Viewed by 19675

Special Issue Editors

Prof. Milos Krstic

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Guest Editor
Design and Test Methodology, University of Potsdam, 14482 Potsdam, Germany
Interests: GALS; asynchronous circuit design; fault tolerance
Dr. Ian W. Jones

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Guest Editor
Oracle Labs, Redwood Shores, CA 94065, USA
Interests: asynchronous circuits; computer architecture; memory systems design; high-speed CMOS Circuits
Prof. Andreas Steininger

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Guest Editor
Department of Computer Engineering, Vienna University of Technology, 1040 Vienna, Austria
Interests: asynchronous logic design; GALS; timing domain crossing; metastability; fault-tolerant/radiation-tolerant computer architecture
Prof. Matthias Függer

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Guest Editor
CNRS & LSV, ENS Paris-Saclay, Université Paris Saclay, France
Interests: theory of distributed algorithms; VLSI circuits; robust algorithms and circuits; distributed computation in dynamic networks; algorithms implemented in silicon; algorithms implemented in (micro)biological systems (bacterial colonies, viruses)

Special Issue Information

Dear Colleagues,

The International Symposium on Asynchronous Circuits and Systems (ASYNC) is the premier forum for researchers to present their latest findings in asynchronous design. For this Special Issue of JLPEA, we invite the authors of the papers published at the ASYNC 2018 conference to submit extended versions of their papers. However, it is also open for other paper submissions in the research field.

Authors are invited to submit papers on any aspect of asynchronous design, ranging from design, synthesis, and test to asynchronous applications. Topics of interest include the following:

  • Asynchronous pipelines, architectures, CPUs, and memories
  • Asynchronous, ultra-low power systems, energy harvesting, and mixed-signal/analogue
  • Asynchrony in emerging technologies, including bio, neural, nano, and quantum computing
  • CAD tools for asynchronous design, synthesis, analysis, and optimization
  • Formal methods for verification and performance/power analysis
  • Test, security, fault tolerance, and radiation hard design
  • Asynchronous variability-tolerant design, resilient design, and design for manufacturing
  • Asynchronous design for neural networks and machine learning applications
  • Asynchronous circuit designs, case studies, comparisons, and applications
  • Mixed-timed circuits, clock domain crossing, GALS systems, Network-on-Chip, and multi-chip interconnects
  • Hardware implementations of asynchronous models and algorithms, asynchronous techniques in clocked designs, and elastic and latency-tolerant synchronous design

The papers will receive a peer review by experts in the field of the paper.

This review process will be single-blind, and the authors should include their names and affiliations on their paper.

Prof. Milos Krstic
Dr. Ian W. Jones
Prof. Andreas Steininger
Prof. Matthias Függer
Guest Editors

Manuscript Submission Information

Manuscripts should be submitted online at www.mdpi.com by registering and logging in to this website. Once you are registered, click here to go to the submission form. Manuscripts can be submitted until the deadline. All submissions that pass pre-check are peer-reviewed. Accepted papers will be published continuously in the journal (as soon as accepted) and will be listed together on the special issue website. Research articles, review articles as well as short communications are invited. For planned papers, a title and short abstract (about 100 words) can be sent to the Editorial Office for announcement on this website.

Submitted manuscripts should not have been published previously, nor be under consideration for publication elsewhere (except conference proceedings papers). All manuscripts are thoroughly refereed through a single-blind peer-review process. A guide for authors and other relevant information for submission of manuscripts is available on the Instructions for Authors page. Journal of Low Power Electronics and Applications is an international peer-reviewed open access quarterly journal published by MDPI.

Please visit the Instructions for Authors page before submitting a manuscript. The Article Processing Charge (APC) for publication in this open access journal is 1800 CHF (Swiss Francs). Submitted papers should be well formatted and use good English. Authors may use MDPI's English editing service prior to publication or during author revisions.

Keywords

  • asynchronous design
  • GALS
  • CAD tools
  • clock-domain crossing

Published Papers (3 papers)

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Research

41 pages, 844 KiB  
Article
Novel Approaches for Efficient Delay-Insensitive Communication
by Florian Huemer and Andreas Steininger
J. Low Power Electron. Appl. 2019, 9(2), 16; https://0-doi-org.brum.beds.ac.uk/10.3390/jlpea9020016 - 06 Apr 2019
Cited by 3 | Viewed by 6650
Abstract
The increasing complexity and modularity of contemporary systems, paired with increasing parameter variabilities, makes the availability of flexible and robust, yet efficient, module-level interconnections instrumental. Delay-insensitive codes are very attractive in this context. There is considerable literature on this topic that classifies delay-insensitive [...] Read more.
The increasing complexity and modularity of contemporary systems, paired with increasing parameter variabilities, makes the availability of flexible and robust, yet efficient, module-level interconnections instrumental. Delay-insensitive codes are very attractive in this context. There is considerable literature on this topic that classifies delay-insensitive communication channels according to the protocols (return-to-zero versus non-return-to-zero) and with respect to the codes (constant-weight versus systematic), with each solution having its specific pros and cons. From a higher abstraction, however, these protocols and codes represent corner cases of a more comprehensive solution space, and an exploration of this space promises to yield interesting new approaches. This is exactly what we do in this paper. More specifically, we present a novel coding scheme that combines the benefits of constant-weight codes, namely simple completion detection, with those of systematic codes, namely zero-effort decoding. We elaborate an approach for composing efficient “Partially Systematic Constant Weight” codes for a given data word length. In addition, we explore cost-efficient and orphan-free implementations of completion detectors for both, as well as suitable encoders and decoders. With respect to the protocols, we investigate the use of multiple spacers in return-to-zero protocols. We show that having a choice between multiple spacers can be beneficial with respect to energy efficiency. Alternatively, the freedom to choose one of multiple spacers can be leveraged to transfer information, thus turning the original return-to-zero protocol into a (very basic version of a) non-return-to-zero protocol. Again, this intermediate solution can combine benefits from both extremes. For all proposed solutions we provide quantitative comparisons that cover the whole relevant design space. In particular, we derive coding efficiency, power efficiency, as well as area effort for pipelined and non-pipelined communication channels. This not only gives evidence for the benefits and limitations of the presented novel schemes—our hope is that this paper can serve as a reference for designers seeking an optimized delay-insensitive code/protocol/implementation for their specific application. Full article
(This article belongs to the Special Issue Selected Papers from the 24th IEEE International Symposium on Asynchronous Circuits and Systems - ASYNC 2018)
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8 pages, 2642 KiB  
Article
A 50.5 ns Wake-Up-Latency 11.2 pJ/Inst Asynchronous Wake-Up Controller in FDSOI 28 nm
by Jean-Frédéric Christmann, Florent Berthier, David Coriat, Ivan Miro-Panades, Eric Guthmuller, Sébastien Thuries, Yvain Thonnart, Adam Makosiej, Olivier Debicki, Frédéric Heitzmann, Alexandre Valentian, Pascal Vivet and Edith Beigné
J. Low Power Electron. Appl. 2019, 9(1), 8; https://0-doi-org.brum.beds.ac.uk/10.3390/jlpea9010008 - 14 Feb 2019
Cited by 3 | Viewed by 6537
Abstract
Due to low activity in Internet of Things (IoT) applications, systems tend to leverage low power modes in order to reduce their power consumption. Normally-off computing thus arose, consisting in having turned off most part of a system’s power supply, while dynamically turning [...] Read more.
Due to low activity in Internet of Things (IoT) applications, systems tend to leverage low power modes in order to reduce their power consumption. Normally-off computing thus arose, consisting in having turned off most part of a system’s power supply, while dynamically turning on components as the application needs it. As wake up sources may be diverse, simple controllers are integrated to handle smart wake up schemes. Therefore, to prevent overconsumption while transitioning to running mode, fast wake up sequences are required. An asynchronous 16-bit Reduced Instruction Set Computer (RISC) Wake-up Controller (WuC) is proposed demonstrating 50.5 [email protected] Million Instructions Per Second (MIPS)@0.6 V wake-up latency, drastically reducing the overall wake-up energy of IoT systems. A clockless implementation of the controller saves the booting time and the power consumption of a clock generator, while providing high robustness to environmental variations such as supply voltage level. The WuC is also able to run simple tasks with a reduced Instruction Set Architecture (ISA) and achieves as low as 11.2 pJ/inst @0.5 V in Fully Depleted Silicon On Insulator (FDSOI) 28 nm. Full article
(This article belongs to the Special Issue Selected Papers from the 24th IEEE International Symposium on Asynchronous Circuits and Systems - ASYNC 2018)
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15 pages, 3430 KiB  
Article
High Level Current Modeling for Shaping Electromagnetic Emissions in Micropipeline Circuits
by Sophie Germain, Sylvain Engels and Laurent Fesquet
J. Low Power Electron. Appl. 2019, 9(1), 6; https://0-doi-org.brum.beds.ac.uk/10.3390/jlpea9010006 - 29 Jan 2019
Viewed by 6108
Abstract
In order to fit circuit electromagnetic emissions within a spectral mask, a design flow based on high level current modeling for micropipeline circuits is proposed. The model produces a quick and rough estimation of the circuit current, thanks to a Timed Petri Net [...] Read more.
In order to fit circuit electromagnetic emissions within a spectral mask, a design flow based on high level current modeling for micropipeline circuits is proposed. The model produces a quick and rough estimation of the circuit current, thanks to a Timed Petri Net determining the activation instants of the different micropipeline stages and an asymmetric Laplace distribution modeling the current peaks of the activated stages. The design flow exploits this current estimation for shaping the electromagnetic emissions by setting the controller delays of the micropipeline circuits. The delay adjustment is performed by a genetic algorithm, which iterates until the electromagnetic emissions match the targeted spectral mask. In order to evaluate the technique, an Advanced Encryption Standard (AES) circuit has been designed. We first observed that the obtained current curve fits well with a gate simulation. Then, after shaping the electromagnetic emissions, the simulation shows that the spectrum fits within the spectral mask. Full article
(This article belongs to the Special Issue Selected Papers from the 24th IEEE International Symposium on Asynchronous Circuits and Systems - ASYNC 2018)
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