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CMOS Low Power Design Vol. 2
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CMOS Low Power Design Vol. 2

A special issue of Journal of Low Power Electronics and Applications (ISSN 2079-9268).

Deadline for manuscript submissions: closed (30 September 2020) | Viewed by 10517

Special Issue Editors

Dr. Aatmesh Shrivastava

E-Mail Website
Guest Editor
Department of Electrical and Computer Engineering, Northeastern University, Boston, MA 02115, USA
Interests: ultra-low power circuits and systems; analog computing; precision circuits; hardware security
Special Issues, Collections and Topics in MDPI journals
Dr. Vishal Saxena

E-Mail Website
Guest Editor
Electrical and Computer Engineering, University of Delaware, Newark, DE 19716, USA
Interests: mixed-signal IC design; cmos photonic ICs; RF/mmwave photonics; neuromorphic circuits
Special Issues, Collections and Topics in MDPI journals

Special Issue Information

Dear Colleagues,

Artificial Intelligence (AI) and Deep Learning are fundamentally transforming the nature of computing and enabling novel cognitive and smart applications. To enable pervasive AI, especially on mobile devices and the Internet of things (IoTs), focus has shifted to realizing low-power Edge-AI hardware. Edge-AI is expected to enable locality of computing, reduced dependence on wireless and Cloud infrastructure, and consequently, privacy of user data.

Edge-AI hardware encompasses several aspects of low-power circuit design which exploit novel devices, circuits, and system architectures to realize high energy-efficiency. Event-driven asynchronous circuits enable low power consumption, while emerging post-CMOS nonvolatile memory devices promise very high-density in-memory computing with reduction in energy per synaptic operation. At the same time, digital architectures and field-programmable gate arrays (FPGAs) leverage approximate computing algorithms and partial reconfiguration to trade off energy efficiency with precision. Novel sensor interfaces and security of such devices will be essential for widespread deployment of Edge-AI.

Authors are invited to submit regular papers following the JLPEA submission guidelines within the remit of the second volume of the Special Issue call. Topics include but are not limited to:

  • Low-power digital, analog or mixed-signal circuits for the realization of machine learning and neural network algorithms;
  • In-memory computing using conventional and emerging memory arrays; vector–matrix multipliers for neural network computations;
  • Approximate and reconfigurable computing architectures for Edge-AI;
  • Neural-inspired or neuromorphic computing circuits and architectures using CMOS, post-CMOS technologies, emerging neuromorphic processors, and FPGAs;
  • Low-power on-chip communication circuits and/or network-on-chip (NoC) for low-latency data transfer for Edge-AI and neuromorphic computing;
  • Low-power sensor interfaces for IoTs and Edge-AI;
  • Circuits and architectures for privacy, authentication, and security for Edge-AI and IoTs.

Dr. Aatmesh Shrivastava
Dr. Vishal Saxena
Guest Editor

Manuscript Submission Information

Manuscripts should be submitted online at www.mdpi.com by registering and logging in to this website. Once you are registered, click here to go to the submission form. Manuscripts can be submitted until the deadline. All submissions that pass pre-check are peer-reviewed. Accepted papers will be published continuously in the journal (as soon as accepted) and will be listed together on the special issue website. Research articles, review articles as well as short communications are invited. For planned papers, a title and short abstract (about 100 words) can be sent to the Editorial Office for announcement on this website.

Submitted manuscripts should not have been published previously, nor be under consideration for publication elsewhere (except conference proceedings papers). All manuscripts are thoroughly refereed through a single-blind peer-review process. A guide for authors and other relevant information for submission of manuscripts is available on the Instructions for Authors page. Journal of Low Power Electronics and Applications is an international peer-reviewed open access quarterly journal published by MDPI.

Please visit the Instructions for Authors page before submitting a manuscript. The Article Processing Charge (APC) for publication in this open access journal is 1800 CHF (Swiss Francs). Submitted papers should be well formatted and use good English. Authors may use MDPI's English editing service prior to publication or during author revisions.

Keywords

  • Ultra-low power
  • Edge-AI
  • Neuromorphic computing
  • IoTs
  • Mixed-signal
  • Emerging devices
  • In-memory computing
  • Hardware security

Published Papers (2 papers)

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15 pages, 1995 KiB  
Article
AxCEM: Designing Approximate Comparator-Enabled Multipliers
by Samar Ghabraei, Morteza Rezaalipour, Masoud Dehyadegari and Mahdi Nazm Bojnordi
J. Low Power Electron. Appl. 2020, 10(1), 9; https://0-doi-org.brum.beds.ac.uk/10.3390/jlpea10010009 - 01 Mar 2020
Cited by 2 | Viewed by 5168
Abstract
Floating-point multipliers have been the key component of nearly all forms of modern computing systems. Most data-intensive applications, such as deep neural networks (DNNs), expend the majority of their resources and energy budget for floating-point multiplication. The error-resilient nature of these applications often [...] Read more.
Floating-point multipliers have been the key component of nearly all forms of modern computing systems. Most data-intensive applications, such as deep neural networks (DNNs), expend the majority of their resources and energy budget for floating-point multiplication. The error-resilient nature of these applications often suggests employing approximate computing to improve the energy-efficiency, performance, and area of floating-point multipliers. Prior work has shown that employing hardware-oriented approximation for computing the mantissa product may result in significant system energy reduction at the cost of an acceptable computational error. This article examines the design of an approximate comparator used for preforming mantissa products in the floating-point multipliers. First, we illustrate the use of exact comparators for enhancing power, area, and delay of floating-point multipliers. Then, we explore the design space of approximate comparators for designing efficient approximate comparator-enabled multipliers (AxCEM). Our simulation results indicate that the proposed architecture can achieve a 66% reduction in power dissipation, another 66% reduction in die-area, and a 71% decrease in delay. As compared with the state-of-the-art approximate floating-point multipliers, the accuracy loss in DNN applications due to the proposed AxCEM is less than 0.06%. Full article
(This article belongs to the Special Issue CMOS Low Power Design Vol. 2)
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22 pages, 3039 KiB  
Article
An Acoustic Vehicle Detector and Classifier Using a Reconfigurable Analog/Mixed-Signal Platform
by Swagat Bhattacharyya, Steven Andryzcik and David W. Graham
J. Low Power Electron. Appl. 2020, 10(1), 6; https://0-doi-org.brum.beds.ac.uk/10.3390/jlpea10010006 - 20 Feb 2020
Cited by 9 | Viewed by 4756
Abstract
The wireless sensor nodes used in a growing number of remote sensing applications are deployed in inaccessible locations or are subjected to severe energy constraints. Audio-based sensing offers flexibility in node placement and is popular in low-power schemes. Thus, in this paper, a [...] Read more.
The wireless sensor nodes used in a growing number of remote sensing applications are deployed in inaccessible locations or are subjected to severe energy constraints. Audio-based sensing offers flexibility in node placement and is popular in low-power schemes. Thus, in this paper, a node architecture with low power consumption and in-the-field reconfigurability is evaluated in the context of an acoustic vehicle detection and classification (hereafter “AVDC”) scenario. The proposed architecture utilizes an always-on field-programmable analog array (FPAA) as a low-power event detector to selectively wake a microcontroller unit (MCU) when a significant event is detected. When awoken, the MCU verifies the vehicle class asserted by the FPAA and transmits the relevant information. The AVDC system is trained by solving a classification problem using a lexicographic, nonlinear programming algorithm. On a testing dataset comprising of data from ten cars, ten trucks, and 40 s of wind noise, the AVDC system has a detection accuracy of 100%, a classification accuracy of 95%, and no false alarms. The mean power draw of the FPAA is 43 μ W and the mean power consumption of the MCU and radio during its validation and wireless transmission process is 40.9 mW. Overall, this paper demonstrates that the utilization of an FPAA-based signal preprocessor can greatly improve the flexibility and power consumption of wireless sensor nodes. Full article
(This article belongs to the Special Issue CMOS Low Power Design Vol. 2)
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