A Single-Voltage-Source Class-D Boost Multi-Level Inverter with Self-Balanced Capacitors

Abstract

A symmetric single-source 7-level DC-AC converter with voltage gain of 3 and self-voltage balance is presented by combining the Class-D amplifier and the diode-clamped DC-AC converter. There is only one switch is switched for any time in this circuit. As a result, the conversion efficiency can be upgraded significantly as well as the control strategy can be simplified considerably. In the paper, the operation principle and circuit design of this converter are analyzed in detail, and its feasibility and effectiveness are verified by simulation and digital control, respectively.

1. Introduction

With the rapid development of technology and power electronics in recent years [1], a large amount of low-frequency harmonic currents, generated by the non-linear loads of power electronics, flow into the power system, resulting in increasingly serious harmonic pollution of the power system. As the generated harmonic is larger or exceeds the tolerance value, it may cause other nearby non-linear load products to mis-activate, mis-measure, degrade efficiency or even burn out. The International Electrotechnical Commission (IEC) in Europe has issued IEC 61000-3-2 Harmonic Specification [2], and the Japanese Specifications have also issued JIS-C-61000-3-2 standard [3] has been promulgated by the Japanese Specifications to formally regulate the harmonics generated by electronic devices.

In order to cope with the AC systems used in the market, DC-AC converters or AC-DC converters combined with DC-AC converters are used to convert the green energy to AC power. Therefore, DC-AC converters are one of the most important technologies used in the industry today. Multi-level DC-AC converters use switching paths to make the output voltage appear in a hierarchical pattern and increase the number of levels or filters to make the output voltage appear like a sine wave. The output voltage of the multistage DC-AC converter is in the form of a stratified output voltage so that the voltage stress on the switch can be clamped. Therefore, the high-voltage AC output can be achieved with the switch with the low-voltage stress. Figure 1 shows the generalized classification of voltage-type multi-stage DC-AC converters, which contain neutral point clamped converters [4], the flywheel capacitor type [5] and the series-connected type [5].

Flying capacitors are DC-AC converters that use multiple capacitors connected to each other to achieve output voltage clamping. However, a large number of capacitors and complex control methods are required to balance the capacitor voltage to achieve a hierarchical output voltage [5].

Although the cascade structure has the characteristics of modular design and floating power supply, it requires multiple independent power inputs to achieve a hierarchical AC output voltage [5].

The circuit structure presented in [4] uses diodes and switches to create a neutral potential for the output voltage, which has a lower harmonic content than the conventional two-level DC-AC converter. The pulse width modulation (PWM) method proposed in [6] is based on the comparison of sine and triangle waves to generate suitable driving signals to turn on/off switches, which in turn make the output voltage appear in the form of a sine wave.

Studies referenced in [7,8] propose a neutral point clamping circuit. The circuit structure presented in [7] consists of six switches and a floating capacitor to realize a DC-AC converter with a voltage gain of 1 at 5 levels. The circuit structure presented in [8] is similar to that of [7] and adopts nine switches to realize a DC-AC converter with a voltage gain of 1.5 at 7 levels. By adding two additional switches and one floating capacitor, a DC-AC converter with a voltage gain of 1 at 9 levels can be realized with eleven switches, two DC link capacitors, and two floating capacitors. At the same time, with the same number of components, a DC-AC converter with a voltage gain of 2.5 at 11 levels can be realized by only changing the switching sequence. The literature [9] proposes a circuit that can operate in a reactive power condition by combining the concept of diode clamping, flywheel capacitor, and T-type active clamping to design a DC-AC converter with a voltage gain of 0.5 at 5 levels.

In [10], a step-up converter is used to provide the required step voltage for the H-bridge output. This approach not only achieves the purpose of the DC step-up voltage but also uses the inductor of this circuit as the input inductor to reduce the input current ripple. In addition, in [10], a 5-, 7-, and 15-level circuit structure is proposed to realize the high-level AC output and applied to the fuel cell system. In [11,12], floating capacitors are used to increase the number of levels of the DC-AC converter. This circuit structure can be used to increase the voltage gain with a single power input, but the floating capacitor must be self-balanced to output the step voltage. The structure proposed in [11] uses two floating capacitors and two diodes along with the required switching sequence to achieve self-balancing of the capacitors, resulting in a voltage gain of 2 at nine levels. In [12], a circuit with three floating capacitors and three diodes is presented, and the capacitor voltage is one to two times the input voltage, so the number of output levels can reach nine with a voltage gain of 4. However, this method will increase the voltage stress on the switch, so a higher specification switch is required. In [13], a modified pulse width modulation control method is proposed to combine the active clamping circuit with the H-bridge structure so that the capacitor voltage across the H-bridge can maintain self-balance in each level.

Therefore, based on the Class-D amplifier and the traditional diode clamped DC-AC converter, a single-voltage-source symmetric two-output-port 7-level DC-AC converter along with only one switch is switched for any time in this circuit is presented. As a result, not only the proposed converter can possess a 3-voltage-gain and the adopted capacitors with the inherent capability of self-voltage balance, but also the conversion efficiency can be upgraded significantly as well as the control strategy can be simplified greatly. In addition, due to the symmetric structure, the interchangeability of mass production of this converter can be easily realized. In the paper, the feasibility of the proposed circuit is demonstrated by simulating a 300 W prototype circuit, and the effectiveness of this prototype circuit is confirmed by using a single comparator PWM voltage feedback control [14] based on the field programmable gate array (FPGA).

2. Operating Principles of the Proposed Circuit

Figure 2 shows the proposed single-voltage-source class-D 7-level DC-AC converter. This converter is composed of 12 switches, 8 diodes, and 4 energy-transferring capacitors.

Before the operating analysis, a brief description of the relevant symbol definitions and required assumptions is given: (1) V_in is the input voltage, v_o is the output voltage, and the voltage v_Co of the filter capacitor C_o is equal to v_o; (2) S₁ to S₁₂ are the switches with the corresponding cross-voltages v_ds1 to v_ds12; (3) D₁ to D₈ are diodes with the corresponding cross-voltages, v_D1 to v_D8; (4) C₁ to C₄ are energy-transferring capacitors with the corresponding currents i_C1 to i_C4; (5) the values of the energy-transferring capacitors are assumed to be large enough that the voltages across them can be considered constant, i.e., V_C1 = V_C2 = V_C3 = V_C4; (6) i_o is the output current; (7) i_L is the current flowing through inductors L₁ and L₂; and (8) all components are regarded as idea except for the body diodes of the switches.

Figure 3 shows the waveforms of the gate driving signals for switches. Since the gate driving signals are the same at the positive and negative half cycles, only the positive half-cycle is analyzed. The circuit operation behavior has five stages, only one switch will be in PWM switching in each stage, and the other switches are normally on or normally off. Since stage I is equivalent to stage V and stage II is equivalent to stage IV, only stages I, II, and III are analyzed.

When the output voltage is at the positive half cycle, the switches S₄, S₉, and S₁₂ remain on, and the switches S₂, S₅, S₆, S₇, S₈, and S₁₁ remain off. The output voltage can be determined by switching S₁, S₃, and S₁₀ to determine the circuit operation behavior of stages I, II, and III, respectively. Note that in the following descriptions, only one switch is switched at any time, and the current path is marked to show that the converter satisfies energy conservation and Kirchhoff’s voltage and current laws in any stage.

2.1. Stage I

Only the switch S₁ is switched as in Figure 4.

Interval $\left[t_0\le t\le t_1\right]$: The switch S₁ is on, but the switches S₃ and S₁₀ are off. As shown in Figure 5, the current flowing through the inductors L₁ and L₂ will form a circuit loop from the input voltage to the switches S₁, S₄, S₉, S₁₂ and the diodes D₂, D₇; therefore, the voltage across the terminals A and B is

$$v_{AB}=V_{in}$$

(1)

Interval $\left[t_1\le t\le t_2\right]$: The switches S₁, S₃ and S₁₀ are all off. At the same time, the input voltage is disconnected from the output. As shown in Figure 6, the current flowing through the inductors L₁ and L₂ will form a circuit loop from the switches S₄, S₉, S₁₂ to the diodes D₂, D₇ and the body diode of the switch S₂, so the voltage across the terminals A and B is

$$v_{AB}=0$$

(2)

2.2. Stage II

Only the switch S₃ is switched as in Figure 7.

Interval $\left[t_3\le t\le t_4\right]$: The switches S₁ and S₃ are on, but the switch S₄ is off. As shown in Figure 8, the current flowing through the inductors L₁ and L₂ will form a circuit loop from the input voltage to S₁, S₃, S₄, S₉, S₁₂ and the diode D₇; therefore, the voltage across the terminals A and B is

$$v_{AB}=V_{in}+V_{C1}=2V_{in}$$

(3)

Interval $[t_4\le t\le t_5]$: The switches S₃ and S₁₀ are off, but the switch S₁ is on. As shown in Figure 9, the current flowing through the inductors L₁ and L₂ will form a circuit loop from the input voltage to the switches S₁, S₄, S₉, S₁₂ and the diodes D₂, D₇; therefore, the voltage across the terminals A and B is

$$v_{AB}=V_{in}$$

(4)

2.3. Stage III

Only the switch S₁₀ is switched as in Figure 10.

Interval $[t_6\le t\le t_7]$: The switches S₁, S₃ and S₁₀ are turned on. As shown in Figure 11, the current flowing through the inductors L₁ and L₂ will form a circuit loop from the input voltage to the switches S₁, S₃, S₄, S₉, S₁₀ and S₁₂; therefore, the voltage across the terminals A and B is

$$v_{AB}=V_{in}+V_{C1}+V_{C4}=3V_{in}$$

(5)

Interval $[t_7\le t\le t_8]$: The switch S₁₀ is off, but the switches S₁ and S₃ are on. As shown in Figure 12, the current flowing through the inductors L₁ and L₂ will form a circuit loop from the input voltage to the switches S₁, S₃, S₄, S₉, S₁₂ and the diode D₇; therefore, the voltage across the terminals A and B is

$$v_{AB}=V_{in}+V_{C1}=2V_{in}$$

(6)

From the above analysis, we can see that the proposed 7-level DC-AC converter has the voltage gain of 3, which can be obtained based on (7):

$$\mathrm{Voltage} \mathrm{Gain}=\frac{\mathrm{AC} \mathrm{output} \mathrm{voltage} \mathrm{amplitude}}{\mathrm{Total} \mathrm{DC} \mathrm{input} \mathrm{voltage}}$$

(7)

Table 1. Switching behavior of the proposed 7-level DC-AC inverter.

		S1	S3	S4	S9	S10	S12
Switching Frequency		fpwm	fpwm	fline	fline	fpwm	fline
Stage I	Switching type	1, 0	0	1	1	0	1
	Maximum voltage stress	Vin	Vin	0	0	Vin	0
Stage II	Switching type	1	1, 0	1	1	0	1
	Maximum voltage stress	0	Vin	0	0	Vin	0
Stage III	Switching type	1	1	1	1	1, 0	1
	Maximum voltage stress	0	0	0	0	Vin	0

shows the switching behavior of the proposed single voltage source Class-D 7-level DC-AC converter and its corresponding maximum voltage stress, where f_PWM is the switching frequency and f_line is the output voltage frequency or mains frequency. For the output voltage at positive half cycle to be considered, the switches S₂, S₅, S₆, S₇, S₈ and S₁₁ are off, their maximum voltage stress is V_in. In addition, all the diodes have the maximum voltage stress of V_in.

Table 1 shows the switching behavior of the proposed single voltage source Class-D 7-level DC-AC converter and its corresponding maximum voltage stress. In addition, the switches S₁, S₃ and S₁₀ take important roles in stages I, II and III.

3. Design Considerations

The specifications of the proposed 7-level DC-AC converter are shown in

Table 2. Specifications of the 7-level DC-AC converter.

Input voltage (Vin)	56 V
Output voltage (mains) frequency (fline)	60 Hz
Output voltage (vo)	110 Vrms
Rated output power (Po,rated)/Rated output current (Io,rated)	300 W/2.72 Arms
Minimum output power (Po,min)/Minimum output current (Io,min)	75 W/0.68 Arms
Switching frequency (fs)	60 kHz

.

3.1. Design of Energy-Transferring Capacitors

The energy-transferring capacitors used in the proposed converter can be divided into two types according to the discharge time. The first one is the capacitor C₁ (=C₃) which provides the AC output of stage II and stage III, whereas the second one is the capacitor C₄ (=C₂) which provides the AC output of stage III. Therefore, based on the concept from Figure 13 and by using Equations (8) and (9), the charge discharged from C₁ and C₄ over one cycle of the mains power can be calculated:

$$\Delta Q_{C1}=\frac{1}{\omega }{\displaystyle {\int }_{\frac{2\pi \cdot t_1}{T_{line}}}^{\pi -\frac{2\pi \cdot t_1}{T_{line}}}{i}_o{}_{ }\sin ({\omega }_{ }t)d{\omega }_{ }t}$$

(8)

$$\Delta Q_{C4}=\frac{1}{\omega }{\displaystyle {\int }_{\frac{2\pi \cdot t_2}{T_{line}}}^{\pi -\frac{2\pi \cdot t_2}{T_{line}}}{i}_o{}_{ }\sin ({\omega }_{ }t)d{\omega }_{ }t}$$

(9)

According to (10), the voltage variation is proportional to the charge variation. Since the results of (8) and (9) can be obtained by PSIM simulation, the value of the capacitor can be worked out under a given voltage ripple percentage of 10% as below:

$$Q=CV\Rightarrow \Delta Q=C\Delta V\Rightarrow C=\frac{\Delta Q}{\Delta V}$$

(10)

$$\Delta V=56\times 10\%=5.6 \mathrm{V}$$

(11)

$$C_1=C_3=\frac{\Delta Q_1}{\Delta V}=\frac{17.548 \mathrm{m}}{5.6}=3.13 \mathrm{mF}$$

(12)

$$C_4=C_2=\frac{\Delta Q_4}{\Delta V}=\frac{8.52 \mathrm{m}}{5.6}=1.52 \mathrm{mF}$$

(13)

Therefore, a 3.3 mF electrolytic capacitor is used for each capacitor, which has the voltage across it is equal to the input voltage. Since the derating of the electrolytic capacitor should be taken into considered, the voltage rating of the selected capacitor should be at least 1.25 times the input voltage, according to the usual thumb rule. Finally, a 3300 μF/100 V Rubycon electrolytic capacitor is chosen as each capacitor.

3.2. Design of the Filter

According to the harmonic voltage limit value proposed by IEEE 519-1992, the total harmonic distortion rate is up to 5% below 69 kV [15]. The proposed structure is a 7-level DC-AC converter with a double-ended symmetrical output, which has a filter shown in Figure 14. As generally known, the inductance has higher reactance for high frequency signals, whereas the capacitance has lower reactance for high frequency signals. Therefore, dividing the inductance of LC filter into L₁ and L₂ not only makes the differential-mode noise filtered by inductance and capacitance and not appear on the output load R_o, but also prevents the common-mode noise from affecting the circuit. Since the switching frequency f_s is 60 kHz, the corner frequency f_c is set at 6 kHz.

The transfer function of the filter is shown in Equation (14), where $L=L_1+L_2$:

$$H\left(s\right)=\frac{{\omega }_o}{s^2+s\frac{Q}{{\omega }_o}+{\omega }_{{}_o}^2}$$

(14)

In (14), we can find

$${\omega }_o=2\pi f_o=\sqrt{\frac{1}{L{C}_o}}$$

(15)

and

$$Q=R_o\sqrt{\frac{C_o}{L}}$$

(16)

Therefore, since f_c is 6 kHz, one relationship between L and C_o can be obtained based on (15):

$$L{C}_o={\left(\frac{1}{2\pi \times f_c}\right)}^2={\left(\frac{1}{2\pi \times 6\mathrm{k}}\right)}^2=0.703\mathrm{n}$$

(17)

Additionally, by rearranging (16), the following equation can be obtained to be

$$\frac{C_o}{L}={\left(\frac{Q}{R_o}\right)}^2$$

(18)

Let the quality factor at rated load be 3 dB, that is, $\sqrt{2}$, and the output resistance R_o at rated load is 39.24 Ω. By substituting these values into (18), the other relationship between L and C_o can be obtained to be

$$\begin{array}{l}\frac{C_o}{L}={\left(\frac{\sqrt{2}}{39.24}\right)}^2=1.3 \mathrm{m}\\ \Rightarrow C_o=L\times 1.3 \mathrm{m}\end{array}$$

(19)

Substituting (19) into (17) yields

$$L=\sqrt{\frac{0.703\mathrm{n}}{1.3\mathrm{m}}}=735.37 \mathsf{\mu }\mathrm{H}$$

(20)

By substituting (20) into (19), the output capacitance can be obtained to be

$$C_o=955\mathrm{nF}$$

(21)

Finally, a 1 μF/275 V metal film capacitor is chosen as filter capacitor. The actual measured capacitance of 1.02 μF, which is brought into (17) to obtain the filter inductance of 690 μH. Since the filter inductor L is composed of two inductors L₁ and L₂ connected in series, the values of L₁ and L₂ are the same, equal to 345 μH.

4. System Block Diagram

Figure 15 shows the system block diagram of the proposed DC-AC converter. The system consists of the main circuit and feedback control circuit. The FPGA digital control core and digital-to-analog converter (DAC) are used to generate a sine wave used as voltage reference, and the ADC-free sampling circuit [14] sends the feedback signal v_FB to the FPGA to obtain the corresponding control force after calculation. This control force is then fed to the isolated gate driver to regulate the switch to achieve a stable output voltage.

5. Simulated and Experimental Results along with Discussions

Figure 16 shows the simulated and experimental waveforms of the proposed 7-level DC-AC converter at rated load, containing the output voltage v_o and output current i_o, the unfiltered output voltage v_PWM, and the voltages across C₁, C₂, C₃ and C₄, called V_C1, V_C2, V_C3 and V_C4. From Figure 16a, it can be seen that the output voltage v_o and output current i_o are AC output. From Figure 16b, it can be seen that the unfiltered output voltage v_PWM, formed by the high-frequency gate driving signals to turn on and off the switches, is filtered to obtain 60 Hz AC voltage. From Figure 16c,d, it can be seen that all the energy-transferring capacitors in the circuit have the characteristics of self-voltage balance. From the above simulated and experimental results, it can be seen that the proposed 7-level DC-AC converter structure is indeed feasible.

Figure 17 and Figure 18 show the distribution of voltage harmonics at rated and minimum load, respectively. The corresponding total harmonic distortion (THD) is 2.75% and 4.1% at rated and minimum load, respectively, as measured by a power meter. The proposed 7-level DC-AC converter can indeed comply with the specifications of IEEE 519-1992, which states that the corresponding THD is less than 5%. Figure 19 displays the load transient response due to step load current change from 25% to 100% load. From this figure, it can be seen that the overshoot voltage is about 50 V and the recovery time is about 0.6 ms.

The efficiency of the proposed inverter under different loads is measured as shown in Figure 20. First, two digital meters, named Fluke 179, are used to measure the input voltage and the voltage across the current-detecting resistor, named shunt. Then, the output voltage, output current, total harmonic distortion, and harmonic voltage of each harmonic order are measured by using a power analyzer (PM1000+). Therefore, the input power and output power can be obtained. Moreover, the AC electronic load, named Prodigit 3255, is used at the load side. Finally, the obtained input power and output power are used to calculate the efficiency as shown in Figure 21. As can be seen in Figure 21, the proposed converter circuit belongs to a diode clamped circuit, causing the efficiency to be decreased when the load is higher.

6. Conclusions

This paper combines the Class-D amplifier and the conventional diode clamped DC-AC converter to create a single-voltage-source 3-voltage-gain 7-level DC-AC converter, where the DC link capacitors of the diode clamped DC-AC converter are used as energy-transferring capacitors to increase the output voltage and the number of levels. Due to the structure of this converter is symmetrical up and down, left and right, the interchangeability of mass production can be easily achieved. Furthermore, since only one switch operates at any time, not only the corresponding control is quite easy, but also any switch has very low switching voltage stress equal to the input voltage. Moreover, the proposed DC-AC converter has the highest conversion efficiency of 97.9% and the minimum THD of 2.75%, respectively.