An 8–12.5-GHz LC PLL with Dual VCO and Noise-Reduced LDO Regulator for Multilane Multiprotocol SerDes in 28-nm CMOS Technology
Marat V. Yuldashev
Round 1
Reviewer 1 Report
Good paper, interesting circuit design. No theorems =)
- Check that all abbreviations are explained (e.g. SerDes, VCO, FIFO)
- Figures are not readable
- No theoretical attainments
- Please provide full simulation model (e.g. github reference) for easy reproducibility
Author Response
Please see the attachment.
Author Response File: 
Author Response.pdf
Reviewer 2 Report
This paper presents a LC-PLL with dual VCO and a noise reduced LDO which was used in a 4-lane multi-protocol serial link applications. The study is interesting, but the manuscript is missing many important details. The authors need to make a major revision and address the issues below, before this manuscript can be reconsidered for publication.
(1) The manuscript has many grammatical mistakes and typographic errors. For example, on Page 1, line 25-27, there is a verb missing in the sentence. Please proof-read the manuscript thoroughly - there are missing words, non-capitalized words (such as PLL written as pll) in several places in the manuscript. The abstract and conclusion also have several errors.
(2) Authors should provide the full meaning of the abbreviations for the first occurrence in the manuscript, such as - LC VCO, LDO, FIFO, CMOS, BGR, etc.
(3) Following Figure 1, the authors should give a brief description of each block in this figure.
(4) The authors need to explain/describe the layout in Figure 2, and also label major components in the figure.
(5) The authors did not show they arrived at the 3.06 and 13.2 nV/sqrt(Hz) @ 1 MHz noise levels for their design and traidional design, respectively. They did provide equation (2) and (3), but how these equations were evaluated (i.e. which values were used), should be clarified.
(6) Authors need to provide details of the simulation, what parameters were used in the simulation.
(7) The authors showed experimental results, but only mentioned the E5052B signal source analyzer. Did they fabricate the device? If so, details should be provided. Also the experimental setup for these measurements should be discussed.
Author Response
Please see the attachment.
Author Response File: Author Response.pdf
Round 2
Reviewer 2 Report
The authors have adequately addressed all the concerns raised in the previous review. I recommend publishing this manuscript without any additional modification.
